TI1 LPV521MG Rrio, cmos input, operational amplifier Datasheet

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LPV521
SNOSB14D – AUGUST 2009 – REVISED DECEMBER 2014
LPV521 NanoPower, 1.8-V, RRIO, CMOS Input, Operational Amplifier
1 Features
3 Description
•
The LPV521 is a single nanopower 552-nW amplifier
designed for ultra long life battery applications. The
operating voltage range of 1.6 V to 5.5 V coupled
with typically 351 nA of supply current make it well
suited for RFID readers and remote sensor
nanopower applications. The device has input
common mode voltage 0.1 V over the rails,
guaranteed TCVOS and voltage swing to the rail
output performance. The LPV521 has a carefully
designed CMOS input stage that outperforms
competitors with typically 40 fA IBIAS currents. This
low input current significantly reduces IBIAS and IOS
errors introduced in megohm resistance, high
impedance photodiode, and charge sense situations.
The LPV521 is a member of the PowerWise™ family
and has an exceptional power-to-performance ratio.
1
For VS = 5 V, Typical Unless Otherwise Noted
– Supply Current at VCM = 0.3 V 400 nA (Max)
– Operating Voltage Range 1.6 V to 5.5 V
– Low TCVOS 3.5 µV/°C (Max)
– VOS 1 mV (Max)
– Input Bias Current 40 fA
– PSRR 109 dB
– CMRR 102 dB
– Open-Loop Gain 132 dB
– Gain Bandwidth Product 6.2 kHz
– Slew Rate 2.4 V/ms
– Input Voltage Noise at f = 100 Hz 255 nV/√Hz
– Temperature Range −40°C to 125°C
The wide input common mode voltage range,
guaranteed 1 mV VOS and 3.5 µV/°C TCVOS enables
accurate and stable measurement for both high-side
and low-side current sensing.
2 Applications
•
•
•
•
•
•
•
•
Wireless Remote Sensors
Powerline Monitoring
Power Meters
Battery Powered Industrial Sensors
Micropower Oxygen sensor and Gas Sensor
Active RFID Readers
Zigbee Based Sensors for HVAC Control
Sensor Network Powered by Energy Scavenging
EMI protection was designed into the device to
reduce sensitivity to unwanted RF signals from cell
phones or other RFID readers.
The LPV521 is offered in the 5-pin SC70 package.
Device Information(1)
PART NUMBER
LPV521
PACKAGE
BODY SIZE (NOM)
SC70 (5)
2.00 mm x 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Nanopower Supply Current
SUPPLY CURRENT (nA)
125°C
800
700
600
500
400
300
200
100
0
85°C
25°C
-40°C
VCM = VS ± 0.3V
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV521
SNOSB14D – AUGUST 2009 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
3
3
4
4
4
5
6
7
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
1.8-V DC Electrical Characteristics...........................
1.8-V AC Electrical Characteristics ...........................
3.3-V DC Electrical Characteristics...........................
3.3-V AC Electrical Characteristics ...........................
5-V DC Electrical Characteristics..............................
5-V AC Electrical Characteristics ............................
Typical Characteristics ............................................
Detailed Description ............................................ 19
7.1
7.2
7.3
7.4
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
19
19
Applications and Implementation ...................... 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 21
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 27
11.1
11.2
11.3
11.4
11.5
Device Support ....................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (Feburary 2013) to Revision D
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SNOSB14D – AUGUST 2009 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
SC70-5 Top View
1
5
OUT
V
-
+
V
2
+
-
3
4
IN-
IN+
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
OUT
O
Output
2
V-
P
Negative Power Supply
3
IN+
I
Noninverting Input
4
IN-
I
Inverting Input
5
V+
P
Positive Power Supply
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
−0.3
6
V
V– – 0.3 V
V+ + 0.3 V
V
40
mA
Differential Input Voltage (VIN+ - VIN-)
–300
300
mV
Junction Temperature (2)
–40
150
°C
260
°C
260
°C
150
°C
Any pin relative to VIN+, IN-, OUT Pins
+
-
V , V , OUT Pins
Mounting Temperature
Infrared or Convection (30 sec.)
Wave Soldering Lead Temp. (4 sec.)
−65
Storage temperature, Tstg
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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LPV521
SNOSB14D – AUGUST 2009 – REVISED DECEMBER 2014
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6.3 Recommended Operating Conditions (1)
MIN
MAX
UNIT
Temperature Range (2)
−40
125
°C
Supply Voltage (VS = V+ - V−)
1.6
5.5
V
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see Electrical Characteristics.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.4 Thermal Information
DCK
THERMAL METRIC (1)
RθJA
(1)
(2)
Junction-to-ambient thermal resistance
UNIT
5 PINS
(2)
456
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.5 1.8-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ. (1)
PARAMETER
VOS
Input Offset Voltage
TEST CONDITIONS
VCM = 0.3 V
Temperature extremes
VCM = 1.5 V
TCVOS
IBIAS
Input Offset Voltage Drift
–1
0.1
–1.23
–1
Temperature extremes
–1.23
Temperature extremes
–3
Input Offset Current
CMRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Common Mode Voltage Range
0.1
–1
(1)
(2)
4
Large Signal Voltage Gain
1
3
0.01
1
50
10
66
Temperature extremes
60
0 V ≤ VCM ≤ 0.7 V
75
Temperature extremes
74
1.2 V ≤ VCM ≤ 1.8 V
75
Temperature extremes
53
1.6 V ≤ V+ ≤ 5.5 V
VCM = 0.3 V
85
Temperature extremes
76
CMRR ≥ 67 dB
CMRR ≥ 60 dB
mV
1.23
–50
0 V ≤ VCM ≤ 1.8 V
UNIT
1
1.23
μV/°C
pA
fA
92
101
dB
120
dB
109
0
0
V
1.8
Temperature extremes
AVOL
MAX
±0.4
Input Bias Current
IOS
CMVR
TYP
(2)
Temperature extremes
PSRR
MIN
1.8
VO = 0.5 V to 1.3 V
RL = 100 kΩ to V+/2
74
Temperature extremes
73
125
dB
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
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1.8-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
VO
Output Swing High
TEST CONDITIONS
MIN
+
RL = 100 kΩ to V /2
VIN(diff) = 100 mV
TYP
MAX
2
50
Temperature extremes
Output Swing Low
50
RL = 100 kΩ to V+/2
VIN(diff) = −100 mV
2
Temperature extremes
Sourcing, VO to V–
VIN(diff) = 100 mV
IO
Output Current (3)
Sinking, VO to V+
VIN(diff) = −100 mV
Supply Current
3
0.5
1
Temperature extremes
IS
mA
3
0.5
VCM = 0.3 V
345
Temperature extremes
400
580
VCM = 1.5 V
472
Temperature extremes
(3)
mV from
either rail
50
1
Temperature extremes
50
UNIT
nA
600
850
The short circuit test is a momentary open-loop test.
6.6 1.8-V AC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
GBW
Gain-Bandwidth Product
CL = 20 pF, RL = 100 kΩ
6.1
SR
Slew Rate
AV = +1,
VIN = 0V to 1.8V
Falling Edge
2.9
Rising Edge
2.3
MAX
UNIT
kHz
V/ms
θm
Phase Margin
CL = 20 pF, RL = 100 kΩ
72
deg
Gm
Gain Margin
CL = 20 pF, RL = 100 kΩ
19
dB
en
Input-Referred Voltage Noise Density
f = 100 Hz
265
nV/√Hz
Input-Referred Voltage Noise
0.1 Hz to 10 Hz
Input-Referred Current Noise
f = 100 Hz
In
(1)
24
μVPP
100
fA/√Hz
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
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SNOSB14D – AUGUST 2009 – REVISED DECEMBER 2014
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6.7 3.3-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ. (1)
PARAMETER
VOS
Input Offset Voltage
TEST CONDITIONS
VCM = 0.3 V
Temperature extremes
VCM = 3 V
TCVOS
IBIAS
Input Offset Voltage Drift
Input Offset Current
CMRR
Common Mode Rejection Ratio
VO
0.1
–1
–1.23
Temperature extremes
–3
Power Supply Rejection Ratio
Common Mode Voltage Range
Large Signal Voltage Gain
Output Swing High
0.1
–1
3
0.01
IS
Output Current (3)
Supply Current
20
72
Temperature extremes
70
0 V ≤ VCM ≤ 2.2 V
78
Temperature extremes
75
2.7 V ≤ VCM ≤ 3.3 V
77
Temperature extremes
76
1.6 V ≤ V+ ≤ 5.5 V
VCM = 0.3 V
85
Temperature extremes
76
CMRR ≥ 72 dB
CMRR ≥ 70 dB
106
121
109
dB
0
3.3
Temperature extremes
76
RL = 100 kΩ to V+/2
VIN(diff) = 100 mV
dB
Temperature extremes
4
Sinking, VO to V+
VIN(diff) = −100 mV
5
Temperature extremes
4
Temperature extremes
(2)
(3)
6
50
mV
from either
rail
50
5
VCM = 3 V
50
50
2
Sourcing, VO to V–
VIN(diff) = 100 mV
VCM = 0.3 V
V
120
3
RL = 100 kΩ to V+/2
VIN(diff) = −100 mV
pA
dB
3.4
82
μV/°C
fA
−0.1
VO = 0.5 V to 2.8 V
RL = 100 kΩ to V+/2
mV
97
11
mA
12
346
Temperature extremes
(1)
1
50
Temperature extremes
IO
1
1.23
–50
0 V ≤ VCM ≤ 3.3 V
UNIT
1
1.23
Temperature extremes
Output Swing Low
MAX
±0.4
Temperature extremes
AVOL
–1
–1.23
Temperature extremes
Input Bias Current
IOS
CMVR
TYP
(2)
Temperature extremes
PSRR
MIN
400
600
471
600
nA
860
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
The short circuit test is a momentary open-loop test.
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6.8 3.3-V AC Electrical Characteristics
Unless otherwise is specified, all limits for TA = 25°C, V+ = 3.3 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
GBW
Gain-Bandwidth Product
CL = 20 pF, RL = 100 kΩ
6.2
SR
Slew Rate
AV = +1,
VIN = 0V to 3.3V
Falling Edge
2.9
Rising Edge
2.5
θm
Phase Margin
CL = 20 pF, RL = 10 kΩ
Gm
Gain Margin
CL = 20 pF, RL = 10 kΩ
en
Input-Referred Voltage Noise Density
f = 100 Hz
Input-Referred Voltage Noise
0.1 Hz to 10 Hz
Input-Referred Current Noise
f = 100 Hz
In
(1)
MAX
UNIT
kHz
V/ms
73
deg
19
dB
259
nV/√Hz
22
μVPP
100
fA/√Hz
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
6.9 5-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ. (1)
PARAMETER
VOS
Input Offset Voltage
TEST CONDITIONS
MIN
VCM = 0.3 V
Temperature extremes
IBIAS
Input Offset Voltage Drift
Temperature extremes
–1.23
Temperature extremes
–3.5
Common Mode Rejection Ratio
CMVR
Power Supply Rejection Ratio
Common Mode Voltage Range
(1)
(2)
Large Signal Voltage Gain
μV/°C
±1
50
60
0 V ≤ VCM ≤ 5.0 V
75
Temperature extremes
74
0 V ≤ VCM ≤ 3.9 V
84
Temperature extremes
80
Temperature extremes
76
1.6 V ≤ V+ ≤ 5.5 V
VCM = 0.3 V
85
Temperature extremes
76
CMRR ≥ 75 dB
CMRR ≥ 74 dB
Temperature extremes
AVOL
mV
3.5
–50
77
PSRR
±1
UNIT
1.23
0.04
Temperature extremes
Input Offset Current
1.23
±0.4
Input Bias Current
CMRR
±1
0.1
(2)
IOS
MAX
0.1
–1.23
VCM = 4.7 V
TCVOS
TYP
pA
fA
102
108
dB
115
109
dB
−0.1
5.1
0
5
V
VO = 0.5 V to 4.5 V
RL = 100 kΩ to V+/2
84
Temperature extremes
76
132
dB
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
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5-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.(1)
PARAMETER
VO
Output Swing High
TEST CONDITIONS
MIN
+
RL = 100 kΩ to V /2
VIN(diff) = 100 mV
TYP
MAX
3
50
Temperature extremes
Output Swing Low
50
RL = 100 kΩ to V+/2
VIN (diff) = −100 mV
3
Temperature extremes
IO
Output Current
Sourcing, VO to V−
VIN(diff) = 100 mV
Sinking, VO to V+
VIN(diff) = −100 mV
Supply Current
23
8
15
Temperature extremes
IS
mV from
either rail
50
15
Temperature extremes
50
UNIT
mA
22
8
VCM = 0.3 V
351
Temperature extremes
400
620
VCM = 4.7 V
475
Temperature extremes
600
nA
870
6.10 5-V AC Electrical Characteristics (1)
Unless otherwise specified, all limits for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL > 1 MΩ.
PARAMETER
TEST CONDITIONS
GBW
Gain-Bandwidth Product
CL = 20 pF, RL = 100 kΩ
SR
Slew Rate
AV = +1,
VIN = 0 V to 5 V
MIN
(2)
TYP
(3)
6.2
Falling Edge
1.1
Temperature
extremes
1.2
Rising Edge
1.1
Temperature
extremes
1.2
MAX
(2)
UNIT
kHz
2.7
2.4
V/ms
θm
Phase Margin
CL = 20 pF, RL = 100 kΩ
73
deg
Gm
Gain Margin
CL = 20 pF, RL = 100 kΩ
20
dB
en
Input-Referred Voltage Noise Density
f = 100 Hz
255
nV/√Hz
Input-Referred Voltage Noise
0.1 Hz to 10 Hz
In
Input-Referred Current Noise
EMIRR
EMI Rejection Ratio, IN+ and IN− (4)
(1)
(2)
(3)
(4)
8
22
μVPP
f = 100 Hz
100
fA/√Hz
VRF_PEAK = 100 mVP (−20 dBP),
f = 400 MHz
121
VRF_PEAK = 100 mVP (−20 dBP),
f = 900 MHz
121
VRF_PEAK = 100 mVP (−20 dBP),
f = 1800 MHz
124
VRF_PEAK = 100 mVP (−20 dBP),
f = 2400 MHz
142
dB
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
All limits are guaranteed by testing, statistical analysis or design.
Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production
material.
The EMI Rejection Ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).
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6.11 Typical Characteristics
At TJ = 25°C, unless otherwise specified.
800
700
600
500
400
300
200
100
0
SUPPLY CURRENT (nA)
SUPPLY CURRENT (nA)
125°C
125°C
85°C
25°C
VCM = 0.3V
-40°C
1
2
3
4
5
800
700
600
500
400
300
200
100
0
6
85°C
25°C
-40°C
VCM = VS ± 0.3V
1
2
SUPPLY VOLTAGE (V)
3
4
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Supply Current vs. Supply Voltage
VS = 1.8V
VS = 1.8V
-40oC = TA = 125oC
o
TA = 25 C
25
VCM = VS/2
VCM = VS/2
PERCENTAGE (%)
PERCENTAGE (%)
20
15
10
5
20
15
10
5
0
-3.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
-2.0
VOS (mV)
-1.0
0.0
1.0
2.0
3.0
TCVOS (PV/C)
Figure 3. Offset Voltage Distribution
Figure 4. TcvOS Distribution
30
20
VS = 3.3V
18
VS = 3.3V
16
TA = 25oC
VCM = VS/2
14
12
10
8
6
-40oC d TA d 125oC
25
PERCENTAGE (%)
PERCENTAGE (%)
6
30
25
0
5
SUPPLY VOLTAGE (V)
VCM = VS/2
20
15
10
4
5
2
0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
0
-3.0
VOS (mV)
-2.0
-1.0
0.0
1.0
2.0
3.0
TCVOS (PV/C)
Figure 5. Offset Voltage Distribution
Figure 6. TcvOS Distribution
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
30
25
VS = 5V
VS = 5V
15
10
PERCENTAGE (%)
PERCENTAGE (%)
VCM = VS/2
VCM = VS/2
20
15
10
5
0
-40oC d TA d 125oC
25
TA = 25oC
20
5
0
-3.0
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
-2.0
-1.0
VOS (mV)
Figure 7. Offset Voltage Distribution
-40°C
100
0
-100
-300
3.0
100
25°C
-200
2.0
VS = 3.3V
-40°C
150
VOS (éV)
VOS (éV)
200
1.0
Figure 8. TcvOS Distribution
VS = 1.8V
300
0.0
TCVOS (PV/C)
50
25°C
0
-50
-100
85°C
125°C
85°C
-150
125°C
0.0
0.3
0.6
0.9
1.2
1.5
1.8
-0.1
0.4
0.9
Figure 9. Input Offset Voltage vs. Input Common Mode
VS = 5V
100
50
50
25°C
0
-50
2.9
3.4
25°C
0
-50
-100
85°C
-150
85°C
-150
125°C
125°C
-0.50.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
1
2
3
4
5
6
VS (V)
VCM (V)
Figure 11. Input Offset Voltage vs. Input Common Mode
10
2.4
VCM = 0.3V
-40°C
150
-40°C
100
-100
1.9
Figure 10. Input Offset Voltage vs. Input Common Mode
VOS (éV)
VOS (éV)
150
1.4
VCM (V)
VCM (V)
Figure 12. Input Offset Voltage vs. Supply Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
100
50
50
VOS (éV)
100
0
85°C
-50
25°C
0
-50
85°C
125°C
-100
VS = 1.8V
150
-40°C
25°C
VOS (éV)
-40°C
VCM = VS - 0.3V
150
-100
-150
-150
125°C
1
2
3
4
5
0.0
6
0.5
VS (V)
Figure 13. Input Offset Voltage vs. Supply Voltage
150
150
0
-50
85°C
-100
VS = 5V
-40°C
50
25°C
0
-50
85°C
-100
-150
-150
125°C
0.0
0.5
1.0
1.5
125°C
2.0
2.5
3.0
3.5
0.0
1.0
Figure 15. Input Offset Voltage vs. Output Voltage
150
0
-50
4.0
5.0
VS = 3.3V
-40°C
100
25°C
VOS (éV)
VOS (éV)
100
50
3.0
Figure 16. Input Offset Voltage vs. Output Voltage
VS = 1.8V
-40°C
2.0
VOUT (V)
VOUT (V)
150
2.0
100
25°C
VOS (éV)
VOS (éV)
100
50
1.5
Figure 14. Input Offset Voltage vs. Output Voltage
VS = 3.3V
-40°C
1.0
VOUT (V)
85°C
-100
50
25°C
0
-50
85°C
-100
-150
-150
125°C
125°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
ISOURCE (mA)
ISOURCE (mA)
Figure 17. Input Offset Voltage vs. Sourcing Current
Figure 18. Input Offset Voltage vs. Sourcing Current
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
VS = 5V
-40°C
150
100
VS = 1.8V
-40°C
150
100
25°C
VOS (éV)
VOS (éV)
25°C
50
0
-50
-100
50
0
-50
85°C
-100
85°C
-150
-150
125°C
125°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
Figure 19. Input Offset Voltage vs. Sourcing Current
2.0
VS = 5V
-40°C
150
100
100
25°C
VOS (éV)
50
VOS (éV)
1.5
Figure 20. Input Offset Voltage vs. Sinking Current
VS = 3.3V
-40°C
150
1.0
ISOURCE (mA)
ISOURCE (mA)
0
-50
85°C
-100
25°C
50
0
-50
-100
-150
85°C
-150
125°C
0.0
0.5
1.0
125°C
1.5
2.0
0.0
0.5
ISOURCE (mA)
1.0
1.5
2.0
ISOURCE (mA)
Figure 21. Input Offset Voltage vs. Sinking Current
Figure 22. Input Offset Voltage vs. Sinking Current
5
5
VS = 1.8V
VS = 1.8V
-40°C
4
-40°C
4
ISINK (mA)
ISOURCE (mA)
25°C
25°C
3
2
3
2
85°C
85°C
1
1
125°C
0
0.0
0.5
1.0
1.5
2.0
0
0.0
OUTPUT VOLTAGE REFERENCED TO V (V)
12
0.5
1.0
1.5
2.0
OUTPUT VOLTAGE REFERENCED TO V- (V)
+
Figure 23. Sourcing Current vs. Output Voltage
125°C
Figure 24. Sinking Current vs. Output Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
16
16
VS = 3.3V
12
25°C
ISINK (mA)
ISOURCE (mA)
12
8
85°C
4
25°C
8
85°C
4
125°C
125°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-
+
OUTPUT VOLTAGE REFERENCED TO V (V)
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 25. Sourcing Current vs. Output Voltage
Figure 26. Sinking Current vs. Output Voltage
30
30
VS = 5V
-40°C
VS = 5V
-40°C
25
25
25°C
25°C
20
20
ISINK (mA)
ISOURCE (mA)
-40°C
VS = 3.3V
-40°C
15
10
15
85°C
10
85°C
125°C
5
0
0
5
125°C
1
2
3
4
0
0
5
OUTPUT VOLTAGE REFERENCED TO V+ (V)
2
3
4
5
-
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 27. Sourcing Current vs. Output Voltage
Figure 28. Sinking Current vs. Output Voltage
40
40
VCM = VS/2
VCM = VS/2
-40°C
30
30
-40°C
ISINK (mA)
ISOURCE (mA)
1
25°C
20
10
25°C
20
10
85°C
85°C
125°C
0
1
2
3
4
125°C
5
6
0
1
VS (V)
2
3
4
5
6
VS (V)
Figure 29. Sourcing Current vs. Supply Voltage
Figure 30. Sinking Current vs. Supply Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
5
125°C
4
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
5 RL = 100 k:
85°C
3
2
25°C
1
RL = 100 k:
125°C
4
85°C
3
-40°C
0
1
-40°C
3
2
2
4
5
25°C
6
1
2
3
4
Figure 31. Output Swing High vs. Supply Voltage
15
VS = 1.8V
VS = 1.8V
10
10
5
125°C
5
25°C
IBIAS (pA)
IBIAS (fA)
6
Figure 32. Output Swing Low vs. Supply Voltage
15
0
-5
5
VS (V)
VS (V)
0
-5
-40°C
-10
85°C
-10
-15
0.0
0.5
1.0
1.5
-15
0.0
2.0
0.5
1.0
1.5
2.0
VCM (V)
VCM (V)
Figure 33. Input Bias Current vs. Common Mode Voltage
Figure 34. Input Bias Current vs. Common Mode Voltage
50
15
VS = 3.3V
40
VS = 3.3V
10
30
25°C
10
0
-10
-20
125°C
5
IBIAS (pA)
IBIAS (fA)
20
0
-5
85°C
-40°C
-10
-30
-40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-15
0.0
1.0
1.5
2.0
2.5
3.0
3.5
VCM (V)
VCM (V)
Figure 35. Input Bias Current vs. Common Mode Voltage
14
0.5
Figure 36. Input Bias Current vs. Common Mode Voltage
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
400
30
VS = 5V
VS = 5V
25
300
20
200
15
IBIAS (pA)
IBIAS (fA)
25°C
100
0
125°C
10
5
0
-5
-100
85°C
-40°C
-10
-200
-15
-300
0
1
2
3
4
-20
0
5
1
2
VCM (V)
3
4
5
VCM (V)
Figure 37. Input Bias Current vs. Common Mode Voltage
Figure 38. Input Bias Current vs. Common Mode Voltage
100
VS = 5V
VS = 5V
VS = 1.8V, 3.3V, 5V
VS = 1.8V, 3.3V, 5V
100
90
80 VS = 3.3V
CMRR (dB)
PSRR (dB)
80
60
VS = 1.8V
+PSRR
40
VS = 1.8V
70
60
20
-PSRR
50
0
100
1k
10k
40
10
1e1
100k
100
1e2
FREQUENCY (Hz)
130
110
90
70
25°C
50
30
10
-40°C -10
-30
0
-20
100
GAIN (dB)
125°C
130
110
90
70
25°C
50
30
10
-40°C -10
-30
RL = 1 M:
40
PHASE (°)
GAIN (dB)
GAIN
CL = 20 pF
PHASE
RL = 1 M:
85°C
20
VS = 3.3V
60
CL = 20 pF
40
100k
1e5
Figure 40. CMRR vs. Frequency
VS = 1.8V
PHASE
10k
1e4
FREQUENCY (Hz)
Figure 39. PSRR vs. Frequency
60
1k
1e3
85°C
20
GAIN
125°C
0
PHASE (°)
10
-20
1k
10k
100k
100
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
Figure 41. Frequency Response vs. Temperature
Figure 42. Frequency Response vs. Temperature
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
130
110
90
70
25°C
50
30
10
-40°C -10
-30
125°C
0
20
GAIN
0
-20
RL = 10 k:
-20
100
1k
10k
100k
100
1k
Figure 43. Frequency Response vs. Temperature
GAIN
0
40
GAIN (dB)
20
100
20
GAIN
0
RL = 10 k:
-20
10k
100k
100
1k
FREQUENCY (Hz)
20
GAIN
CL = 200 pF
0
-20
40
CL = 100 pF
20
GAIN
CL = 200 pF
0
130
110
CL = 20 pF
90
70
50
30
10
-10
-30
-20
100
1k
10k
100k
FREQUENCY (Hz)
100
1k
10k
100k
FREQUENCY (Hz)
Figure 47. Frequency Response vs. CL
16
RL = 10 M:
CL = 50 pF
PHASE
GAIN (dB)
CL = 100 pF
130
110
CL = 20 pF 90
70
50
30
10
-10
-30
PHASE (°)
GAIN (dB)
40
VS = 3.3V
60
RL = 10 M:
CL = 50 pF
100k
Figure 46. Frequency Response vs. RL
VS = 1.8V
PHASE
10k
FREQUENCY (Hz)
Figure 45. Frequency Response vs. RL
60
130
110
RL = 10 M:
90
70
50
30
10
-10
-30
RL = 10 k:
-20
1k
CL = 20 pF
RL = 1 M:
PHASE
PHASE (°)
GAIN (dB)
40
130
110
RL = 10 M:
90
70
50
30
10
-10
-30
VS = 5V
RL = 100 k:
60
CL = 20 pF
RL = 1 M:
PHASE
100k
Figure 44. Frequency Response vs. RL
VS = 3.3V
RL = 100 k:
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
60
130
110
RL = 10 M:
90
70
50
30
10
-10
-30
PHASE (°)
GAIN
GAIN (dB)
85°C
20
40
PHASE (°)
GAIN (dB)
40
CL = 20 pF
RL = 1 M:
PHASE
RL = 1 M:
PHASE (°)
PHASE
VS = 1.8V
RL = 100 k:
60
CL = 20 pF
PHASE (°)
VS = 5V
60
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Figure 48. Frequency Response vs. CL
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
VS = 5V
60
GAIN
CL = 200 pF
0
FALLING EDGE
3.0
SLEW RATE (V/ms)
GAIN (dB)
CL = 100 pF
PHASE (°)
130
110
CL = 20 pF
90
70
50
30
10
-10
-30
40
20
3.3
RL = 10 M:
CL = 50 pF
PHASE
2.7
2.4
RISING EDGE
2.1
AV = +1
1.8
-20
VOUT = VS
100
1k
10k
100k
1.5
FREQUENCY (Hz)
2.3
3.1
3.9
4.7
5.5
SUPPLY VOLTAGE (V)
Figure 49. Frequency Response vs. CL
Figure 50. Slew Rate vs. Supply Voltage
15
1000
VS = 1.8V
VCM = VS/2
VOLTAGE NOISE (nV/íHz)
10
5 PV/DIV
5
0
-5
-10
VS = 5V
100
1
10
100
1k
-15
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
10k
FREQUENCY (Hz)
1s/DIV
Figure 52. 0.1 to 10 Hz Time Domain Voltage Noise
15
10
10
5
5
5 PV/DIV
5 PV/DIV
Figure 51. Voltage Noise vs. Frequency
15
0
-5
VS = 5V
VCM = VS/2
0
-5
-10
-10
VS = 3.3V
VCM = VS/2
-15
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
-15
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
1s/DIV
1s/DIV
Figure 53. 0.1 to 10 Hz Time Domain Voltage Noise
Figure 54. 0.1 to 10 Hz Time Domain Voltage Noise
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Typical Characteristics (continued)
At TJ = 25°C, unless otherwise specified.
INPUT
50 mV/DIV
50 mV/DIV
INPUT
OUTPUT
OUTPUT
VS = 5V
VS = 1.8V
RL = 100 k:
RL = 100 k:
200 Ps/DIV
200 Ps/DIV
Figure 55. Small Signal Pulse Response
Figure 56. Small Signal Pulse Response
INPUT
500 mV/DIV
500 mV/DIV
INPUT
OUTPUT
OUTPUT
VS = 5V
VS = 1.8V
RL = 100 k:
RL = 100 k:
200 Ps/DIV
200 Ps/DIV
Figure 57. Large Signal Pulse Response
Figure 58. Large Signal Pulse Response
4
INPUT
3
OUTPUT
EMIRRV_PEAK (dB)
2
1V/DIV
1
0
-1
-2
+
-3
170
150
130
110
90
70
50
30
10
VS = 5V
V = +2.5V
VPEAK = -20 dBVp
-
V = -2.5V
-4
2 ms/DIV
0.1
1.0e-1
1
1.0
10
1.0e1
100
1.0e2
1000
1.0e3
10000
1.0e4
FREQUENCY (MHz)
Figure 59. Overload Recovery Waveform
18
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Figure 60. EMIRR vs. Frequency
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7 Detailed Description
7.1 Overview
The LPV521 is fabricated with Texas Instruments' state-of-the-art VIP50 process. This proprietary process
dramatically improves the performance of Texas Instruments' low-power and low-voltage operational amplifiers.
The following sections showcase the advantages of the VIP50 process and highlight circuits which enable ultralow power consumption.
7.2 Functional Block Diagram
Figure 61. Block Diagram
7.3 Feature Description
The amplifier's differential inputs consist of a noninverting input (+IN) and an inverting input (–IN). The amplifier
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp Vout is given by Equation 1:
VOUT = AOL (IN+ - IN-)
(1)
where AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10uV per Volt).
7.4 Device Functional Modes
7.4.1 Input Stage
The LPV521 has a rail-to-rail input which provides more flexibility for the system designer. Rail-to-rail input is
achieved by using in parallel, one PMOS differential pair and one NMOS differential pair. When the common
mode input voltage (VCM) is near V+, the NMOS pair is on and the PMOS pair is off. When VCM is near V−, the
NMOS pair is off and the PMOS pair is on. When VCM is between V+ and V−, internal logic decides how much
current each differential pair will get. This special logic ensures stable and low distortion amplifier operation
within the entire common mode voltage range.
Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LPV521
becomes a function of VCM. VOS has a crossover point at 1.0 V below V+. Refer to the ’VOS vs. VCM’ curve in the
Typical Performance Characteristics section. Caution should be taken in situations where the input signal
amplitude is comparable to the VOS value and/or the design requires high accuracy. In these situations, it is
necessary for the input signal to avoid the crossover point. In addition, parameters such as PSRR and CMRR
which involve the input offset voltage will also be affected by changes in VCM across the differential pair transition
region.
7.4.2 Output Stage
The LPV521 output voltage swings 3 mV from rails at 3.3-V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV521 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load. The LPV521 output swings 50 mV from the rail at 5-V supply with an output load of 100 kΩ.
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV521is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.25 V). Many of the specifications apply
from –40°C to 125°C. The LMV521 features rail to rail input and rail-to-rail output swings while consuming only
nanowatts of power. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
8.1.1 Driving Capacitive Load
The LPV521 is internally compensated for stable unity gain operation, with a 6.2-kHz, typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed at the output of an amplifier along with the amplifier’s output impedance creates a phase
lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response
will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp
might start oscillating.
-
RISO
VOUT
VIN
+
CL
Figure 62. Resistive Isolation of Capacitive Load
In order to drive heavy capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 62. By
using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger the value of
RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be
stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive.
Recommended minimum values for RISO are given in the following table, for 5-V supply. Figure 63 shows the
typical response obtained with the CL = 50 pF and RISO = 154 kΩ. The other values of RISO in the table were
chosen to achieve similar dampening at their respective capacitive loads. Notice that for the LPV521 with larger
CL a smaller RISO can be used for stability. However, for a given CL a larger RISO will provide a more damped
response. For capacitive loads of 20 pF and below no isolation resistor is needed.
20
CL
RISO
0 – 20 pF
not needed
50 pF
154 kΩ
100 pF
118 kΩ
500 pF
52.3 kΩ
1 nF
33.2 kΩ
5 nF
17.4 kΩ
10 nF
13.3 kΩ
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VIN
20 mV/DIV
VOUT
VS = 5V
200 Ps/DIV
Figure 63. Step Response
8.1.2 EMI Suppression
The near-ubiquity of cellular, Bluetooth, and Wi-Fi signals and the rapid rise of sensing systems incorporating
wireless radios make electromagnetic interference (EMI) an evermore important design consideration for
precision signal paths. Though RF signals lie outside the op amp band, RF carrier switching can modulate the
DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components.
The added DC offset and the induced signals are amplified with the signal of interest and thus corrupt the
measurement. The LPV521 uses on chip filters to reject these unwanted RF signals at the inputs and power
supply pins; thereby preserving the integrity of the precision signal path.
Twisted pair cabling and the active front-end’s common-mode rejection provide immunity against low-frequency
noise (i.e. 60-Hz or 50-Hz mains) but are ineffective against RF interference. Even a few centimeters of PCB
trace and wiring for sensors located close to the amplifier can pick up significant 1 GHz RF. The integrated EMI
filters of the LPV521 reduce or eliminate external shielding and filtering requirements, thereby increasing system
robustness. A larger EMIRR means more rejection of the RF interference. For more information on EMIRR,
please refer to AN-1698.
8.2 Typical Applications
8.2.1 60-Hz Twin T-Notch Filter
VBATT = 3V o2V @ end of life
CR2032 Coin Cell
225 mAh = 5 circuits @ 9.5 yrs.
10 M:
10 M:
VBATT
-
Remote Sensor
10 M:
+
VIN
Signal
+
60 Hz
To ADC
VOUT
10 M:
270 pF
270 pF
10 M:
10 M:
Signal × 2
(No 60 Hz)
60 Hz Twin T Notch Filter
270 pF
AV = 2 V/V
270 pF
Figure 64. 60-Hz Notch Filter
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Typical Applications (continued)
8.2.1.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60-Hz
interference from AC power lines. The circuit of Figure 64 notches out the 60 Hz and provides a gain AV = 2 for
the sensor signal represented by a 1-kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd
harmonics of 60 Hz. Thanks to the nA power consumption of the LPV521, even 5 such circuits can run for 9.5
years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3 V and an end of life voltage
of 2 V. With an operating voltage from 1.6 V to 5.5 V the LPV521 can function over this voltage range.
8.2.1.2 Detailed Design Procedure
The notch frequency is set by F0 = 1 / 2πRC. To achieve a 60-Hz notch use R = 10 MΩ and C = 270 pF. If
eliminating 50-Hz noise, which is common in European systems, use R = 11.8 MΩ and C = 270 pF.
The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency
path through the resistors R - R and another separate high frequency path through the capacitors C - C.
However, at frequencies around the notch frequency, the two paths have opposing phase angles and the two
signals will tend to cancel at the amplifier’s input.
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter
needs to be as balanced as possible. To obtain circuit balance, while overcoming limitations of available
standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements
for the filter components that connect to ground.
To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water,
and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may
increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 64 can be done over a bandwidth of 5 kHz,
which takes the conservative approach of overestimating the bandwidth (LPV521 typical GBW/AV is lower). The
total noise at the output is approximately 800 µVpp, which is excellent considering the total consumption of the
circuit is only 540 nA. The dominant noise terms are op amp voltage noise (550 µVpp), current noise through the
feedback network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total
circuit's noise is below ½ LSB of a 10 bit system with a 2-V reference, which is 1 mV.
8.2.1.3 Application Curve
Figure 65. 60-Hz Notch Filter Waveform
22
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Typical Applications (continued)
8.2.2 Portable Gas Detection Sensor
100 M:
V
1 M:
+
VOUT
+
-
V
RL
OXYGEN SENSOR
Figure 66. Precision Oxygen Sensor
8.2.2.1 Design Requirements
Gas sensors are used in many different industrial and medical applications. They generate a current which is
proportional to the percentage of a particular gas sensed in an air sample. This current goes through a load
resistor and the resulting voltage drop is measured. The LPV521 makes an excellent choice for this application
as it only draws 345 nA of current and operates on supply voltages down to 1.6V. Depending on the sensed gas
and sensitivity of the sensor, the output current can be in the order of tens of microamperes to a few
milliamperes. Gas sensor datasheets often specify a recommended load resistor value or they suggest a range
of load resistors to choose from.
Oxygen sensors are used when air quality or oxygen delivered to a patient needs to be monitored. Fresh air
contains 20.9% oxygen. Air samples containing less than 18% oxygen are considered dangerous. This
application detects oxygen in air. Oxygen sensors are also used in industrial applications where the environment
must lack oxygen. An example is when food is vacuum packed. There are two main categories of oxygen
sensors, those which sense oxygen when it is abundantly present (i.e. in air or near an oxygen tank) and those
which detect traces of oxygen in ppm.
8.2.2.2 Detailed Design Procedure
Figure 66 shows a typical circuit used to amplify the output of an oxygen detector. The oxygen sensor outputs a
known current through the load resistor. This value changes with the amount of oxygen present in the air sample.
Oxygen sensors usually recommend a particular load resistor value or specify a range of acceptable values for
the load resistor. The use of the nanopower LPV521 means minimal power usage by the op amp and it
enhances the battery life. With the components shown in Figure 66 the circuit can consume less than 0.5 µA of
current ensuring that even batteries used in compact portable electronics, with low mAh charge ratings, could
last beyond the life of the oxygen sensor. The precision specifications of the LPV521, such as its very low offset
voltage, low TCVOS , low input bias current, high CMRR, and high PSRR are other factors which make the
LPV521 a great choice for this application.
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Typical Applications (continued)
8.2.2.3 Application Curve
5.0
4.5
4.0
VOUT (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
VSENSOR (mV)
C001
Figure 67. Calculated Oxygen Sensor Circuit Output (Single 5V Supply)
8.2.3 High-Side Battery Current Sensing
ICHARGE
RSENSE
+
V
-
+
+
V
R1
24.9 k:
Q1
2N2907
RSENSE X R3
VOUT =
R1
-
R2
24.9 k:
+
10:
LOAD
X ICHARGE
VOUT
R3
10 M:
Figure 68. High-Side Current Sensing
8.2.3.1 Design Requirements
The rail-to-rail common mode input range and the very low quiescent current make the LPV521 ideal to use in
high-side and low-side battery current sensing applications. The high-side current sensing circuit in Figure 68 is
commonly used in a battery charger to monitor the charging current in order to prevent over charging. A sense
resistor RSENSE is connected in series with the battery.
8.2.3.2 Detailed Design Procedure
The theoretical output voltage of the circuit is VOUT = [ ®SENSE × R3) / R1 ] × ICHARGE. In reality, however, due to
the finite Current Gain, β, of the transistor the current that travels through R3 will not be ICHARGE, but instead, will
be α × ICHARGE or β/( β+1) × ICHARGE. A Darlington pair can be used to increase the β and performance of the
measuring circuit.
Using the components shown in Figure 68 will result in VOUT ≈ 4000 Ω × ICHARGE. This is ideal to amplify a 1 mA
ICHARGE to near full scale of an ADC with VREF at 4.1 V. A resistor, R2 is used at the noninverting input of the
amplifier, with the same value as R1 to minimize offset voltage.
24
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Typical Applications (continued)
Selecting values per Figure 68 will limit the current traveling through the R1 – Q1 – R3 leg of the circuit to under 1
µA which is on the same order as the LPV521 supply current. Increasing resistors R1 , R2 , and R3 will decrease
the measuring circuit supply current and extend battery life.
Decreasing RSENSE will minimize error due to resistor tolerance, however, this will also decrease VSENSE =
ICHARGE × RSENSE, and in turn the amplifier offset voltage will have a more significant contribution to the total error
of the circuit. With the components shown in Figure 68 the measurement circuit supply current can be kept below
1.5 µA and measure 100 µA to 1 mA.
8.2.3.3 Application Curve
5.0
4.5
4.0
VOUT (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
0.25
0.5
0.75
1
ICHARGE (mA)
1.25
1.5
C001
Figure 69. Calculated High-Side Current Sense Circuit Output
9 Power Supply Recommendations
The LPV521 is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
Low bandwidth nanopower devices do not have good high frequency (>1KHz) AC PSRR rejection against highfrequency switching supplies and other kHz and above noise sources, so extra supply filtering is recommended if
kHz range noise is expected on the power supply lines.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 70. Noninverting Layout Example
26
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LPV521 PSPICE Model, SNOM024
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
TI Filterpro Software, http://www.ti.com/tool/filterpro
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
Evaluation board for 5-pin, north-facing amplifiers in the SC70 package, SNOA487.
Manual for LMH730268 Evaluation board 551012922-001
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Feedback Plots Define Op Amp AC Performance, SBOA015 (AB-028)
• Circuit Board Layout Techniques, SLOA089
• Op Amps for Everyone, SLOD006
• AN-1698 A Specification for EMI Hardened Operational Amplifiers, SNOA497
• EMI Rejection Ratio of Operational Amplifiers, SBOA128
• Capacitive Load Drive Solution using an Isolation Resistor, TIPD128
• Handbook of Operational Amplifier Applications, SBOA092
11.3 Trademarks
PowerWise is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LPV521MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AHA
LPV521MGE/NOPB
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AHA
LPV521MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AHA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LPV521MG/NOPB
SC70
DCK
5
LPV521MGE/NOPB
SC70
DCK
LPV521MGX/NOPB
SC70
DCK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
250
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LPV521MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LPV521MGE/NOPB
SC70
DCK
5
250
210.0
185.0
35.0
LPV521MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
Pack Materials-Page 2
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