LINER LT6237 18-bit, 1msps, 8-channel sar adc with 100db snr Datasheet

LTC2373-18
18-Bit, 1Msps, 8-Channel
SAR ADC with 100dB SNR
Features
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Description
1Msps Throughput Rate
18-Bit Resolution with No Missing Codes
8-Channel Multiplexer with Selectable Input Range
n Fully Differential (±4.096V)
n Pseudo-Differential Unipolar (0V to 4.096V)
n Pseudo-Differential Bipolar (±2.048V)
INL: ±2.75LSB (Maximum)
SNR: 100dB (Fully Differential)/95dB (PseudoDifferential) (Typical) at fIN = 1kHz
THD: –110dB (Typical) at fIN = 1kHz
Programmable Sequencer
Selectable Digital Gain Compression
Single 5V Supply with 1.8V to 5V I/O Voltages
SPI-Compatible Serial I/O
Onboard 2.048V Reference and Reference Buffer
No Pipeline Delay, No Cycle Latency
Power Dissipation 40mW (Typical)
Guaranteed Operation to 125°C
32-Lead 5mm × 5mm QFN Package
The LTC®2373-18 is a low noise, high speed, 8-channel
18-bit successive approximation register (SAR) ADC. Operating from a single 5V supply, the LTC2373-18 has a highly
configurable, low crosstalk 8-channel input multiplexer,
supporting fully differential, pseudo-differential unipolar
and pseudo-differential bipolar analog input ranges. The
LTC2373-18 achieves ±2.75LSB INL (maximum) in all
input ranges, no missing codes at 18-bits and 100dB (fully
differential)/ 95dB (pseudo-differential) SNR (typical).
The LTC2373-18 has an onboard low drift (20ppm/°C max)
2.048V temperature-compensated reference and a singleshot capable reference buffer. The LTC2373-18 also has a
high speed SPI-compatible serial interface that supports
1.8V, 2.5V, 3.3V and 5V logic through which a sequencer
with a depth of 16 may be programmed. An internal oscillator sets the conversion time, easing external timing
considerations. The LTC2373-18 dissipates only 40mW
and automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided to reduce the power
consumption of the LTC2373-18 to 300μW for further
power savings during inactive periods.
Applications
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Programmable Logic Controllers
Industrial Process Control
High Speed Data Acquisition
Portable or Compact Instrumentation
ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673.
Typical Application
Integral Nonlinearity
vs Output Code
5V
4.096V
0.1µF
0V
10Ω
VDDLBYP OVDD
LTC2373-18
+
18-BIT
SAMPLING ADC
–
ADCIN–
4.096V
–
1200pF
CH0
CH1
CH2
CH3 MUX
CH4
CH5
CH6
CH7
COM
VDD
ADCIN+
0V
1200pF
MUXOUT+
4.096V
+
MUXOUT–
0V
10Ω
REFBUF
47µF
FULLY DIFFERENTIAL
BIPOLAR
UNIPOLAR
1.5
2.2µF
REFIN
0.1µF
GND
1.0
INL ERROR (LSB)
10µF
0V
4.096V
2.0
1.8V TO 5V
0V
RESET
RDL
SDO
SCK
SDI
BUSY
CNV
237318 TA01a
2.048V
0.5
0
–0.5
–1.0
SAMPLE
CLOCK
–1.5
–2.0
0
65536
131072
OUTPUT CODE
196608
262144
2373 TA01b
237318f
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1
LTC2373-18
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
OVDD
GND
GND
VDDLBYP
VDD
COM
CH0
CH1
TOP VIEW
32 31 30 29 28 27 26 25
CH2 1
24 RESET
CH3 2
23 GND
MUXOUT+ 3
22 SDO
ADCIN+ 4
21 SCK
33
ADCIN– 5
20 SDI
MUXOUT– 6
19 BUSY
CH4 7
18 RDL
CH5 8
17 GND
CNV
GND
GND
REFIN
REFBUF
CH7
GND
9 10 11 12 13 14 15 16
CH6
Supply Voltage (VDD).................................................. 6V
Supply Voltage (OVDD)................................................ 6V
Analog Input Voltage (Note 3)
CH0 to CH7, COM......... (GND – 0.3V) to (VDD + 0.3V)
REFBUF........................ (GND – 0.3V) to (VDD + 0.3V)
REFIN....................................................................... 2.8V
Digital Input Voltage
(Note 3)............................(GND –0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)............................(GND –0.3V) to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2373C.................................................0°C to 70°C
LTC2373I..............................................–40°C to 85°C
LTC2373H...........................................–40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 44°C/W
EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2373CUH-18#PBF
LTC2373CUH-18#TRPBF
237318
32-Lead (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2373IUH-18#PBF
LTC2373IUH-18#TRPBF
237318
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2373HUH-18#PBF
LTC2373HUH-18#TRPBF
237318
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
237318f
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LTC2373-18
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
+
Absolute Input Range (CH0 to CH7)
(Note 5)
l
–
Absolute Input Range
(CH0 to CH7, COM)
Fully Differential (Note 5)
Pseudo-Differential Unipolar (Note 5)
Pseudo-Differential Bipolar (Note 5)
l
l
l
Fully Differential
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
l
l
l
Pseudo-Differential Bipolar and
Fully Differential (Note 6)
l –VREFBUF/2 – 0.1 VREFBUF/2 VREFBUF/2 + 0.1
VIN
VIN
VIN+ – VIN– Input Differential Voltage Range
VCM
Common Mode Input Range
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio Fully Differential, fIN = 500kHz
Pseudo-Differential Unipolar, fIN = 500kHz
Pseudo-Differential Bipolar, fIN = 500kHz
MIN
l
TYP
–0.1
MAX
UNITS
VREFBUF + 0.1
V
–0.1
VREFBUF + 0.1
–0.1
0.1
0
VREFBUF/2 – 0.1 VREFBUF/2 VREFBUF/2 + 0.1
–VREFBUF
0
–VREFBUF/2
VREFBUF
VREFBUF
VREFBUF/2
–1
1
Sample Mode
Hold Mode
V
V
V
V
V
V
V
µA
75
5
pF
pF
67
66
66
dB
dB
dB
Converter Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
l
18
Bits
No Missing Codes
l
18
Bits
Transition Noise
Fully Differential
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
INL
Integral Linearity Error
Fully Differential (Note 7)
Pseudo-Differential Unipolar (Note 7)
Pseudo-Differential Bipolar (Note 7)
l
l
l
–2
–2.75
–2.75
±0.5
±0.8
±0.8
2
2.75
2.75
LSB
LSB
LSB
DNL
Differential Linearity Error
Fully Differential (Note 6)
Pseudo-Differential Unipolar (Note 6)
Pseudo-Differential Bipolar (Note 6)
l
l
l
–0.9
–0.9
–0.9
±0.25
±0.25
±0.25
0.9
0.9
0.9
LSB
LSB
LSB
ZSE
Zero-Scale Error
Fully Differential (Note 8)
Pseudo-Differential Unipolar (Note 8)
Pseudo-Differential Bipolar (Note 8)
l
l
l
–15
–30
–30
±2
±2
±2
15
30
30
LSB
LSB
LSB
Zero-Scale Error Drift
Fully Differential
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
Zero-Scale Error Match
Fully Differential
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
Full-Scale Error
Fully Differential
REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
Pseudo-Differential Unipolar
REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
Pseudo-Differential Bipolar
REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
FSE
0.85
1.5
1.5
LSBRMS
LSBRMS
LSBRMS
20
30
30
mLSB/°C
mLSB/°C
mLSB/°C
l
l
l
–18
–24
–28
±2
±4
±4
18
24
28
LSB
LSB
LSB
l
l
–50
–100
±7
±11
50
100
LSB
LSB
l
l
–75
–200
±5
±14
75
200
LSB
LSB
l
l
–50
–120
±8
±12
50
120
LSB
LSB
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3
LTC2373-18
Converter Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
Full-Scale Error Drift
Full-Scale Error Match
CONDITIONS
MIN
Fully Differential
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Fully Differential
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
TYP
MAX
UNITS
0.2
ppm/°C
0.2
ppm/°C
0.2
ppm/°C
l
–18
±2
18
LSB
l
–24
±4
24
LSB
l
–28
±4
28
LSB
Dynamic Accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 10)
SYMBOL
PARAMETER
CONDITIONS
SINAD
Signal-to-(Noise + Distortion) Ratio
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Unipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
MIN
TYP
l
96
99.5
dB
l
90.5
94.8
dB
l
90.5
94.8
dB
101.4
dB
96.6
dB
96.6
dB
98.4
dB
93.3
dB
Fully Differential
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
SNR
Signal-to-Noise Ratio
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Unipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Fully Differential
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
4
MAX
UNITS
l
96.5
100
dB
l
91
95.0
dB
l
91
95.0
dB
102
dB
96.8
dB
96.8
dB
98.5
dB
93.4
dB
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Dynamic Accuracy
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 10)
SYMBOL
PARAMETER
CONDITIONS
THD
Total Harmonic Distortion
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Unipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
MIN
TYP
l
–104
–114
dB
l
–99
–110
dB
l
–99
–110
dB
–111
dB
–110
dB
–110
dB
–113
dB
–110
dB
Fully Differential
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
SFDR
Spurious Free Dynamic Range
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Unipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven)
104
114
dB
l
99
110
dB
l
99
110
dB
112
dB
112
dB
112
dB
112.5
dB
113.5
dB
Fully Differential
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
Pseudo-Differential Bipolar
fIN = 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
fIN = 100kHz, Signal Applied to an OFF Channel
–107
–3dB Input Linear Bandwidth
22
Aperture Delay
500
Aperture Jitter
4
Transient Response
UNITS
l
Fully Differential
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
fIN = 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
Channel-to-Channel Crosstalk
MAX
Full-Scale Step
dB
MHz
ps
psRMS
460
ns
Internal Reference Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VREFIN
Internal Reference Output Voltage
VREFIN Temperature Coefficient
CONDITIONS
(Note 11)
MIN
TYP
MAX
2.043
2.048
2.053
4
20
l
REFIN Output Impedance
15
VREFIN Line Regulation
VDD = 4.75V to 5.25V
REFIN Input Voltage Range
(REFIN Overdriven) (Note 5)
V
ppm/°C
kΩ
0.06
1.25
UNITS
mV/V
2.4
V
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5
LTC2373-18
Reference Buffer Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREFBUF
Reference Buffer Output Voltage
VREFIN = 2.048V
l
4.088
4.096
4.104
V
REFBUF Input Voltage Range
(REFBUF Overdriven) (Notes 5, 9)
l
2.5
REFBUF Output Impedance
VREFIN = 0V (Buffer Disabled)
REFBUF Load Current
VREFBUF = 5V (REFBUF Overdriven) (Notes 9, 12)
VREFBUF = 5V, Nap Mode (REFBUF Overdriven) (Note 9)
IREFBUF
5
V
13
kΩ
1.1
0.38
l
1.5
mA
mA
Digital Inputs and Digital Outputs
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
CONDITIONS
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
MIN
l
TYP
MAX
UNITS
0.8 • OVDD
V
l
VIN = 0V to OVDD
l
–10
High Level Output Voltage
IO = –500µA
l
OVDD – 0.2
VOL
Low Level Output Voltage
IO = 500µA
l
l
0.2 • OVDD
V
10
μA
5
pF
V
0.2
V
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
–10
10
µA
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VDD
Supply Voltage
CONDITIONS
OVDD
Supply Voltage
IVDD
IOVDD
INAP
ISLEEP
Supply Current
Supply Current
Nap Mode Current
Sleep Mode Current
1Msps Sample Rate
1Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD)
Sleep Mode (IVDD + IOVDD)
PD
Power Dissipation
Nap Mode
Sleep Mode
1Msps Sample Rate
Conversion Done (IVDD + IOVDD)
Sleep Mode (IVDD + IOVDD)
MIN
TYP
MAX
UNITS
l
4.75
5
5.25
V
l
1.71
5.25
l
l
l
l
V
8.0
0.7
1.25
60
1.5
120
mA
mA
mA
μA
40
6.25
300
55
7.5
600
mW
mW
µW
11
ADC Timing Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
tCONV
Conversion Time
tACQ
Acquisition Time
CONDITIONS
MIN
l
tACQ = tCYC – tCONV – tBUSYLH (Note 6)
TYP
MAX
UNITS
1
Msps
l
460
l
460
527
ns
ns
tCYC
Time Between Conversions
l
1
µs
tCNVH
CNV High Time
l
20
ns
tCNVL
Minimum Low Time for CNV
(Note 14)
l
20
tBUSYLH
CNV↑ to BUSY↑ Delay
CL = 20pF
l
tRESETH
RESET Pulse Width
tQUIET
SCK, SDI and RDL Quiet Time from CNV↑
6
(Note 6)
ns
13
ns
l
200
ns
l
20
ns
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LTC2373-18
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
tSCK
tSCKH
tSCKL
tSSDISCK
SCK Period
SCK High Time
SCK Low Time
(Notes 13, 14)
SDI Setup Time From SCK↑
(Note 13)
l
10
4
4
4
tHSDISCK
SDI Hold Time From SCK↑
(Note 13)
l
1
tDSDO
SDO Data Valid Delay from SCK↑
l
l
l
tHSDO
SDO Data Remains Valid Delay from SCK↑
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
CL = 20pF (Note 6)
tDSDOBUSYL
SDO Data Valid Delay from BUSY↓
CL = 20pF (Note 6)
tEN
Bus Enable Time After RDL↓
tDIS
Bus Relinquish Time After RDL↑
REFBUF Wake-Up Time
tWAKE
tCNVMRST
tMRST1
tVLDMRST
tMRST2
l
l
l
ns
ns
ns
ns
ns
7.5
8
9.5
ns
ns
ns
ns
l
5
ns
(Note 13)
l
16
ns
(Note 13)
l
13
ns
l
CREFBUF = 47μF, CREFIN = 0.1µF
1
CNV↑ to MUX Starts Resetting Delay
MUX Reset Time During Conversion
l
38
ms
ns
l
8th SCK↑ to MUX Starts Resetting Delay After
Programming 1st Valid Configuration Word
MUX Reset Time During Acquisition After
Programming 1st Valid Configuration Word
l
36
40
ns
ns
l
42
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above VDD or OVDD without
latchup.
Note 4: VDD = 5V, OVDD = 2.5V, fSMPL = 1MHz, REFIN = 2.048V unless
otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Guaranteed by design, not subject to test.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Fully differential zero-scale error is the offset voltage measured
from –0.5LSB when the output code flickers between 01 1111 1111 1111
1111 and 10 0000 0000 0000 0000 in straight binary format and 00 0000
0000 0000 0000 and 11 1111 1111 1111 1111 in two’s complement
format. Unipolar zero-scale error is the offset voltage measured from
200
0.5LSB when the output code flickers between 00 0000 0000 0000 0000
and 00 0000 0000 0000 0001. Bipolar zero-scale error is the offset voltage measured from –0.5LSB when the output code flickers between 00
0000 0000 0000 0000 and 11 1111 1111 1111 1111. Fully differential fullscale error is the worst-case deviation of the first and last code transitions
from ideal and includes the effect of offset error. Unipolar full-scale error
is the deviation of the last code transition from the ideal and includes the
effect of offset error. Bipolar full-scale error is the worst-case deviation
of the first and last code transitions from ideal and includes the effect of
offset error.
Note 9: When REFBUF is overdriven, the internal reference buffer must be
turned off by setting REFIN=0V.
Note 10: All specifications in dB are referred to a full-scale ±VREFBUF (fully
differential), 0V to VREFBUF (pseudo-differential unipolar), or ±VREFBUF/2
(pseudo-differential bipolar) input.
Note 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 12: fSMPL = 1MHz, IREFBUF varies proportionally with sample rate.
Note 13: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 14: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising edge capture.
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
237318 F01
Figure 1. Voltage Levels for Timing Specifications
237318f
For more information www.linear.com/LTC2373-18
7
LTC2373-18
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
Fully Differential Range, VCM = 2.048V, fSMPL = 1Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
2.0
0
–0.5
–1.0
100000
0.4
0.2
COUNTS
DNL ERROR (LSB)
0.5
0
–0.2
–0.4
65536
131072
196608
OUTPUT CODE
–1.0
262144
0
65536
131072
196608
OUTPUT CODE
120000
0
σ = 1.00
100000
20000
–80
–100
–120
–160
100
200
300
FREQUENCY (kHz)
400
–180
500
99
98
97
3
4.5
4
3.5
REFBUF VOLTAGE (V)
5
237318 G07
0
100
200
300
FREQUENCY (kHz)
400
SNR, SINAD vs Input Level,
fIN = 1kHz
101.0
–110
SNR
100.5
–115
THD
3RD
SINAD
100.0
–120
99.5
–125
–130
2.5
500
237318 G06
THD, Harmonics vs REFBUF,
fIN = 1kHz
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
–120
–105
100
8
–100
–160
0
4
SNR = 102.3dB
THD = –111.5dB
SINAD = 101.8dB
SFDR = 111.9dB
237318 G05
103
SINAD
3
–80
–140
SNR, SINAD vs REFBUF, fIN = 1kHz
SNR
2
–60
–140
237318 G04
101
0
1
CODE
–40
–60
–180
131052 131054 131056 131058 131060
CODE
102
–1
–20
SNR, SINAD (dBFS)
COUNTS
40000
–2
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40
60000
–3
32k Point FFT fSMPL = 1Msps,
fIN = 1kHz, REFBUF = 5V
SNR = 100.7dB
THD = –114dB
SINAD = 100.5dB
SFDR = 115.3dB
–20
80000
–4
237318 G03
32k Point FFT fSMPL = 1Msps,
fIN = 1kHz
DC Histogram (Near Full-Scale)
96
2.5
0
262144
237318 G02
237318 G01
0
60000
20000
–0.8
0
80000
40000
–0.6
–1.5
σ = 0.85
120000
0.6
1.0
INL ERROR (LSB)
140000
0.8
1.5
–2.0
DC Histogram (Zero-Scale)
1.0
2ND
3
4.5
4
3.5
REFBUF VOLTAGE (V)
5
237318 G08
99.0
–40
–30
–20
–10
INPUT LEVEL (dB)
0
237318 G09
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
Fully Differential Range, VCM = 2.048V, fSMPL = 1Msps, unless otherwise noted.
THD, Harmonics vs Input
Frequency
SNR, SINAD vs Input Frequency
SNR
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
100
95
90
SINAD
85
80
80
–80
75
–90
70
–100
0
25
50
–130
75 100 125 150 175 200
FREQUENCY (kHz)
60
THD
2ND
3RD
0
25
50
55
50
75 100 125 150 175 200
FREQUENCY (kHz)
SNR, SINAD (dBFS)
65
60
SNR
SINAD
98
55
500
THD
100
99
400
–110
THD, HARMONICS (dBFS)
101
85
70
300
200
FREQUENCY (kHz)
THD, Harmonics vs Temperature,
fIN = 1kHz
102
95
90
75
100
237318 G12
SNR, SINAD vs Temperature,
fIN = 1kHz
PSRR vs Frequency
80
0
237318 G11
237318 G10
PSRR (dB)
65
–110
–120
75
70
–70
CMRR (dB)
105
CMRR vs Input Frequency
–115
3RD
–120
2ND
–125
97
50
1
100
10
FREQUENCY (kHz)
96
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1k
237318 G14
237318 G13
237318 G15
Full-Scale Error vs Temperature
REFBUF = 4.096V
INL vs Temperature
2
Zero-Scale Error vs Temperature
4
2.0
3
FULL-SCALE ERROR (LSB)
1
INL ERROR (LSB)
–130
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
MAX INL
0
MIN INL
–1
–2
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G16
1.5
–FS
2
1
OFFSET ERROR (LSB)
45
+FS
0
–1
–2
1.0
0.5
0
–0.5
–1.0
–3
–1.5
–4
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–2.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G17
237318 G18
237318f
For more information www.linear.com/LTC2373-18
9
LTC2373-18
Typical Performance Characteristics
Pseudo-Differential Unipolar Range, fSMPL = 1Msps, unless otherwise noted.
Differential Nonlinearity vs
Output Code
Integral Nonlinearity vs Output
Code
2.0
0.6
0.5
0
–0.5
–1.0
60000
0.4
0.2
COUNTS
DNL ERROR (LSB)
0
–0.2
–0.4
20000
–0.6
–1.5
–0.8
–2.0
–1.0
0
65536
131072
196608
OUTPUT CODE
262144
0
65536
131072
196608
OUTPUT CODE
DC Histogram (Near Full-Scale)
0
σ = 1.89
262134
–40
–80
–100
–120
–160
0
100
200
300
FREQUENCY (kHz)
400
500
–180
THD, Harmonics vs REFBUF,
fIN = 1kHz
100
200
300
FREQUENCY (kHz)
400
THD, HARMONICS (dBFS)
500
SNR, SINAD vs Input Level,
fIN = 1kHz
96.0
97
92
0
237318 G24
–105
93
20
–120
237318 G23
98
94
18
–100
–160
SNR, SINAD vs REFBUF, fIN = 1kHz
95
16
–80
–140
237318 G22
SINAD
12 14
CODE
–60
–140
–180
262140
SNR
10
SNR = 96.9dB
THD = –111dB
SINAD = 96.7dB
SFDR = 112.8dB
–20
–60
CODE
96
8
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
COUNTS
262128
6
32k Point FFT fSMPL = 1Msps,
fIN = 1kHz, REFBUF = 5V
SNR = 95.1dB
THD = –110dB
SINAD = 94.9dB
SFDR = 113.3dB
–40
0
262122
4
237318 G21
32k Point FFT fSMPL = 1Msps,
fIN = 1kHz
–20
20000
0
262144
237318 G20
237318 G19
40000
40000
THD
–110
95.5
SNR, SINAD (dBFS)
INL ERROR (LSB)
σ = 1.54
0.8
1.0
SNR, SINAD (dBFS)
DC Histogram (Zero-Scale)
80000
1.0
1.5
60000
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
2ND
–115
–120
3RD
95.0
SNR
SINAD
94.5
–125
91
90
2.5
3
4.5
4
3.5
REFBUF VOLTAGE (V)
5
237318 G25
10
–130
2.5
3
4.5
4
3.5
REFBUF VOLTAGE (V)
5
237318 G26
94.0
–40
–30
–20
–10
INPUT LEVEL (dB)
0
237318 G27
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
Pseudo-Differential Unipolar Range, fSMPL = 1Msps, unless otherwise noted.
THD, Harmonics vs Input
Frequency
SNR, SINAD vs Input Frequency
100
95
90
85
80
75
SINAD
70
75
–80
70
CMRR (dB)
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
80
–70
SNR
65
CMRR vs Input Frequency
–60
–90
–100
60
–110
THD
2ND
3RD
–120
0
25
50
75 100 125 150 175 200
FREQUENCY (kHz)
65
–130
0
25
50
55
50
75 100 125 150 175 200
FREQUENCY (kHz)
237318 G28
0
100
237318 G29
500
THD, Harmonics vs Temperature,
fIN = 1kHz
97
95
400
237318 G30
SNR, SINAD vs Temperature,
fIN = 1kHz
PSRR vs Frequency
300
200
FREQUENCY (kHz)
–100
90
SNR, SINAD (dBFS)
PSRR (dB)
80
75
70
65
60
55
SINAD
SNR
THD, HARMONICS (dBFS)
96
85
95
94
93
–105
THD
–110
3RD
2ND
–115
–120
50
100
10
FREQUENCY (kHz)
1
92
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1k
237318 G31
237318 G32
2
Zero-Scale Error vs Temperature
5
4.0
3.5
4
MAX INL
FULL-SCALE ERROR (LSB)
1
INL ERROR (LSB)
237318 G33
Full-Scale Error vs Temperature
REFBUF = 4.096V
INL vs Temperature
0
–1
–125
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
MIN INL
3.0
3
OFFSET ERROR (LSB)
45
2
1
0
237318 G34
2.0
1.5
1.0
0.5
0
–1
–2
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.5
–0.5
–2
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G35
–1.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G36
237318f
For more information www.linear.com/LTC2373-18
11
LTC2373-18
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
Pseudo-Differential Bipolar Range, fSMPL = 1Msps, unless otherwise noted.
Differential Nonlinearity vs
Output Code
Integral Nonlinearity vs Output
Code
2.0
1.0
1.5
0.8
0.6
0.5
0
–0.5
–1.0
0.2
0
–0.2
–0.4
–0.8
0
65536
131072
196608
OUTPUT CODE
–1.0
262144
0
65536
131072
196608
OUTPUT CODE
237318 G37
0
–3
–1
1
CODE
3
5
–40
20000
0
131055 131058 131061 131063 131066 131069
CODE
0
–40
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
SNR = 97.2dB
THD = –109.2dB
SINAD = 96.9dB
SFDR = 112.2dB
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
40000
–180
500
0
100
237318 G41
237318 G40
98
200
300
FREQUENCY (kHz)
400
500
237318 G42
SNR, SINAD vs Input Level,
fIN = 1kHz
THD, Harmonics vs REFBUF,
fIN = 1kHz
SNR, SINAD vs REFBUF, fIN = 1kHz
7
32k Point FFT fSMPL = 1Msps,
fIN = 1kHz, REFBUF = 5V
SNR = 95.6dB
THD = –109.8dB
SINAD = 95.5dB
SFDR = 111.6dB
–20
60000
96.0
–105
THD
97
THD, HARMONICS (dBFS)
SNR
96
SINAD
95
94
93
92
91
3
4.5
4
3.5
REFBUF VOLTAGE (V)
5
237318 G43
12
–5
237318 G39
32k Point FFT fSMPL = 1Msps,
fIN = 1kHz
σ = 1.65
90
2.5
–7
237318 G38
DC Histogram (Near Full-Scale)
80000
0
262144
–110
2ND
95.5
SNR, SINAD (dBFS)
–2.0
COUNTS
40000
20000
–0.6
–1.5
σ = 1.55
60000
0.4
COUNTS
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
SNR, SINAD (dBFS)
DC Histogram (Zero-Scale)
80000
–115
3RD
–120
95.0
94.5
–125
–130
2.5
SNR
SINAD
3
4.5
4
3.5
REFBUF VOLTAGE (V)
5
237318 G44
94.0
–40
–30
–20
–10
INPUT LEVEL (dB)
0
237318 G45
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Typical Performance Characteristics
Pseudo-Differential Bipolar Range, fSMPL = 1Msps, unless otherwise noted.
THD, Harmonics vs Input
Frequency
SNR, SINAD vs Input Frequency
100
90
85
SINAD
80
75
70
65
80
–70
75
–80
70
–90
–100
25
50
75 100 125 150 175
FREQUENCY (kHz)
–130
200
60
THD
2ND
3RD
0
25
50
75 100 125 150 175
FREQUENCY (kHz)
237318 G46
55
50
200
0
100
300
200
FREQUENCY (kHz)
237318 G47
95
500
THD, Harmonics vs Temperature,
fIN = 1kHz
97
90
400
237318 G48
SNR, SINAD vs Temperature,
fIN = 1kHz
PSRR vs Frequency
–100
SNR
SNR, SINAD (dBFS)
80
75
70
65
60
95
THD, HARMONICS (dBFS)
96
85
PSRR (dB)
65
–110
–120
0
CMRR vs Input Frequency
–60
CMRR (dB)
SNR
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
95
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
SINAD
94
93
55
–105
THD
–110
3RD
–115
2ND
–120
50
100
10
FREQUENCY (kHz)
1
92
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1k
237318 G49
237318 G50
2
Zero-Scale Error vs Temperature
3
2.0
1.5
2
MAX INL
FULL-SCALE ERROR (LSB)
INL ERROR (LSB)
237318 G51
Full-Scale Error vs Temperature
REFBUF = 4.096V
INL vs Temperature
1
–125
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
MIN INL
–1
+FS
OFFSET ERROR (LSB)
45
1
0
–FS
–1
–2
–2
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G52
1.0
0.5
0
–0.5
–1.0
–1.5
–3
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G53
–2.0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G54
237318f
For more information www.linear.com/LTC2373-18
13
LTC2373-18
Typical Performance Characteristics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
fSMPL = 1Msps, unless otherwise noted.
Supply Current vs Temperature
10
100
8
200
6
4
2
LEAKAGE CURRENT (nA)
80
IVDD
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
Input Leakage Current vs Temperature
(MUXOUT± Shorted to ADCIN±)
Sleep Current vs Temperature
60
40
20
100
ON CHANNEL, V(CHx,COM) = 5V
OFF CHANNEL, V(CHx,COM) = 5V
ON CHANNEL, V(CHx,COM) = 0V
OFF CHANNEL, V(CHx,COM) = 0V
60
–100
IOVDD
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G55
237318 G56
237318 G57
Internal Reference Output
Temperature Coefficient Distribution
40
2.051
35
2.050
30
NUMBER OF PARTS
2.052
2.049
2.048
2.047
Supply Current vs Sampling Rate
10
8
SUPPLY CURRENT (mA)
Internal Reference Output vs
Temperature
INTERNAL REFERENCE OUTPUT (V)
–200
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
25
20
15
2.046
10
2.045
5
2.044
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
IVDD
6
4
2
IOVDD
0
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12
DRIFT (ppm/°C)
237318 G59
0 100 200 300 400 500 600 700 800 900 1000
SAMPLING FREQUENCY (kHz)
237318 G58
237318 G60
Crosstalk FFT (AC CrosstalkChannel Adjacent to MUXOUT)
0
Crosstalk FFT (AC CrosstalkChannel NOT Adjacent to MUXOUT)
0
SFDR = 107.3dB
fIN = 100kHz
–20
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
SFDR = 130dB
fIN = 100kHz
–20
0
100
200
300
FREQUENCY (kHz)
400
500
–180
0
237318 G61
14
100
200
300
FREQUENCY (kHz)
400
500
237318 G62
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Pin Functions
CH0 to CH7 (Pins 1, 2, 7, 8, 9, 10, 31 and 32): Analog
Inputs. CH0 to CH7 can be configured as single-ended
inputs relative to COM, or as pairs of differential input
channels. See the Analog Input Multiplexer section.
Unused analog inputs should be tied to a DC voltage within
the analog input voltage range of (GND – 0.3V) to (VDD +
0.3V) as specified in Absolute Maximum Ratings.
MUXOUT+, MUXOUT– (Pin 3, Pin 6): Analog Output Pins
of MUX.
ADCIN+, ADCIN– (Pin 4, Pin 5): Analog Input Pins of
ADC Core.
GND (Pins 11, 14, 15, 17, 23, 26, 27 and Exposed Pad
Pin 33): Ground.
REFBUF (Pin 12): Reference Buffer Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 47μF ceramic capacitor. The internal buffer
driving this pin may be disabled by grounding its input
at REFIN. Once the buffer is disabled, an external reference may overdrive this pin in the range of 2.5V to 5V.
A resistive load greater than 500k can be placed on the
reference buffer output.
REFIN (Pin 13): Reference Output/Reference Buffer Input. An onboard bandgap reference nominally outputs
2.048V at this pin. Bypass this pin with a 0.1μF ceramic
capacitor to GND to limit the reference output noise. If
more accuracy is desired, this pin may be overdriven by
an external reference in the range of 1.25V to 2.4V.
CNV (Pin 16): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
RDL (Pin 18): Read Low Input. When RDL is low, the serial
data I/O bus is enabled. When RDL is high, the serial data
I/O bus becomes Hi-Z. RDL also gates the external shift
clock. Logic levels are determined by OVDD.
BUSY (Pin 19): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
SDI (Pin 20): Serial Data Input. Data provided on this pin
in synchrony with SCK can be used to program the MUX
channel configuration, converter input range and digital
gain compression setting via the sequencer. Input data on
SDI is latched on rising edges of SCK when the serial data
I/O bus is enabled. Logic levels are determined by OVDD.
SCK (Pin 21): Serial Data Clock Input. When the serial
data I/O bus is enabled, the conversion result followed
by configuration information is shifted out at SDO on
the rising edges of this clock MSB first. Serial input data
is latched on the rising edges of this clock at SDI. Logic
levels are determined by OVDD.
SDO (Pin 22): Serial Data Output. The conversion result
followed by configuration information is output on this
pin on each rising edge of SCK MSB first when the serial
data I/O bus is enabled. The output data format is determined by the converter operating mode. Logic levels
are determined by OVDD.
RESET (Pin 24): Reset Input. When this pin is brought high,
the LTC2373-18 is reset. If this occurs during a conversion, the conversion is halted and the data bus becomes
Hi-Z. Logic levels are determined by OVDD.
OVDD (Pin 25): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.
VDDLBYP (Pin 28): 2.5V Supply Bypass Pin. The voltage on
this pin is generated via an onboard regulator off of VDD.
This pin must be bypassed with a 2.2μF ceramic capacitor
to GND. Applying an external voltage to this pin can cause
damage to the IC or improper operation.
VDD (Pin 29): 5V Power Supply. The range of VDD is 4.75V
to 5.25V. Bypass VDD to GND with a 10µF ceramic capacitor.
COM (Pin 30): Common Input. This is the reference point
for all single-ended inputs. It must be free of noise and
connected to GND for unipolar conversions and REFBUF/2
for bipolar conversions. If unused, this input should be
tied to a DC voltage within the analog input voltage range
of (GND – 0.3V) to (VDD + 0.3V) as specified in Absolute
Maximum Ratings.
237318f
For more information www.linear.com/LTC2373-18
15
LTC2373-18
Functional Block Diagram
VDD = 5V
OVDD = 1.8V
TO 5V
VDDLBYP = 2.5V
LTC2373-18
LDO
CNV
BUSY
RESET
CONTROL LOGIC
CH0
SEQUENCER
8-CHANNEL MULTIPLEXER
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SPI
PORT
+
RDL
SDO
SDI
SCK
18-BIT SAMPLING ADC
–
15k
2x REFERENCE
BUFFER
MUXOUT–
ADCIN– REFBUF = 2.5V
MUXOUT+ ADCIN+
TO 5V
2.048V
REFERENCE
GND
237318 BD01
REFIN = 1.25V
TO 2.4V
Timing Diagram
Typical Conversion and Serial Interface Timing
RESET = 0
N
N+1
CNV
BUSY
CONVERT
NAP
SCK
RDL
SDO
Hi-Z
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
D7 D6
D5 D4 D3
D2 D1
D0 SOS A3 A2
DATA FROM CONVERSION N
SDI
C7
C6
C5
C4
C3 C2
C1
A1 A0
R1 R0 SEL
Hi-Z
CONFIGURATION WORD
FROM CONVERSION N
C0
237318 TD01
CONFIGURATION WORD
FOR CONVERSION N + 1
16
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
TRANSFER FUNCTION
The LTC2373-18 is a low noise, high speed, highly configurable 8-channel 18-bit successive approximation
register (SAR) ADC. The LTC2373-18 features a low
crosstalk 8-channel input multiplexer (MUX) and a high
performance 18-bit accurate ADC core that can be configured to accept fully-differential, pseudo-differential
unipolar and pseudo-differential bipolar input signals. The
input range of the ADC core can be set independently of
the MUX input channel configuration. The outputs of the
MUX and inputs of the ADC core are pinned out, allowing
flexibility in how the MUX is connected to the ADC core.
The MUX may be wired directly to the ADC core or signal
conditioning circuitry may be inserted between the MUX
and ADC core, depending on the application. The LTC237318 also has a selectable digital gain compression (DGC)
feature. The LTC2373-18 has a programmable sequencer
that can be programmed with configuration words
ranging from a depth of one up to a maximum depth of
16 configuration words.
The LTC2373-18 digitizes the full-scale voltage of 2 ×
REFBUF in fully differential mode and REFBUF in pseudodifferential mode into 218 levels. With REFBUF = 4.096V,
the resulting LSB sizes in fully differential and pseudodifferential modes are 31.25μV and 15.625μV, respectively.
The binary format of the conversion result depends on the
converter input range as described in Table 6. The ideal
two’s complement transfer function is shown in Figure 2,
while the ideal straight binary transfer function is shown in
Figure 3. The ideal straight binary transfer function can be
obtained from the two’s complement transfer function by
inverting the most significant bit (MSB) of each output code.
The LTC2373-18 has an onboard low drift reference and
a single-shot capable reference buffer. The LTC2373-18
also has a high speed SPI-compatible serial interface that
supports 1.8V, 2.5V, 3.3V and 5V logic. The LTC237318 automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided for further power
savings during inactive periods.
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/262144
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
237318 F02
Figure 2. LTC2373-18 Two’s Complement Transfer Function.
Straight Binary Transfer Function Can Be Obtained by Inverting
the Most Significant Bit (MSB) of Each Output Code
The LTC2373-18 operates in two phases. During the acquisition phase when MUXOUT+/– is wired to ADCIN+/–,
the charge redistribution capacitor D/A converter (CDAC)
is connected through the MUX to the selected MUX
analog input pins. A rising edge on the CNV pin initiates
a conversion. During the conversion phase, the 18-bit
CDAC is sequenced through a successive approximation
algorithm, effectively comparing the sampled input with
binary-weighted fractions of the reference voltage (e.g.
VREFBUF/2, VREFBUF/4 … VREFBUF/262144) using a differential comparator. At the end of conversion, the CDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 18-bit digital output code
for serial transfer.
OUTPUT CODE (STRAIGHT BINARY)
CONVERTER OPERATION
111...111
111...110
100...001
100...000
011...111 UNIPOLAR
ZERO
011...110
000...001
FSR = +FS
1LSB = FSR/262144
000...000
0V
FSR – 1LSB
INPUT VOLTAGE (V)
237318 F03
Figure 3. LTC2373-18 Straight Binary Transfer Function
For more information www.linear.com/LTC2373-18
237318f
17
LTC2373-18
Applications Information
ANALOG INPUTS
The LTC2373-18 can be configured to accept one of
three voltage ranges: fully differential (±4.096V), pseudodifferential unipolar (0V to 4.096V), and pseudo-differential
bipolar (±2.048V). In all three ranges, the ADC samples and
digitizes the voltage difference between the two ADC core
analog input pins (ADCIN+ − ADCIN−), and any unwanted
signal that is common to both inputs is reduced by the
common mode rejection ratio (CMRR) of the ADC. The
MUX outputs the voltages of the selected MUX analog input
channels to MUXOUT+/–, according to the MUX configuration. MUXOUT+/– may be wired directly to ADCIN+/– or
connected through a buffer. Refer to the Configuring the
LTC2373-18 section for details on how to select the analog
input range and MUX channel configuration.
Independent of the selected range or channel configuration,
the MUX analog inputs can be modeled by the equivalent
circuit shown in Figure 4. CHx and CHy are distinct input
pins selected from the CH0 to CH7 MUX analog inputs,
depending on the MUX configuration. Each pin has ESD
protection diodes. The ADC core analog inputs, ADCIN+/–,
each see a sampling network consisting of approximately
50pF (CIN) from the sampling CDAC in series with 40Ω
(RON) from the on-resistance of the sampling switch.
The MUX is modeled by a 40Ω resistor representing the
MUX switch on-resistance (RSW) and a capacitance to
VDD
During acquisition, each active MUX analog input sees a
cascade of two first order lowpass filters formed by RSW,
CPAR and the ADC sampling network when MUXOUT+/– is
wired directly to ADCIN+/–. If a buffer is inserted between
MUXOUT+/– and ADCIN+/–, then each active MUX analog
input only sees a first order lowpass filter formed by RSW
and CPAR that is loaded with the input impedance of the
buffer.
Both CIN and CPAR draw current spikes while being charged
during acquisition. If MUXOUT+/– is wired directly to
ADCIN+/–, the current spikes from the charging of both
capacitors are drawn from the active MUX analog inputs.
A buffer inserted between MUXOUT+/– and ADCIN+/– will
absorb the current spike from CIN, leaving the current spike
from CPAR to be drawn from the active MUX analog inputs.
During conversion and sleep, the MUX analog inputs and
ADC core analog inputs draw only a small leakage current.
VDD
VDD
RSW
40Ω
CHX
ground, CPAR, at the output summing node of the MUX.
CPAR is a lumped capacitance on the order of 20pF formed
primarily by pin parasitics and diode junctions. Parasitic
capacitances from the PCB will also contribute to CPAR.
This capacitance is discharged through a switch to ground
every conversion cycle or when a first new configuration is
programmed to minimize crosstalk due to charge sharing
between channels.
RON
40Ω
OR
MUXOUT+
ADCIN+
CIN
50pF
CPAR
20pF
VDD
CHY, COM
RSW
40Ω
BIAS
VOLTAGE
VDD
VDD
OR
MUXOUT–
ADCIN–
RON
40Ω
CIN
50pF
CPAR
20pF
ADC CORE
MUX
237318 F04
Figure 4. Equivalent Circuit for the Differential Analog Inputs of the LTC2373-18
18
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
Fully Differential Input Range
INPUT DRIVE CIRCUITS
The fully differential input range provides the widest
input signal swing, configuring the ADC to digitize the
differential analog input voltage to the ADC core (ADCIN+ −
ADCIN−) provided through the selected MUX analog inputs
over a span of ±VREFBUF. In this range, the ADCIN+ and
ADCIN− pins should be driven 180 degrees out-of-phase
with respect to each other, centered around a common
mode voltage (ADCIN+ + ADCIN−)/2 that is restricted to
(VREFBUF/2 ± 0.1V). Both the ADCIN+ and ADCIN− pins are
allowed to swing from (GND − 0.1V) to (VREFBUF + 0.1V).
Unwanted signals common to both inputs are reduced
by the CMRR of the ADC. The output data format may be
selected as straight binary or two’s complement.
Whether MUXOUT+/− is wired directly to ADCIN+/− or
through a buffer with high input impedance, the MUX
analog inputs of the LTC2373-18 are high impedance. In
either case, a low impedance source can directly drive the
MUX analog inputs without gain error. A high impedance
source should be buffered in both cases to minimize settling time during acquisition and to optimize ADC linearity.
Pseudo-Differential Unipolar Input Range
In the pseudo-differential unipolar input range, the ADC
digitizes the differential analog input voltage to the ADC
core (ADCIN+ − ADCIN−) provided through the selected
MUX analog inputs over a span of (0V to VREFBUF). In this
range, a single-ended unipolar input signal, driven on the
ADCIN+ pin, is measured with respect to the signal ground
reference level, driven on the ADCIN− pin. The ADCIN+
pin is allowed to swing from (GND − 0.1V) to (VREFBUF +
0.1V), while the ADCIN− pin is restricted to (GND ± 0.1V).
Unwanted signals common to both inputs are reduced by
the CMRR of the ADC. The output data format is straight
binary.
Pseudo-Differential Bipolar Input Range
In the pseudo-differential bipolar input range, the ADC
digitizes the differential analog input voltage to the ADC
core (ADCIN+ − ADCIN−) provided through the selected
MUX analog inputs over a span of (±VREFBUF/2). In this
range, a single-ended bipolar input signal, driven on the
ADCIN+ pin, is measured with respect to the signal midscale reference level, driven on the ADCIN− pin. The ADCIN+
pin is allowed to swing from (GND − 0.1V) to (VREFBUF
+ 0.1V), while the ADCIN− pin is restricted to (VREFBUF/2
± 0.1V). Unwanted signals common to both inputs are
reduced by the CMRR of the ADC. The output data format
is two’s complement.
For best performance, a buffer amplifier should be used
to drive the MUX analog inputs of the LTC2373-18 with
MUXOUT+/− wired directly to ADCIN+/−. The amplifier
provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spikes drawn by the MUX analog inputs when
entering acquisition.
Noise and Distortion
The noise and distortion of the buffer amplifiers and signal
sources must be considered since they add to the ADC
noise and distortion. Noisy input signals should be filtered
prior to the inputs of the buffers driving the MUX analog
inputs with an appropriate filter to minimize noise. The
simple 1-pole RC lowpass filter (LPF1) shown in Figure 5
is sufficient for many applications.
Buffer amplifiers with low noise density must be selected
to minimize SNR degradation. Coupling filter networks
(LPF2) should be placed between the buffer outputs and
MUX analog inputs to both minimize the noise contribution of the buffers and reduce disturbances reflected into
the buffer from MUX analog input sampling transients.
If a buffer amplifier is used between MUXOUT+/− and
ADCIN+/−, a coupling filter network (LPF3) should be
placed between the buffer output and ADC core analog
inputs to both minimize the noise contribution of the buffer and reduce disturbances reflected into the buffer from
the ADC core analog input sampling transients. Long RC
time constants at the MUX or ADC core analog inputs will
slow down the settling of those inputs. Therefore, LPF2
and LPF3 typically require wider bandwidths than LPF1.
237318f
For more information www.linear.com/LTC2373-18
19
LTC2373-18
Applications Information
Table 1 lists typical recommended values for the R and C
of each LPF mentioned.
coupling filters that are used to both filter noise and reduce sampling transients due to the current spikes.
Table 1. Recommended R and C Values for Each Lowpass Filter
The MUX and ADC core analog inputs may be modeled
as a switched capacitor load on the drive circuit. A drive
circuit may rely partially on attenuating switched-capacitor
current spikes with small filter capacitors CFILT placed
directly at the ADC inputs and partially on the driver amplifier
having sufficient bandwidth to recover from the residual
disturbance. Amplifiers optimized for DC performance may
not have sufficient bandwidth to fully recover at the ADC’s
maximum conversion rate, which can produce nonlinearity
and other errors. Coupling filter circuits may be classified
in three broad categories:
LPF1
Rx(Ω)
Cx(pF)
BANDWIDTH
50
100000
31.8kHz
LPF2
10
1200
13MHz
LPF3
25
2700
2.4MHz
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Input Currents
One of the biggest challenges in coupling an amplifier to
the LTC2373-18 is in dealing with current spikes drawn
by the MUX and ADC core analog inputs at the start of
each acquisition phase. LPF2 and LPF3 are examples of
Fully Settled: This case is characterized by filter time
constants and an overall settling time that are considerably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2373-18), the disturbance will not contribute any error.
LTC2373-18
CH0
LPF2
CH1
CH2
LPF1
SIGNAL
SOURCES
LPF2
CH3
CH4
LPF1
LPF2
CH5
CH6
LPF1
LPF2
1/2 LPF1
1/2 LPF2
BANDLIMITING
SIGNAL SOURCE
NOISE
BANDLIMITING
BUFFER NOISE
AND REDUCING
SAMPLING TRANSIENTS
8-CHANNEL MULTIPLEXER
LPF1
+
18-BIT ADC CORE
–
CH7
COM
RX
CX
LPFx
RX
CX
MUXOUT+/–
ADCIN+/–
237318 F05
LPF3
BANDLIMITING
BUFFER NOISE
AND REDUCING
SAMPLING TRANSIENTS
Figure 5. Input Signal Chain
20
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
Partially Settled: In this case, the beginning of acquisition
causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switchedcapacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high frequency
energy before it reaches the amplifier.
Fully Averaged: Consider the case where MUXOUT+/– is
directly wired to ADCIN+/–. If the coupling filter’s capacitors (CFILT) at the MUX analog inputs are much larger than
the sum of the ADC’s sample capacitors (50pF) and the
MUX’s output summing node capacitances (20pF), then the
sampling glitch is greatly attenuated. The driving amplifier
effectively only sees the average sampling current, which
is quite small. At 1Msps, the equivalent input resistance is
approximately 14k (as shown in Figure 6), a benign resistive load for most precision amplifiers. However, resistive
voltage division will occur between the coupling filter’s
DC resistance and MUX’s equivalent (switched-capacitor)
input resistance, thus producing a gain error.
CHX
REQ
CFILT >> CTOT
CHY, COM
REQ
LTC2373-18
BIAS
VOLTAGE
CFILT >> CTOT
The first form of crosstalk is often referred to as static
crosstalk. In static crosstalk, a signal applied to an OFF
channel, VINTERFERER, couples capacitively into the input
signal path, thus corrupting the input signal of the ON
channel, VSIGNAL. Figure 7 shows an RC model of two MUX
input channels and the associated parasitic capacitances.
Capacitive coupling from an OFF channel into the input
signal path can occur through CSW of an OFF switch to
the MUXOUT+/– output pins or through CPIN to an adjacent input pin or the MUXOUT+/– output pins. Coupling
through CPIN to the MUXOUT+/– pins is the dominant
coupling mechanism that limits the crosstalk to –107dB
with a 100kHz input signal applied to an OFF CH3 or CH4.
These pins sit adjacent to the MUXOUT+ and MUXOUT–
pins, respectively.
The second form of crosstalk is referred to as adjacent
channel crosstalk, which has to do with memory from the
input of one channel affecting the sampled value of another
channel. In this case, CPAR at the output summing nodes
of the MUX, MUXOUT+/–, can act as memory storage
elements if not dealt with properly. The potential crosstalk mechanism here is through charge sharing. CPAR is
charged approximately to the voltage of each channel that
is sampled. If that charge is not cleared when switching
from one channel to the next, then charge sharing between
the charge on the filter capacitor (CFILT) of one channel
will occur with the charge from another channel stored on
CPAR. The unwanted charge from CPAR can take a long time
to settle out depending on the input filter bandwidth. CPAR
is discharged through a low impedance switch to ground
every conversion cycle or when a first new configuration
is programmed to mitigate this effect.
237318 F06
REQ =
1
fSMPL • CTOT
MUXOUT+/–
CTOT = CIN + CPAR = 70pF
CPAR
Figure 6. Equivalent Circuit for the MUX Analog Inputs of the
LTC2373-18 at 1Msps
Crosstalk
CPIN
VINTERFERER
RSW
CH3/CH4
CSW
CFILT
Crosstalk is a typical concern in systems that employ
multiplexers. The LTC2373-18 features a low crosstalk
8-channel MUX. There are two forms of crosstalk in the
LTC2373-18 that potentially allow the signal from one
channel to corrupt the signal from another channel being
sampled.
OFF CHANNEL
CPIN
VSIGNAL
CH2/CH5
CFILT
RSW
CSW
ON CHANNEL
237318 F07
Figure 7. RC Equivalent Circuit for Two MUX Analog
Input Channels
237318f
For more information www.linear.com/LTC2373-18
21
LTC2373-18
Applications Information
Driving the MUX Analog Inputs
The LTC2373-18 can be programmed to accept fully
differential or pseudo-differential input signals. In most
applications, it is recommended that the LTC2373-18 be
driven using the LT6237 ADC driver configured as two
unity-gain buffers regardless of the input range, as shown
in Figure 8a. The LT6237 combines fast settling and good
DC linearity with a 1.1nV/√Hz input-referred noise den4.096V
sity, enabling it to achieve the full ADC data sheet SNR
and THD specifications for all input ranges, as shown in
the FFT plots in Figures 8b, 8c and 8d. The RC filter time
constant is chosen to allow for sufficient transient settling
of the LTC2373-18 MUX analog inputs during acquisition.
With a maximum supply current of 7.8mA, the LT6237
is a perfect complement to the low power LTC2373-18.
V+
8
MUX CHANNELS
CH0 AND CH1
SELECTED
0V
–
2
1
4.096V
10Ω
+
3
0V
CH1
1200pF
CH2
LT6237
4.096V
+
5
0V
7
10Ω
CH3
1200pF
CH4
–
6
LTC2373-18
CH0
8-CHANNEL MULTIPLEXER
0V
CH5
4.096V
CH6
4
0V
18-BIT ADC CORE
–
CH7
COM
V–
2.048V
+
237318 F08a
MUXOUT+/–
SHORTED TO
ADCIN+/–
Figure 8a. LT6237 Buffering a Fully Differential or Pseudo-Differential Signal Source
–20
–60
–80
–100
–120
0
SNR = 94.8dB
THD = –106.1dB
SINAD = 94.6dB
SFDR = 107.1dB
–20
–40
AMPLITUDE (dBFS)
–40
AMPLITUDE (dBFS)
0
SNR = 100dB
THD = –113dB
SINAD = 99.7dB
SFDR = 113.8dB
–60
–80
–100
–120
–40
–60
–80
–100
–120
–140
–140
–140
–160
–160
–160
–180
100
0
200
300
FREQUENCY (kHz)
400
500
237318 F08b
Figure 8b. 32k Point FFT fSMPL =
1Msps, fIN = 1kHz for Circuit Shown
in Figure 8a; Driven with Fully
Differential Inputs
22
–180
0
100
200
300
FREQUENCY (kHz)
400
500
237318 F08c
Figure 8c. 32k Point FFT fSMPL =
1Msps, fIN = 1kHz for Circuit Shown
in Figure 8a; Driven with Unipolar
Inputs
SNR = 94.8dB
THD = –105.5dB
SINAD = 94.6dB
SFDR = 107.1dB
–20
AMPLITUDE (dBFS)
0
–180
0
100
200
300
FREQUENCY (kHz)
400
500
237318 F08d
Figure 8d. 32k Point FFT fSMPL =
1Msps, fIN = 1kHz for Circuit Shown
in Figure 8a; Driven with Bipolar
Inputs
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
Maximizing SNR with a Single-Ended to Differential
Conversion
0
SNR = 100dB
THD = –106.2dB
SINAD = 99.4dB
SFDR = 108.1dB
–20
–40
AMPLITUDE (dBFS)
A single-ended input signal may be converted to a fully
differential signal prior to driving the MUX analog inputs
of the LTC2373-18 to take advantage of the higher SNR
of the LTC2373-18 in the fully differential input range.
The LT6350 ADC driver shown in Figure 9a can be used
to convert a 0V to 4.096V input signal to a fully differential
±4.096V output signal. The RC time constant is larger in
this case to limit the high frequency noise contribution
of the LT6350. This topology provides a 5dB increase in
SNR over single-ended operation and achieves the full
data sheet SNR performance of the fully differential input
range of 100dB as shown in the FFT plot in Figure 9b. The
maximum supply current of 10.4mA makes the LT6350 a
good companion to the low power LTC2373-18.
–60
–80
–100
–120
–140
–160
–180
0
100
237318 F09b
Figure 9b. 32k Point FFT fSMPL = 1Msps,
fIN = 1kHz for Circuit Shown in Figure 9a
Maximizing SNR for Eight Single-Ended Inputs Using
a Shared Amplifier Between MUXOUT+/– and ADCIN+/–
While converting a single-ended signal to a fully differential signal offers the benefit of higher SNR, two input
channels are required per single-ended input, leading to
a reduced number of single-ended input signals that can
be interfaced to the LTC2373-18. Performing the single-ended to differential conversion using the LT6237
0V
MUX CHANNELS
CH0 AND CH1
SELECTED
LT6350
10Ω
1
–
0V
3300pF
RINT
RINT
10Ω
5
2
3300pF
+
CH3
CH4
CH5
CH6
6
V–
CH1
CH2
3300pF
–
VCM = 2.048V
+
–
LTC2373-18
CH0
4.096V
OUT2
0V
8-CHANNEL MULTIPLEXER
4
+
500
OUT1
3
8
400
4.096V
V+
4.096V
200
300
FREQUENCY (kHz)
+
18-BIT ADC CORE
–
CH7
COM
237318 F09a
MUXOUT+/–
SHORTED TO
ADCIN+/–
Figure 9a. LT6350 Converting a 0V to 4.096V Single-Ended Signal to a ±4.096V Fully Differential Signal
237318f
For more information www.linear.com/LTC2373-18
23
LTC2373-18
Applications Information
inputs achieve an SNR of 99dB with this circuit as shown
in Figure 10b, which is a 4dB improvement in SNR over
single-ended operation.
0
SNR = 99dB
THD = –108dB
SINAD = 98.4dB
SFDR = 107.7dB
–20
SUPPLY CURRENT (mA)
between MUXOUT+/– and ADCIN+/– as shown in Figure 10a
provides the SNR benefits of the fully differential range
without sacrificing additional MUX inputs to do so. Using
the MUX configurations where CH0 to CH7 is output to
MUXOUT+ and COM to MUXOUT– enables eight singleended inputs to be converted with the fully differential
input range. The COM MUX input channel is used in the
feedback connection of the buffer amplifier connected
in a follower configuration to improve the distortion
performance of the circuit. THD degradation would otherwise occur due to the non-linear voltage drop across
the MUX switch from the input current of the buffer and
the non-linear on-resistance of the MUX switch. The 1k
resistor between COM and MUXOUT– maintains negative
feedback around the buffer when the MUX turns OFF, so
that the buffer output does not rail. Eight single-ended
–40
–60
–80
–100
–120
–140
–160
–180
100
0
300
200
FREQUENCY (kHz)
400
500
237318 F10b
Figure 10b. 32k Point FFT fSMPL = 1Msps,
fIN = 1kHz for Circuit Shown in Figure 10a
V+
MUX CHANNELS
CH0 AND COM
SELECTED
6
3
+
1
LT6236
0V
4
–
10Ω
1200pF
2
LTC2373-18
CH0
CH1
5
CH2
CH3
V–
CH4
CH5
CH6
8-CHANNEL MULTIPLEXER
4.096V
+
18-BIT ADC CORE
–
CH7
COM
MUXOUT–
1k
V+
8
MUXOUT+
7
6
5
–
+
ADCIN+
ADCIN–
237318 F10a
24.9Ω
100pF
100pF
499Ω
499Ω
2
–
LT6237
3
4
V–
VCM = 2.048V
2700pF
+
2700pF
1
24.9Ω
+
–
Figure 10a. LT6236 Buffering a Single-Ended 0V to 4.096V Input Signal and the LT6237 Configured to Perform a
Single-Ended to Differential Conversion to the ±4.096V Fully Differential Input Range
24
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
Using Digital Gain Compression for Single Supply
Operation
The LTC2373-18 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be between 10% and 90% of the ±VREFBUF analog input range.
This feature allows the ADC driver to be powered off of a
single positive supply since each input swings between
0.41V and 3.69V with VREFBUF = 4.096V as in Figure 11a.
Needing only a positive supply and ground to power the
VREFBUF = 4.096V
3.69V
0.41V
0V
ADC driver results in additional power savings for the
entire system versus conventional systems that have a
negative supply for the ADC driver.
With DGC enabled, the LTC2373-18 can be driven by the
low power LTC6362 differential driver which is powered
from a single 5V supply. Figure 11b shows how to configure
the LTC6362 to accept a ±3.28V true bipolar single-ended
input signal and level shift the signal to the reduced input
range of the LTC2373-18 when digital gain compression
is enabled. Using the LT6236 to buffer the resistor divider
that creates VCM, the entire signal chain solution can be
powered from a single 5V supply, minimizing power
consumption and reducing complexity. The reduced input
signal swing of this single 5V supply solution limits the
achievable SNR to 98dB, as shown in the FFT of Figure 11c.
To enable DGC, set SEL=1 in the configuration word.
237318 F11a
Figure 11a. Input Swing of the LTC2373-18 with Digital Gain
Compression Enabled and VREFBUF = 4.096V
5V
6
0.1µF
4.096V
+
3
–
4
LT6236
1
5
47µF
2
0.1µF
10µF
1k
VCM
2
V+
3
5
850Ω
150Ω
3.28V
0V
–3.28V
0.22µF
100Ω
0.22µF 850Ω
8
0.41V
1500pF
–
4
V–
1k
6
1500pF
35.7Ω
REFBUF
CH1
CH2
LTC6362
1
VDD
CH0
+
RSOURCE = 50Ω
VSOURCE
35.7Ω
10µF
MUX CHANNELS
CH0 AND CH1
SELECTED
3.69V
1k
CH3
CH4
3.69V
CH5
0.41V
CH6
LTC2373-18
8-CHANNEL MULTIPLEXER
1k
+
18-BIT ADC CORE
–
CH7
DIGITAL GAIN COMPRESSION ENABLED BY SETTING
SEL = 1 IN THE CONFIGURATION WORD
COM
237318 F11b
MUXOUT+/–
SHORTED TO
ADCIN+/–
Figure 11b. LTC6362 Configured to Accept a ±3.28V Input Signal While Running from a Single 5V Supply When
Digital Gain Compression is Enabled in the LTC2373-18
For more information www.linear.com/LTC2373-18
237318f
25
LTC2373-18
Applications Information
0
–40
AMPLITUDE (dBFS)
Internal Reference with Internal Buffer
SNR = 98dB
THD = –106.1dB
SINAD = 97.5dB
SFDR = 110dB
–20
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
FREQUENCY (kHz)
400
500
237318 F11c
Figure 11c. 32k Point FFT fSMPL = 1Msps, fIN = 1kHz for
Circuit Shown in Figure 11b
The LTC2373-18 has an on-chip, low noise, low drift
(20ppm/°C), temperature compensated bandgap reference that is factory trimmed to 2.048V. It is internally
connected to a reference buffer as shown in Figure 12a
and is available at REFIN (Pin 13). REFIN should be bypassed to GND with a 0.1μF ceramic capacitor to minimize
noise. The reference buffer gains the REFIN voltage by 2
to 4.096V at REFBUF (Pin 12). Bypass REFBUF to GND
with at least 47μF ceramic capacitor (X7R, 10V, 1210 size)
to compensate the reference buffer and minimize noise.
LTC2373-18
ADC REFERENCE
There are three ways of providing the ADC reference. The
first is to use both the internal reference and reference
buffer. The second is to externally overdrive the internal
reference and use the internal reference buffer. The third
is to disable the internal reference buffer and overdrive
the REFBUF pin from an external source. The following
tables give examples of these cases and the resulting fully
differential, unipolar and bipolar input ranges.
Table 2. Internal Reference with Internal Buffer
REFIN
FULLY
DIFFERENTIAL UNIPOLAR
BIPOLAR
REFBUF INPUT RANGE INPUT RANGE INPUT RANGE
2.048V
4.096V
±4.096V
0V to 4.096V
±2.048V
Table 3. External Reference with Internal Buffer
FULLY
DIFFERENTIAL UNIPOLAR
BIPOLAR
(OVERDRIVE) REFBUF INPUT RANGE INPUT RANGE INPUT RANGE
REFIN
1.25 (Min)
2.5V
±2.5V
0V to 2.5V
±1.25V
2.048V
4.096V
±4.096V
0V to 4.096V
±2.048V
2.4V (Max)
4.8V
±4.8V
0V to 4.8V
±2.4V
0.1µF
REFBUF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
47µF
6.5k
GND
237318 F12a
Figure 12a. LTC2373-18 Internal Reference Circuit
External Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN
can be easily overdriven by an external reference since a
15k resistor is in series with the reference as shown in
Figure 12b. REFIN can be overdriven in the range from
1.25V to 2.4V. The resulting voltage at REFBUF will be
2 × REFIN. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
LTC2373-18
15k
REFIN
Table 4. External Reference Unbuffered
REFIN
15k
REFIN
2.7µF
FULLY
DIFFERENTIAL UNIPOLAR
BIPOLAR
REFBUF INPUT RANGE INPUT RANGE INPUT RANGE
0V
2.5V
(Min)
±2.5V
0V to 2.5V
±1.25V
0V
5V
(Max)
±5V
0V to 5V
±2.5V
REFBUF
LTC6655-2.048
47µF
BANDGAP
REFERENCE
REFERENCE
BUFFER
6.5k
6.5k
GND
237318 F12b
Figure 12b. Using the LTC6655-2.048 as an External Reference
26
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with
the LTC2373-18 when overdriving the internal reference.
The LTC6655-2.048 offers 0.025% (max) initial accuracy
and 2ppm/°C (max) temperature coefficient for high precision applications. The LTC6655-2.048 is fully specified
over the H-grade temperature range and complements
the extended temperature range of the LTC2373-18 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7μF to 100μF
ceramic capacitor close to the REFIN pin is recommended.
External Reference Unbuffered
The internal reference buffer can also be overdriven from
2.5V to 5V with an external reference at REFBUF as shown
in Figure 12c. To do so, REFIN must be grounded to disable
the reference buffer. A 13k resistor loads the REFBUF pin
when the reference buffer is disabled. To maximize the input
signal swing and corresponding SNR, the LTC6655-5 is
recommended when overdriving REFBUF. The LTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-2.048. By using a 5V
reference, an SNR of 102dB can be achieved. Bypassing
the LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805
size) close to the REFBUF pin is recommended.
LTC2373-18
15k
REFIN
REFBUF
LTC6655-5
BANDGAP
REFERENCE
REFERENCE
BUFFER
Internal Reference Buffer Transient Response
For optimum transient performance, the internal reference
buffer should be used. The internal reference buffer uses a
proprietary design that results in an output voltage change
at REFBUF of less than 1LSB when responding to a sudden
burst of conversions. This makes the internal reference
buffer of the LTC2373-18 truly single-shot capable since
the first sample taken after idling will yield the same result as a sample taken after the transient response of the
internal reference buffer has settled. Figures 14a, 14b,
and 14c show the transient responses of the LTC237318 with the internal reference buffer and with the internal
reference buffer overdriven by the LTC6655-5, both with
a bypass capacitance of 47μF in fully differential, pseudodifferential unipolar, and pseudo-differential bipolar input
ranges, respectively.
DYNAMIC PERFORMANCE
6.5k
47µF
external reference must provide all of this charge with a
DC current equivalent to IREFBUF = QCONV/tCYC. Thus, the
DC current draw of REFBUF depends on the sampling rate
and output code. In applications where a burst of samples
is taken after idling for long periods, as shown in Figure 13,
IREFBUF quickly goes from approximately 380µA to a maximum of 1.5mA for REFBUF = 5V at 1Msps. This step in DC
current draw triggers a transient response in the external
reference that must be considered since any deviation in
the voltage at REFBUF will affect the accuracy of the output
code. If an external reference is used to overdrive REFBUF,
the fast settling LTC6655-5 reference is recommended.
6.5k
GND
237318 F12c
Figure 12c. Overdriving REFBUF Using the LTC6655-5
The REFBUF pin of the LTC2373-18 draws a charge (QCONV)
from the external bypass capacitor during each conversion
cycle. If the internal reference buffer is overdriven, the
Fast fourier transform (FFT) techniques are used to test the
ADC’s frequency response, distortion and noise at the rated
throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s
spectral content can be examined for frequencies outside the
fundamental. The LTC2373-18 provides guaranteed tested
limits for both AC distortion and noise measurements.
CNV
IDLE
PERIOD
IDLE
PERIOD
237318 F13
Figure 13. CNV Waveform Showing Burst Sampling
237318f
For more information www.linear.com/LTC2373-18
27
LTC2373-18
Applications Information
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 15 shows that the LTC2373-18 achieves
a typical SINAD of 100dB (fully differential) at a 1MHz
sampling rate with a 1kHz input.
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
6
4
2
0
0
–2
0 100 200 300 400 500 600 700 800 900 1000
TIME (µs)
237318 F11c
Figure 14a. Transient Response of the LTC2373-18 in the
Fully Differential Input Range
DEVIATION FROM FINAL VALUE (LSBs)
8
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
–60
–80
–100
–120
–160
–180
4
0
100
200
300
FREQUENCY (kHz)
400
500
237318 F15
2
Figure 15. 32k Point FFT fSMPL = 1Msps, fIN = 1kHz
0
Signal-to-Noise Ratio (SNR)
0 100 200 300 400 500 600 700 800 900 1000
TIME (µs)
237318 F14b
Figure 14b. Transient Response of the LTC2373-18 in the
Pseudo-Differential Unipolar Input Range
2
DEVIATION FROM FINAL VALUE (LSBs)
–40
–140
6
–2
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 15 shows
that the LTC2373-18 achieves a typical SNR of 100dB (fully
differential) at a 1MHz sampling rate with a 1kHz input.
Total Harmonic Distortion (THD)
0
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
–2
–4
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
–6
0 100 200 300 400 500 600 700 800 900 1000
TIME (µs)
237318 F14c
Figure 14c. Transient Response of the LTC2373-18 in the
Pseudo-Differential Bipolar Input Range
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
28
SNR = 100.7dB
THD = –114dB
SINAD = 100.5dB
SFDR = 115.3dB
–20
AMPLITUDE (dBFS)
DEVIATION FROM FINAL VALUE (LSBs)
8
THD=20log
V22 + V32 + V42 +…+ VN
V1
2
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics. Figure 15 shows that
the LTC2373-18 achieves a typical THD of –114dB (fully
differential) at a 1MHz sampling rate with a 1kHz input.
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
The LTC2373-18 provides two power supply pins: the 5V
power supply (VDD), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows the
LTC2373-18 to communicate with any digital logic operating
between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2373-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2373-18
has a power-on-reset (POR) circuit that will reset the
LTC2373-18 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 100ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2373-18 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the
LTC2373-18. Once a conversion has been initiated, it cannot
be restarted until the conversion is complete. For optimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2373-18 powers down and begins acquiring the
input signal. It is not necessary to clock out all of the data
and configuration bits before starting a new conversion.
Internal Conversion Clock
The LTC2373-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 527ns. With a mini-
mum acquisition time of 460ns, throughput performance
of 1Msps is guaranteed without any external adjustments.
Auto Nap Mode
The LTC2373-18 automatically enters nap mode after a
conversion has been completed and completely powers
up once a new conversion is initiated on the rising edge of
CNV. During nap mode, only the ADC core powers down
and all other circuits remain active. During nap, data from
the last conversion can be clocked out. The auto nap mode
feature will reduce the power dissipation of the LTC2373-18
as the sampling frequency is reduced. Since full power is
consumed only during a conversion, the ADC core of the
LTC2373-18 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 16.
10
8
SUPPLY CURRENT (mA)
POWER CONSIDERATIONS
IVDD
6
4
2
IOVDD
0
0 100 200 300 400 500 600 700 800 900 1000
SAMPLING FREQUENCY (kHz)
237318 F16
Figure 16. Power Supply Current of the LTC2373-18 vs
Sampling Rate
Sleep Mode
The auto nap mode feature provides limited power savings
since only the ADC core powers down. To obtain greater
power savings, the LTC2373-18 provides a sleep mode.
During sleep mode, the entire part is powered down
except for a small standby current resulting in a power
dissipation of 300μW. To enter sleep mode, toggle CNV
twice with no intervening rising edge on SCK. The part
will enter sleep mode on the falling edge of BUSY from
the last conversion initiated. Once in sleep mode, a rising
237318f
For more information www.linear.com/LTC2373-18
29
LTC2373-18
Applications Information
edge on SCK will wake the part up. Upon emerging from
sleep mode, wait tWAKE ms before initiating a conversion
to allow the reference and reference buffer to wake-up
and charge the bypass capacitors at REFIN and REFBUF.
(Refer to the Timing Diagrams section for more detailed
timing information about sleep mode.)
DIGITAL INTERFACE
The LTC2373-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2373-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial data I/O bus is enabled when RDL is low. Serial
output data is clocked out on the SDO pin and serial input
configuration data is clocked in at the SDI pin when an external
clock is applied to the SCK pin if the serial data I/O bus is
enabled. Serial output data transitions on rising edges of SCK
and serial input data is latched on rising edges of SCK. D17
remains valid till the first rising edge of SCK. After the 18 bits
of the conversion result are shifted out, a start-of-sequence
(SOS) bit followed by the 7-bit control word corresponding
to the conversion result is shifted out. SDO will remain low
after 26 SCK rising edges have been issued. Clocking out the
data and configuration information after the conversion will
yield the best performance. Table 5 lists the minimum shift
clock frequency needed to achieve 1Msps throughput when
shifting out a different number of bits.
Configuring the LTC2373-18
The various modes of operation of the LTC2373-18 are
programmed by seven bits of an 8-bit control word, C[7:0].
The control word is shifted in at SDI on the rising edges
of SCK, MSB first. The control word is defined as follows:
C[7]
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
X
A[3]
A[2]
A[1]
A[0]
R[1]
R[0]
SEL
The MSB of the control word, C[7], is used during the
programming of the sequencer and does not control
the operating mode or configuration of the MUX or ADC
(see Programming the Sequencer section). Referring to
Table 6, bits A[3:0] (C[6:3]) control the analog input MUX
channel configuration. Bits R[1:0] (C[2:1]) control the
input range configuration of the ADC and the SEL (C[0])
bit enables/disables the digital gain compression feature
(see Using Digital Gain Compression for Single Supply
Operation section).
Table 6. Description of Decoded Configuration Bits
BITS
NAME
[A3:A0] MUX Channel
Configuration Bits
See Table 7
[R1:R0] Input Range
Selection Bits
00 – Pseudo-Differential Unipolar Input
(Straight Binary Output Data Format)
01 – Pseudo-Differential Bipolar Input
(Two’s-Complement Output Data
Format)
10 – Fully Differential Input
(Straight Binary Output Data Format)
11 – Fully Differential Input
(Two’s-Complement Output Data
Format)
SEL
0 – Digital Gain Compression Disabled
1 – Digital Gain Compression Enabled
Table 5. Minimum Shift Clock Frequency vs Number of Bits for 1Msps
NUMBER OF BITS
fSCK(MHz)
Conversion Result
18
41
Conversion Result + SOS Bit
19
44
Conversion Result + SOS Bit +
Configuration Data
26
60
The configuration of the LTC2373-18 is programmed via
a sequencer through the serial interface. The following
sections describe the various ways the LTC2373-18 can be
programmed, the operation of the sequencer and general
use of the LTC2373-18.
30
BEHAVIOR
Digital Gain
Compression Bit
Note: Digital gain compression feature always disabled for the pseudodifferential unipolar input range.
Analog Input Multiplexer
The analog input MUX is programmed by the A[3:0]
(C[6:3]) bits of the input control word. Table 7 lists the
MUX configurations for all combinations of the configuration bits. The selected positive (+) channel is output
to MUXOUT+ and the selected negative (−) channel is
output to MUXOUT−. Figure 17 shows an example of the
MUX configuration being updated on successive conversions. Note how the voltages of the selected positive (+)
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
CONVERSION #1
(+)
(–)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
MUXOUT+
MUXOUT–
V(CH0)
CONVERSION #2
(+)
ADCIN+
V(CH1)
ADCIN–
18-BIT
ADC CORE
(–)
R[1:0] = 10
FULLY DIFFERENTIAL
STRAIGHT BINARY
MUX
A[3:0] = 0000
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
MUXOUT+
V(CH2)
ADCIN+
MUXOUT–
V(COM)
ADCIN–
MUX
A[3:0] = 1010
18-BIT
ADC CORE
R[1:0] = 00
PSEUDO-DIFFERENTIAL
UNIPOLAR
237318 F17
Figure 17. Changing the Configuration of the LTC2373-18 on Successive Conversions
and negative (−) channels are output at MUXOUT+ and
MUXOUT−, respectively.
Table 7. Channel Configuration
MUX CONFIGURATION
BITS
MULTIPLEXER CONFIGURATION
A[3] A[2] A[1] A[0] CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
+
–
+
–
+
–
–
+
–
–
+
+
–
+
–
+
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
Sequencer
The LTC2373-18 features a sequencer that can store up
to 16 7-bit control words in internal memory. The 7-bit
control word is defined in the Configuring the LTC2373-18
section. The sequencer repeatedly cycles through the
control words stored in sequencer memory on successive conversions if no new valid control words are input
to the part in a given transaction. The sequencer memory
is shown in Figure 18a.
An internal memory pointer determines which of the up
to 16 programmed control words is currently controlling
the converter. The pointer is reset to point to the first programmed control word each time the sequencer memory is
programmed. Upon reaching the final programmed control
word stored in memory, the pointer is automatically reset
to the first memory location and the sequence is restarted.
At power-up or after resetting the LTC2373-18, the internal
sequencer memory programming defaults to a depth of 1
with control word C0[6:0] = 0000000 (CH0+/CH1–, unipolar
input range, digital gain compression disabled). Figure
18b shows the sequencer memory programmed with 8
configurations along with the memory pointer location for
conversions run after programming.
Start of Sequence
The start of sequence (SOS) bit is output to SDO on the
19th SCK cycle during all SPI transactions and indicates
whether the configuration for the conversion just performed corresponds to the control word stored in the
first memory location of the sequencer memory. When
SOS=1, the current configuration corresponds to the first
memory location of the sequencer. The SOS bit can be
used to align the conversion data with the corresponding
control word when truncated SPI transactions are used
to maximize throughput. Only one extra bit needs to be
shifted out to maintain alignment of the configuration
with the conversion data. This results in needing 19 SCK
cycles instead of 26, which allows a higher throughput
to be achieved while being able to keep the configuration
information properly aligned with the conversion data.
237318f
For more information www.linear.com/LTC2373-18
31
LTC2373-18
Applications Information
SEQUENCER MEMORY
7-BITS WIDE
SEQUENCER PROGRAMMED
WITH EIGHT CONTROL WORDS
C0[6:0]
C1[6:0]
C2[6:0]
C3[6:0]
C4[6:0]
C5[6:0]
C6[6:0]
C7[6:0]
C8[6:0]
C9[6:0]
C10[6:0]
C11[6:0]
C12[6:0]
C13[6:0]
C14[6:0]
C15[6:0]
C0[6:0]
C1[6:0]
C2[6:0]
C3[6:0]
C4[6:0]
C5[6:0]
C6[6:0]
C7[6:0]
X
X
X
X
X
X
X
X
16
CONTROL
WORDS
237318 F18a
1ST CONVERSION
2ND CONVERSION
3RD CONVERSION
4TH CONVERSION
5TH CONVERSION
6TH CONVERSION
7TH CONVERSION
8TH CONVERSION
9TH CONVERSION
10TH CONVERSION
11TH CONVERSION
12TH CONVERSION
13TH CONVERSION
14TH CONVERSION
15TH CONVERSION
16TH CONVERSION
....
MEMORY POINTER
LOCATION
237318 F18b
Figure 18a. Internal Sequencer Memory
Figure 18b. Sequencer Programmed with Eight Control Words and the
Memory Pointer Location for Conversions Run After Programming
Programming the Sequencer
Transaction Window
A transaction window opens at power-up, after resetting
the LTC2373-18, and every conversion cycle at the falling
edge of BUSY, allowing the sequencer to be programmed.
Once the transaction window opens, the state machine
controlling the programming of the sequencer memory is
in a reset state, waiting for control words to be shifted in
at SDI. The transaction window closes at the start of the
next conversion when BUSY transitions from low to high,
as shown in Figure 19. Serial input data at SDI is ignored
by the sequencer state machine when BUSY is high.
Input Control Word
The input control word is used to determine whether or
not the sequencer is being programmed. In many cases
the user will simply need to configure the converter once
for their specific application after power-up or resetting
the part, and then drive the SDI pin to GND. This will force
the control word bits to all zeros and the converter will
automatically sequence through the configurations stored
in sequencer memory. The following sections provide
further details on programming the sequencer.
The sequencer memory may be programmed by inputting
one or more valid control words at SDI. Each control word is
an 8-bit word as described in the Configuring the LTC237318 section. A valid input control word is one where C[7] = 1
and the remaining lower 7-bits, C[6:0], have been shifted
in before the transaction window closes as shown in
Figure 20a. When the 1st control word is successfully entered on the 8th rising edge of SCK, the sequencer memory
is cleared, the new configuration, C[6:0], is written into
the first memory location and is applied to the converter.
At this point, a new acquisition window begins since the
CNV
BUSY
237318 F19
TRANSACTION WINDOW
Figure 19. Sequencer Programming Transaction Window
32
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
new configuration may result in a different channel being
acquired. Additional valid input control words are written
into subsequent memory locations. The sequencer only
stores valid input control words and discards control words
that are partially written or have C[7] = 0. If C[7] = 0 at any
point during sequencer programming, the LTC2373-18
closes the input transaction window until the completion
of the next conversion as shown in Figure 20b. Figure 21
shows a truncated programming transaction where the
first partial input control word is discarded and the second
complete input control word is successfully programmed.
The transaction window also closes after 16 successive
valid input control words have been written, since the
sequencer memory has been filled.
CNV
BUSY
RDL
SCK
1
SDI
DON’T CARE
C[7]
Hi-Z
SDO
D17
2
3
4
5
6
7
8
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
D16
D15
D14
D13
START OF NEW
TRANSACTION
WINDOW
D12
D11
D10
D9
1ST VALID CONTROL WORD ENTERED
SEQUENCER MEMORY CLEARED AND UPDATED
NEW CONFIGURATION APPLIED
NEW ACQUISITION PERIOD BEGINS
237318 F20a
Figure 20a. Valid Control Word Successfully Programmed, C[7] = 1
CNV
BUSY
RDL
SCK
SDI
SDO
1
DON’T CARE
2
3
4
D17
6
7
8
DON’T CARE
C[7]
Hi-Z
5
D16
D15
D14
D13
D12
D11
D10
D9
237318 F20b
START OF NEW
TRANSACTION
WINDOW
TRANSACTION WINDOW CLOSED
Figure 20b. Invalid Control Word Entered, C[7] = 0
237318f
For more information www.linear.com/LTC2373-18
33
LTC2373-18
Applications Information
CNV
BUSY
RDL
SCK
SDI
1
DON’T CARE
C[7]
2
3
4
A[3]
A[2]
A[1]
5
1
2
3
C[7]
A[3]
A[2]
6
A[0] R[1]
DON’T CARE
PARTIAL CONTROL
WORD DISCARDED
SDO
Hi-Z
D17
START OF NEW
TRANSACTION
WINDOW
D16
D15
D14
D13
4
5
A[1] A[0]
6
7
8
R[1]
R[0] SEL
D12
D11
VALID CONTROL
WORD ACCEPTED
D12
Hi-Z
TRANSACTION
WINDOW CLOSED
D17
D16
START OF NEW
TRANSACTION
WINDOW
PARTIAL CONTROL
WORD DISCARDED
D15
D14
D13
D10
Hi-Z
1ST VALID CONTROL WORD ENTERED
SEQUENCER MEMORY CLEARED AND UPDATED
NEW CONFIGURATION APPLIED
NEW ACQUISITION PERIOD BEGINS
237318 F21
Figure 21. Truncated Programming Transaction Followed by the Successful Programming of One Configuration
34
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Applications Information
Programming the Sequencer with Two Configurations
ing and after the programming process. The first stored
configuration will instruct the converter to sample a fully
differential signal on the CH7+/CH6– pair with digital gain
compression disabled, and the second stored configuration will instruct the converter to sample a unipolar signal
on the CH3/COM pair with digital gain compression disabled. The converter will then alternate between the two
programmed configurations on successive conversions.
Note that configurations stored in sequencer memory are
retained until the power is cycled, the part is reset, or a
new series of configuration programming words are input.
Figure 22 illustrates the sequencer memory being programmed while reading out a conversion result. C[7] of
the first two input control words is 1, so these control
words are valid and are written to sequencer memory
in succession. C[7] of the third control word is 0, so the
input transaction is terminated at this point. Since there
were only two valid control words entered, the sequencer
memory is programmed with a depth of two. Figure 23
shows the state of the sequencer memory before, durCNV
BUSY
RDL
SCK
SDI
1
DON’T CARE
C[7]
2
3
4
A[3]
A[2]
A[1]
6
7
8
9
10
11
12
A[0] R[1]
R[0]
SEL
C[7]
A[3]
A[2]
A[1]
5
CONTROL WORD #1
SDO
Hi-Z
D17
D16
D15
D14
START OF NEW
TRANSACTION
WINDOW
D13
13
A[0]
14
15
R[1]
R[0]
16
17
SEL C[7]
18
DON’T CARE
CONTROL WORD #2
D12
D11
D10
D9
D8
D7
D6
1ST VALID CONTROL WORD ENTERED
SEQUENCER MEMORY CLEARED AND UPDATED
NEW CONFIGURATION APPLIED
NEW ACQUISITION PERIOD BEGINS
D5
D4
D3
D2
D1
D0
Hi-Z
TRANSACTION
WINDOW CLOSED
2ND VALID CONTROL WORD ENTERED
237318 F22
SEQUENCER MEMORY UPDATED
Figure 22. Sequencer Programmed with Two Control Words
SEQUENCER MEMORY
FROM PREVIOUS
PROGRAMMING
SEQUENCER MEMORY
AFTER PROGRAMMING
1ST CONTROL WORD
SEQUENCER MEMORY
AFTER PROGRAMMING
2ND CONTROL WORD
C0[6:0]
C1[6:0]
C2[6:0]
C3[6:0]
C4[6:0]
C5[6:0]
C6[6:0]
C7[6:0]
C8[6:0]
C9[6:0]
C10[6:0]
C11[6:0]
C12[6:0]
C13[6:0]
C14[6:0]
C15[6:0]
C0[6:0] = 0111100
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C0[6:0] = 0111100
C1[6:0] = 1011000
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1ST CONVERSION
2ND CONVERSION
3RD CONVERSION
4TH CONVERSION
....
MEMORY POINTER
LOCATION
237318 F23
Figure 23. Sequencer Memory Before, During and After Programming
237318f
For more information www.linear.com/LTC2373-18
35
LTC2373-18
Timing Diagrams
MUX Reset Timing
The MUX turns OFF and begins resetting tCNVMRST ns
after a conversion is initiated by the rising edge of CNV.
After tMRST1 ns, the MUX turns ON to the next channel
programmed in the sequencer.
The parasitic capacitances (CPAR) on the output summing
nodes of the MUX, MUXOUT+/–, are discharged to ground
every conversion cycle and when a first new valid configuration word is programmed into the sequencer. This
is done to avoid crosstalk between input channels due to
charge sharing from CPAR. The bottom most waveform in
Figure 24 represents the voltages of the MUX output nodes.
The MUX is being reset when V(MUXOUT+/–) sits at 0V.
The MUX also turns OFF and resets after tVLDMRST ns when
a first new valid configuration word is programmed into the
sequencer on the 8th rising edge of SCK. This is because
the MUX may need to switch channels based on the newly
input configuration, so memory of the previous channel
needs to be cleared. A new acquisition period begins when
the MUX is reconnected after tMRST2 ns.
tCNVMRST
tACQ
CNV
BUSY
SCK
1
SDI
C[7]
SDO
V(MUXOUT+/–)
D17
tMRST1
2
C[6]
D16
3
C[5]
D15
4
C[4]
D14
5
6
C[3]
C[2]
D13
D12
7
C[1]
D11
tVLDMRST
9
8
10
11
12
13
14
15
16
17
18
C[0]
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SOS
tMRST2
237318 F24
0V
Figure 24. MUX Reset Timing
36
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Timing Diagrams
Single Device, Sequencer Not Programmed
available at the falling edge of BUSY. The start-of-sequence
(SOS) bit followed by the current configuration is shifted
out after the conversion data.
RDL enables or disables the serial data I/O bus. If RDL is
high, the serial data I/O bus is disabled and the serial shift
clock SCK is ignored. If RDL is low, SDO is driven and
serial input data may be shifted in at SDI. Figure 25 shows
a single LTC2373-18 operated with RDL and RESET tied
to ground. With RDL grounded, the serial data I/O bus is
enabled and the MSB(D17) of the new conversion data is
Bringing SDI low during data readback as shown closes
the sequencer programming window at the first rising
edge of SCK after the falling edge of BUSY since C[7] = 0.
As a result, the sequencer is not programmed.
CONVERT
DIGITAL HOST
CNV
RDL
RESET
LTC2373-18
BUSY
IRQ
SDO
SCK
DATA IN
SDI
SDI
CLK
NAP AND
ACQUIRE
CONVERT
NAP AND ACQUIRE
tCYC
RDL = 0
RESET = 0
CNV
CONVERT
tCNVL
tCNVH
tACQ = tCYC – tCONV – tBUSYLH
tACQ
BUSY
tCONV
tSCK
tBUSYLH
SCK
1
2
3
17
18
tSCKH
19
20
21
22
tQUIET
23
24
25
26
tSCKL
tHSDO
tDSDO
SDI
tDSDOBUSYL
SDO
D17
D16
D15
D0
SOS
A[3]
A[2]
A[1]
A[0]
R[1]
R[0]
SEL
237318 F25
Figure 25. Using a Single LTC2373-18 without Programming the Sequencer
237318f
For more information www.linear.com/LTC2373-18
37
LTC2373-18
Timing Diagrams
Single Device, Sequencer Programmed
open, a valid input configuration is detected on the 8th
rising edge of SCK. At this point, the MUX turns OFF and
resets and sequencer memory is reset and updated with
the new configuration. The new channel configuration is
applied when the MUX turns ON, marking the beginning
of a new acquisition period.
Figure 26 shows the timing for a single device being
operated with RDL and RESET tied to ground. With RDL
grounded, the serial data I/O bus is enabled and the
MSB(D17) of the new conversion data is available at the
falling edge of BUSY. The start-of-sequence (SOS) bit
followed by the configuration used for the conversion just
performed is shifted out after the new conversion data.
‘On the Fly’ Device Programming
The sequencer may be programmed with one control
word as shown in Figure 26 every conversion cycle to
achieve complete flexibility in the multiplexer configuration, input range and digital gain compression setting on
each conversion.
When SDI is high at the first rising edge of SCK after
the falling edge of BUSY as shown, the sequencer programming window stays open, allowing the sequencer to
be programmed. With the sequencer programming window
NAP
NAP
CONVERT
CONVERT
RDL = 0
RESET = 0
CNV
tCNVL
tCNVH
tVLDMRST + tMRST2 + tACQ
BUSY
tCONV
tBUSYLH
tSCK
tSCKH
SCK
1
2
3
4
5
6
7
9
8
tSSDISCK
tSCKL
tHSDISCK
SDI
C[7]
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
D17
D16
D15
D14
D13
D12
D11
D10
tQUIET
23
24
25
26
tHSDO
tDSDO
tDSDOBUSYL
SDO
D9
R[1]
R[0]
SEL
237318 F26
Figure 26. Using a Single LTC2373-18 Programming the Sequencer
38
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Timing Diagrams
Multiple Devices
avoid bus conflicts. RDL must also be used to selectively
program each ADC through the shared SDI input line. The
RDL inputs idle high and are individually brought low to read
data out of and selectively program each device between
conversions. When RDL is brought low, the MSB(D17)
of the selected device is output onto SDO.
Figure 27 shows the multiple LTC2373-18 devices operating and sharing CNV, SDI, SCK and SDO. By sharing CNV,
SDI, SCK and SDO, the number of signals required to
operate multiple ADCs in parallel is reduced. Since SDO is
shared, the RDL input of each ADC must be used to allow
only one LTC2373-18 to drive SDO at a time in order to
RDLB
RDLA
CONVERT
CNV
RDL
RESET
DIGITAL HOST
CNV
LTC2373-18
B
SCK
BUSY
RDL
SDI
RESET
LTC2373-18
A
SDO
SCK
BUSY
IRQ
SDI
SDO
SDI
DATA IN
CLK
NAP
CONVERT
NAP
CONVERT
RESET = 0
tCNVL
CNV
tCNVH
BUSY
tCONV
tBUSYLH
RDLA
RDLB
tSCK
SCK
1
2
3
16
17
19
18
tSSDISCK
tHSDISCK
SDI
SDO
DON’T CARE
Hi-Z
D16A
D15A
21
34
35
36
CB[7] CB[6] CB[5]
tHSDO
tDSDO
D17A
20
tSCKL
CA[7] CA[6] CA[5]
tEN
tQUIET
tSCKH
tDIS
D1A
D0A
Hi-Z
D17B
D16B D15B
D1B
D0B
Hi-Z
237318 F27
Figure 27. Multiple Devices Sharing CNV, SCK and SDO
237318f
For more information www.linear.com/LTC2373-18
39
LTC2373-18
Timing Diagrams
Sleep Mode
The LTC2373-18 automatically naps and starts acquiring
the input once a conversion has completed. Only the ADC
core powers down in nap mode. As a result, the auto nap
feature provides limited power savings. To obtain greater
power savings, the LTC2373-18 provides a sleep mode.
During sleep mode, the entire part is powered down except
for a small standby current resulting in a 300μW power
dissipation. To enter sleep mode, toggle CNV twice with no
intervening rising edge on SCK as shown in Figure 28. The
RDL = DON’T CARE
SDI = DON’T CARE
CONVERT
NAP
part will enter sleep mode on the falling edge of BUSY from
the last conversion initiated. Once in sleep mode, a rising
edge on SCK will wake the part up. Upon emerging from
sleep mode, wait tWAKE ms before initiating a conversion
to allow the reference and reference buffer to wake-up and
charge the bypass capacitors at REFIN and REFBUF. The
serial data I/O bus is enabled or disabled by RDL during
sleep mode. Sleep mode does not affect the state of the
sequencer memory or memory pointer.
SLEEP
CONVERT
tCNVH
NAP
CONVERT
tWAKE
CNV
BUSY
tCONV
tCONV
tBUSYLH
SCK
RDL = DON’T CARE
SDI = DON’T CARE
CONVERT
SLEEP
tCNVH
NAP
CONVERT
tWAKE
CNV
BUSY
tCONV
tBUSYLH
SCK
237318 F28
Figure 28. Sleep Mode Timing Diagram
40
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Timing Diagrams
RESET Timing
When the RESET pin is high, the LTC2373-18 is reset and
the serial I/O data bus is put into a high impedance mode,
as shown in Figure 29. The serial data output register and
sequencer memory are also cleared and set to their default
states. If this occurs during a conversion, the conversion
is immediately halted. During reset, requests for new
conversions are ignored. Once RESET returns low, the
LTC2373-18 is ready to start a new conversion after the
acquisition time has been met.
tRESETH
RESET
tACQ
CNV
SDO
Hi-Z
237318 F29
Figure 29. RESET Pin Timing
Board Layout
To obtain the best performance from the LTC2373-18
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC2071, the
evaluation kit for the LTC2373-18.
237318f
For more information www.linear.com/LTC2373-18
41
LTC2373-18
Board Layout
Figure 30. Top Silkscreen
42
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Board Layout
Figure 31. Layer 1 Component Side
237318f
For more information www.linear.com/LTC2373-18
43
LTC2373-18
Board Layout
Figure 32. Layer 2 Ground Plane
44
237318f
For more information www.linear.com/LTC2373-18
LTC2373-18
Board Layout
Figure 33. Layer 3 Power Plane
237318f
For more information www.linear.com/LTC2373-18
45
LTC2373-18
Board Layout
Figure 34. Layer 4 Bottom Layer
46
237318f
For more information www.linear.com/LTC2373-18
VCM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
GND
CM
C28
1500pF
C25
1500pF
C23
3300pF
C21
3300pF
C20
OPT
C16
OPT
C14
1200pF
C8
1200pF
JP9
COM
1
2
3
C26
OPT
CM
C22
3300pF
C17
OPT
C9
OPT
R21
10
1
BUFOUT
R128
0
R130
OPT
R129
OPT
EN
C37
OPT
R24
0
C36
0.1uF
-
+
-
+
V-
R8
0
V+
4
3
R7
OPT
1
V-
-
U7A
OPT
R15
0
+
C35
10uF
25V
0805
LT6236CS6
U8
C104
OPT
R18
OPT
C29
OPT
2
3
C27
OPT
R14
OPT
7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
OPT
U7B
31
32
1
2
7
8
9
10
30
C31
1200pF
6
5
C32
0.1uF V+
C103
OPT
R17
OPT
R13
OPT
R131
OPT
6
2
4
6
8
*
EXT_CM
E2
EXT
2.5V
2.048V
GND
C30
1uF
C24
OPT
HD2X4-100
1
3
5
7
JP2
R16
OPT
C11
0.1uF
U1
LTC237X
C15
OPT
C10
10uF
25V
0805
VDD
0805 25V
C7
10uF
C6
0.1uF
CNV
SCK
SDI
SDO
BUSY
R23
1k
R22
221
R20
787
R19
OPT
RDL
RESET
2
EXT
INT
5
33
5
6
7
8
GND
GND
VOUT_S GND
VIN
SHDN
VOUT_F
GND
4
3
2
V+
REFBUF
1
5
6
4
C34
1uF
C18
0.1uF
VCCIO
U2
4
1
CLR
GND
NC7SZ04P5X
R10 33
R9
3
LTC6655BHMS8-4.096
R12
1k
JP1
REF
R4
1k
R1
1k
U9
R11
1k
C19
4.7uF
1
2
3
C13
47uF 10V
1210
X7R
REFBUF
R3
49.9
1206
C3
0.1uF
C33
2.2uF
18
24
16
21
20
22
19
REFBUF
E1
BNC
C12
0.1uF
J1
VCCIO
CLK
100MHz MAX
3.3VPP
25
8
4
BUFOUT
5
For more information www.linear.com/LTC2373-18
2
3
8CH-MUX
4
8
MUXOUT+
MUXOUT-
6
29
VDD
28
VDDLBYP
12
OVDD
4
ADCIN+
ADCIN5
REFIN
13
REFBUF
GND
GND
GND
GND
GND
OGND
GND
GND
27
17
15
14
11
26
23
33
C1
0.1uF
VCC
2
B
A
R6
33
OE
PR
VCC
D
Q
CP
Q
3
1
2
5
4
U6
R5
33
C4
0.1uF
NC7SZ66P5X
3
U4
7
8
VCCIO
U3
4
C2
0.1uF
4
NC7SZ04P5X
NL17SZ74
2
VCCIO
5
3
VCCIO
GND
R2
33
VCCIO
5
3
VCCIO
U5
CNV SCK SDI
NC7SZ04P5X
2
C5
0.1uF
BUSY
SDO
WRIN
BUSY
CNV
SCK
SDI
SDO
WRIN
CSB
CLKIN
LTC2373-18
Schematics
237318f
47
+/- 8.192V
AIN2
0V - 4.096V
AIN1-
0V - 4.096V
J4
J3
J2
BNC
BNC
BNC
C79
OPT
1206
R112
0
C91
10uF
6.3V
AC DC
C92
OPT
1206
JP8
-
+
U25A
C98
10uF
25V 0805
1
LT1469CS8
OPAMP-
2
3
C93
10uF
25V 0805
R110
OPT
C89
10uF
6.3V
R97
OPT
R106
OPT
CM2
JP6
OPAMP+
AC DC
C96
OPT
-IN1
COUPLING
R109
0
+IN1
COUPLING
3
2
1
AIN1+
C77
10uF
6.3V
3
2
1
R94
0
8
4
R134
20
R95
24.9
R125
20k
R116
20k
R107
24.9
6.3V
-
+
V-
3
2
R137
OPT
6
5
C90
15pF
C99
10uF
C80
15pF
V+
8
4
4
6
5
-
+
R105
10
R96
10
C0G
C102
0.01uF
C0G
C106
0.01uF
R126
10k
7
R135
20
3
20
4
2
20
R132
1
R133
R108
OPT
R92
OPT
LT1469CS8
U25B
C105
0.01uF
C0G
LT6237CMS8
U24A
1
R104
24.9
C86
OPT
C84
OPT
R101
24.9
C82
0.1uF
7
LT6237CMS8
U24B
C75
0.1uF
R120
4.99k
8
C74
10uF
6.3V
8
4
EP
R4
R3
R2
R1
5
6
7
8
LT5400ACMS8E-4
U26
R121
0
R113
0
E13
CH3
CH2
VCM
CH1
CH0
CM2
CM2
R90
0
CM
AIN3
+/- 4.096V
AIN4-
+/- 4.096V
AIN4+
0V - 4.096V
CM
J7
J6
J5
BNC
BNC
BNC
R98
0
R122
100
R114
0
IN3
COUPLING
C81
OPT
1206
C78
10uF
6.3V
AC DC
3
2
1
R124
OPT
R117
150
JP7
C100
0.22uF
C0G
1812
C97
0.22uF
C0G
1812
R100
OPT
R93
OPT
CM2
R123
1k
R115
1k
CM
C83
15pF
C76
10uF
6.3V
C85
1uF
2
1
8
+IN2
+IN1
C94
0.1uF
C87
10uF
6.3V
R102
499
8
C72
1uF
+
-
-
+
C73
0.1uF
V+
-
+
C108
0.01uF
R127
1k
+
-
CM
4
5
C101
10uF
6.3V
U28
OUT2
-IN1
OUT1
5
1
4
U27
R119
35.7
R118
35.7
LT6350CMS8
LTC6362CMS8
VDD
C95
4.7uF 10V
R111
1k
C107
0.01uF
C88
0.1uF V-
7
SHDN
3
V+
V6
R91
OPT
9
3
7
V+
SHDN
For more information www.linear.com/LTC2373-18
6 V2 VOCM
+
48
-
CM2
R103
10
R99
10
CH7
CH6
CH4
CH5
LTC2373-18
Schematics
237318f
LTC2373-18
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
237318f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC2373-18
49
LTC2373-18
Typical Application
LTC6362 Configured to Accept a ±10V Input Signal Using a Single 5V Supply with Digital
Gain Compression Enabled on the LTC2373-18
5V
6
1
LT6236
10µF
1k
10µF
150Ω
–10V
1k
2
850Ω
V+
8
100Ω
3
5
35.7Ω
1
850Ω
RSOURCE = 50Ω
4
4
35.7Ω
6
333Ω
1500pF
47µF
MUX CHANNELS
CH0 AND CH1
SELECTED
REFBUF
VDD
CH1
CH2
–
10µF
CH0
1500pF
+
V–
VSOURCE
–
2
0.41V
LTC6362
LTC6362
0.22µF
3
3.69V
333Ω
0.22µF
10V
0V
VCM
5
+
CH3
CH4
3.69V
CH5
0.41V
CH6
LTC2373-18
8-CHANNEL MULTIPLEXER
4.096V
+
18-BIT ADC CORE
–
CH7
DIGITAL GAIN COMPRESSION ENABLED BY SETTING
SEL = 1 IN THE CONFIGURATION WORD
COM
237318 TA02
MUXOUT+/– SHORTED TO ADCIN+/–
Related Parts
PART NUMBER
ADCs
LTC2378-20/LTC2377-20
LTC2376-20
LTC2379-18/LTC2378-18
LTC2377-18/LTC2376-18
LTC2380-16/LTC2378-16
LTC2377-16/LTC2376-16
LTC2369-18/LTC2368-18
LTC2367-18/LTC2364-18
LTC2370-16/LTC2368-16
LTC2367-16/LTC2364-16
DACs
LTC2756
LTC2641
LTC2630
References
LTC6655
LTC6652
Amplifiers
LT6237/LT6236
LT6350
LTC6362
DESCRIPTION
COMMENTS
20-Bit, 1Msps/500ksps/250ksps, ±0.5ppm
INL Serial, Low Power ADC
18-Bit, 1.6Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
16-Bit, 2Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
18-Bit, 1.6Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
16-Bit, 2Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
2.5V Supply, ±5V Fully Differential Input, 104dB SNR, MSOP-16 and
4mm × 3mm DFN-16 Packages
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
18-Bit, Serial IOUT SoftSpan™ DAC
±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28 Package
16-Bit/14-Bit/12-Bit Single Serial VOUT DAC
12-Bit/10-Bit/8-Bit Single VOUT DACs
±1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output
SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
Precision Low Drift Low Noise Buffered
Reference
Precision Low Drift Low Noise Buffered
Reference
5V/2.5V/2.048V/1.2V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
Dual/Single Rail-to-Rail Output ADC Driver
Low Noise Single-Ended-to-Differential ADC
Driver
Low Power, Fully Differential Input/Output
Amplifier/Driver
215MHz GBW, 1.1nV/√Hz, 3.5mA Supply Current
Rail-to-Rail Inputs and Outputs, 240ns, 0.01% Settling Time
50 Linear Technology Corporation
5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Single 2.8V to 5.25V Supply, 1mA Supply Current, MSOP-8 and 3mm × 3mm
DFN-8 Packages
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2373-18
●
●
(408) 432-1900 FAX: (408) 434-0507
www.linear.com/LTC2373-18
237318f
LT 0115 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2015