CAT9552 16-Channel I2C-bus LED Driver with Programmable Blink Rate FEATURES DESCRIPTION 16 LED drivers with On/Off and programmable blink rate control The CAT9552 is a 16-channel, parallel input/output port expander optimized for LED On/Off and blinking control. Each individual LED may be turned ON, OFF, or set to blinking at one of two programmable rates. The CAT9552 is compatible with I2C and SMBus applications where it is desireable to limit the bus traffic or free-up the bus master’s internal timer. Three address pins allow up to eight CAT9552 devices to occupy the same bus. 2 selectable, programmable blink rates: – frequency: 0.172Hz to 44Hz – duty cycle: 0% to 99.6% 16 open drain outputs drive 25mA each I/Os can be used as GPIOs 400kHz I2C bus compatible The CAT9552 contains an internal oscillator and two PWM signals, which drive the LED outputs. The user may program the period and duty cycle for each individual PWM signal. After an initial set-up command to program the Blink Rate 1 and Blink Rate 2 (frequency and duty cycle), only one command from the bus master is required to turn each individual open drain output ON, OFF, or cycle at Blink Rate 1 or Blink Rate 2. Each open drain LED output can sink a maximum current of 25mA. The total continuous current sunk by all I/Os must not exceed 200mA per package. 2.3V to 5.5V operation 5V tolerant I/Os Active low reset input RoHS-compliant 24-Lead SOIC, TSSOP and 24-pad TQFN (4 x 4mm) packages APPLICATIONS Office machines Appliance control panels Alarm systems TYPICAL APPLICATION CIRCUIT Point of sale displays 5V 5V For Ordering Information details, see page 16. 3 x 10kΩ SDA SDA SCL SCL RESET RS0 RS1 RS11 VCC LED0 RESET LED1 CAT9552 I2C/SMBus Master LED11 A2 LED12 A1 GPIOs A0 VSS LED15 Notes: LED0 to LED11 are shown being used as LED drivers LED12 to LED15 are used as standard GPIOs © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 1 Doc. No. MD-9005 Rev B CAT9552 PIN CONFIGURATION 19 SCL 20 SDA 21 VCC 22 A0 23 A1 TQFN (HV6) 24 A2 SOIC (W), TSSOP (Y) 22 SCL LED0 1 18 RESET LED0 4 21 RESET LED1 2 17 LED15 LED1 5 20 LED15 LED2 6 19 LED14 LED2 3 16 LED14 LED3 7 19 LED13 LED4 8 17 LED12 LED3 4 15 LED13 LED5 9 16 LED11 LED4 5 14 LED12 LED6 10 15 LED10 LED7 11 14 LED9 LED5 6 13 LED11 VSS 12 13 LED8 LED10 12 3 LED9 11 SDA A2 LED8 10 VCC 23 VSS 9 24 2 LED7 8 1 A1 LED6 7 AO PIN DESCRIPTION SOIC / TSSOP 1 2 3 4-11 12 13-20 21 22 23 24 TQFN 22 23 24 1-8 9 10-17 18 19 20 21 PIN NAME AO A1 A2 LED0 - LED7 VSS LED8 - LED15 ¯¯¯¯¯¯ RESET SCL SDA VCC FUNCTION Address Input 0 Address Input 1 Address Input 2 LED Driver Output 0 to 7, I/O Port 0 to 7 Ground LED Driver Output 8 to 15, I/O Port 8 to 15 Reset Input Serial Clock Serial Data Power Supply — Pad Backside pad For enhanced heat dissipation. Electrically this pad must be at ground potential. BLOCK DIAGRAM A2 VCC A1 A0 POWER ON RESET RESET SCL INPUT FILTERS SDA INPUT REGISTER LED SELECT (LSx) REGISTER I2C BUS CONTROL LEDx PRESCALER 0 REGISTER PWM 0 REGISTER BLINK 0 PRESCALER 1 REGISTER PWM 1 REGISTER BLINK 1 OSCILLATOR VSS CAT9552 Note: Only one I/O is shown for clarity Doc. No. MD-9005 Rev B CONTROL LOGIC 2 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 ABSOLUTE MAXIMUM RATINGS (1) Parameters Ratings Units VCC with Respect to Ground -2.0 to +7.0 V Voltage on Any Pin with Respect to Ground -0.5 to +5.5 V DC Current on I/Os ±25 mA Supply Current 200 mA Package Power Dissipation Capability (TA = 25ºC) 1.0 W Junction Temperature +150 °C Storage Temperature -65 to +150 ºC 300 ºC -40 to +85 ºC Lead Soldering Temperature (10 seconds) Operating Ambient Temperature Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 3 Doc. No. MD-9005 Rev B CAT9552 D.C. OPERATING CHARACTERISTICS VCC = 2.3 to 5.5V, VSS = 0V; TA = -40ºC to +85ºC, unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit 2.3 — 5.5 V Supplies VCC Supply Voltage ICC Supply Current Operating mode; VCC = 5.5V; no load; fSCL = 100kHz — 250 550 µA Istb Standby Current Standby mode; VCC = 5.5V; no load; VI = VSS or VCC, fSCL = 0kHz — 2.1 5.0 µA Additional Standby Current Standby mode; VCC = 5.5V; every LED I/O = VIN = 4.3V, fSCL = 0kHz — — 2 mA Power-on Reset Voltage VCC = 3.3V, No load; VI = VCC or VSS — 1.5 2.2 V ΔIstb VPOR (1) ¯¯¯¯¯¯ SCL, SDA, RESET (2) Low Level Input Voltage -0.5 — 0.3 VCC V (2) High Level Input Voltage 0.7 VCC — 5.5 V VIL VIH IOL Low Level Output Current VOL = 0.4V 3 — — mA IIL Leakage Current VI = VCC = VSS -1 — +1 µA (3) Input Capacitance VI = VSS — — 6 pF (3) Output Capacitance VO = VSS — — 8 pF CI CO A0, A1, A2 VIL (2) Low Level Input Voltage -0.5 — 0.8 V (2) High Level Input Voltage 2.0 — 5.5 V Input Leakage Current -1 — 1 µA VIH IIL I/Os (2) Low Level Input Voltage -0.5 — 0.8 V (2) High Level Input Voltage 2.0 — 5.5 V VOL = 0.4V; VCC = 2.3V 9 — — VOL = 0.4V; VCC = 3.0V 12 — — VOL = 0.4V; VCC = 5.0V 15 — — VOL = 0.7V; VCC = 2.3V 15 — — VOL = 0.7V; VCC = 3.0V 20 — — VOL = 0.7V; VCC = 5.0V 25 — — VCC = 3.6V; VI = VSS or VCC -1 — 1 µA — — 8 pF VIL VIH (4) IOL IIL (3) CI/O Low Level Output Current Input Leakage Current Input/Output Capacitance mA Notes: (1) VDD must be lowered to 0.2V in order to reset the device. (2) VIL min and VIH max are reference values only and are not tested. (3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (4) The output current must be limited to a maximum 25mA per each I/O; the total current sunk by all I/O must be limited to 200mA (or 100mA for eight I/Os) Doc. No. MD-9005 Rev B 4 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 A.C. CHARACTERISTICS VCC = 2.3V to 5.5V, TA = -40ºC to +85ºC, unless otherwise specified (1) Symbol Standard I2C Parameter Min FSCL Clock Frequency tHD:STA Low Period of SCL Clock tHIGH High Period of SCL Clock Min 100 START Condition Hold Time tLOW Max Fast I2C Units Max 400 kHz 4 0.6 µs 4.7 1.3 µs 4 0.6 µs 4.7 0.6 µs Data In Hold Time 0 0 µs Data In Setup Time 250 100 ns tSU:STA START Condition Setup Time tHD:DAT tSU:DAT (2) SDA and SCL Rise Time 1000 300 ns (2) SDA and SCL Fall Time 300 300 ns tR tF tSU:STO tBUF STOP Condition Setup Time (2) Bus Free Time Between STOP and START tAA SCL Low to Data Out Valid tDH Data Out Hold Time (2) Ti Symbol 4 0.6 µs 4.7 1.3 µs 3.5 100 Noise Pulse Filtered at SCL and SDA Inputs Parameter 0.9 50 100 Min µs ns 100 ns Max Units 200 ns Port Timing tPV Output Data Valid tPS Input Data Setup Time 100 ns tPH Input Data Hold Time 1 µs tW(2) Reset Pulse Width 10 ns tREC Reset Recovery Time 0 ns 400 ns Reset tRESET (3) Time to Reset Notes: (1) Test conditions according to "AC Test Conditions" table. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (3) The full delay to reset the part will be the sum of tRESET and the RC time constant of the SDA line. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 5 Doc. No. MD-9005 Rev B CAT9552 AC TEST CONDITIONS Input Pulse Voltage 0.2VCC to 0.8VCC Input Rise and Fall Times ≤5ns Input Reference Voltage 0.3VCC, 0.7VCC Output Reference Voltage 0.5VCC Output Load Current source: IOL = 3mA; 400pF for fSCL(max) = 400kHz tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 1. 2-Wire Serial Interface Timing PIN DESCRIPTION SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. LED0 to LED15: LED Driver Outputs / General Purpose I/Os These pins are open drain outputs used to directly drive LEDs. Any of these pins can be programmed to drive the LED ON, OFF, or to Blink Rate1 or Blink Rate2. A current limiting resistor should be placed in series with each LED to control the maximum LED current. When not used for controlling the LEDs, these pins may be used as general purpose parallel input/output. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pullup resistor must be connected from SDA line to VCC. ¯¯¯¯¯¯: External Reset Input RESET Active low Reset input is used to initialize the 2 CAT9552 internal registers and the I C state machine. The internal registers are held in their default state while Reset input is active. An external pull-up resistor of maximum 25kΩ is required when this pin is not actively driven. Doc. No. MD-9005 Rev B 6 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 FUNCTIONAL DESCRIPTION The CAT9552 is a 16-channel I/O bus expander that provides a pair of programmable LED blinkers, controlled through an I2C compatible serial interface. SDA when SCL is HIGH. The CAT9552 monitors the SDA and SCL lines and will not respond until this condition is met. CAT9552 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9552 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing After the bus Master sends a START condition, a slave address byte is required to enable the CAT9552 for a read or write operation. The four most significant bits of the slave address are fixed as binary 1100 (Figure 3). The CAT9552 uses the next three bits as address bits. 2 I C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 2). The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. Following the START condition and the slave address byte, the CAT9552 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9552 then performs a read or a write operation depending on the state of the R/W bit. START and STOP Conditions The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA SCL START CONDITION STOP CONDITION Figure 2. Start/Stop Timing SLAVE ADDRESS 1 1 0 FIXED 0 A2 A1 A0 R/W PROGRAMMABLE HARDWARE SELECTABLE Figure 3. CAT9552 Slave Address © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 7 Doc. No. MD-9005 Rev B CAT9552 The Control Register acts as a pointer to determine which register will be written or read. The four least significant bits, B0, B1, B2, B3, are used to select which internal register is accessed, according to the Table 1. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 4). If the auto increment flag is set (AI = 1), the four least significant bits of the Control Register are automatically incremented after a read or write operation. This allows the user to access the CAT9552 internal registers sequentially. The content of these bits will rollover to “0000” after the last register is accessed. The CAT9552 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. Table 1. Internal Registers Selection When the CAT9552 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9552 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT9552 to the standby power mode and place the device in a known state. Registers and Bus Transactions After the successful acknowledgement of the slave address, the bus master will send a command byte to the CAT9552 which will be stored in the Control Register. The format of the Control Register is shown in Figure 5. SCL FROM MASTER B3 B2 B1 B0 Register Name Type 0 0 0 0 INPUT0 READ Register Function Input Register 0 0 0 0 1 INPUT1 READ Input Register 1 0 0 1 0 PSC0 READ/ WRITE Frequency Prescaler 0 0 0 1 1 PWM0 READ/ WRITE PWM Register 0 0 1 0 0 PSC1 READ/ WRITE Frequency Prescaler 1 0 1 0 1 PWM1 READ/ WRITE PWM Register 1 0 1 1 0 LS0 READ/ WRITE LED 0-3 Selector 0 1 1 1 LS1 READ/ WRITE LED 4-7 Selector 1 0 0 0 LS2 READ/ WRITE LED 8-11 Selector 1 0 0 1 LS3 READ/ WRITE LED 12-15 Selector 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 4. Acknowledge Timing 0 0 0 AI B3 B2 B1 B0 REGISTER ADDRESS RESET STATE: 00h AUTO-INCREMENT FLAG Figure 5. Control Register Doc. No. MD-9005 Rev B 8 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 Table 4. PWM Register 0 and PWM Register 1 Input Register 0 and Input Register 1 reflect the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output. These registers are read only ports. Writes to the input registers will be acknowledged but will have no effect. PWM0 bit 7 6 5 4 3 2 1 0 default 1 0 0 0 0 0 0 0 PWM1 Table 2. Input Register 0 and Input Register 1 bit INPUT0 default LED LED LED LED LED LED LED 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 LED 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 default X X X X X X X X LED LED LED LED LED LED LED LED 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 default X X X X X X X X Every LED driver output can be programmed to one of four states, LED OFF, LED ON, LED blinks at BLINK0 rate and LED blinks at BLINK1 rate using the LED Selector Registers (Table 5). INPUT1 Table 5. LED Selector Registers LS0 LED 3 The Frequency Prescaler 0 and Frequency Prescaler 1 registers (PSC0, PSC1) are used to program the period of the pulse width modulated signals BLINK0 and BLINK1 respectively: LED 2 LED 1 LED 0 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 LS1 LED 7 T_BLINK0 = (PSC0 + 1) / 44; T_BLINK1 = (PSC1 + 1) / 44 LED 6 LED 5 LED 4 bit 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 LS2 Table 3. Frequency Prescaler 0 and Frequency Prescaler 1 Registers LED 11 PSC0 bit 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 default 1 1 1 1 1 1 1 1 LED 9 LED 8 7 6 5 4 3 2 1 0 default 0 0 0 0 0 0 0 0 LS3 LED 15 PSC1 bit LED 10 bit bit 7 6 default 0 0 LED 14 LED 13 LED 12 5 4 3 2 1 0 0 0 0 0 0 0 The LED output (LED0 to LED15) is set by the 2 bit value from the corresponding LSx Register (x = 0 to 3): The PWM Register 0 and PWM Register 1 (PWM0, PWM1) are used to program the duty cycle of BLINK0 and BLINK1 respectively: 00 = LED Output set LOW (LED On) 01 = LED Output set Hi-Z (LED Off – Default) 10 = LED Output blinks at BLINK0 Rate 11 = LED Output blinks at BLINK1 Rate Duty Cycle_BLINK0 = (256 - PWM0) / 256; Duty Cycle_BLINK1 = (256 - PWM1) / 256 After writing to the PWM0/1 register an 8-bit internal counter starts to count from 0 to 255. The outputs are low (LED on) when the counter value is less than the value programmed into PWM register. The LED is off when the counter value is higher than the value written into PWM register. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 9 Doc. No. MD-9005 Rev B CAT9552 Write Operations Data is transmitted to the CAT9552 registers using the write sequence shown in Figure 6. LED Pins Used as General Purpose I/O Any LED pins not used to drive LEDs can be used as general purpose input/output, GPIO. If the AI bit from the command byte is set to “1”, the CAT9552 internal registers can be written sequentially. After sending data to one register, the next data byte will be sent to the next register sequentially addressed. When used as input, the user should program the corresponding LED pin to Hi-Z (“01” for the LSx register bits). The pin state can be read via the Input Register according to the sequence shown in Figure 8. Read Operations The CAT9552 registers are read according to the timing diagrams shown in Figure 7 and Figure 8. Data from the register, defined by the command byte, will be sent serially on the SDA line. For use as a logic output, an external pull-up resistor should be connected to the pin. The value of the pullup resistor is calculated according to the DC operating characteristics. To set the output high, the user has to program the output Hi-Z writing “01” into the corresponding LED Selector (LSx) register bits. The output pin is set low when the output is programmed low through the LSx register bits (“00” in LSx register bits). After the first byte is read, additional data bytes may be read when the auto-increment flag, AI, is set. The additional data byte will reflect the data read from the next register sequentially addressed by the (B3, B2, B1, B0) bits of the command byte. GPIO can also be used as PWM outputs by setting the LED Selector (LSx) register to “10” or “11” to output either the BLINK0 or BLINK1 waveform. When reading Input Port Registers (Figure 8), data is clocked into the register on the failing edge of the acknowledge clock pulse. The transfer is stopped when the master will not acknowledge the data byte received and issue the STOP condition. 1 SCL 3 2 4 5 6 7 8 9 Command Byte Slave Address SDA S 1 1 0 0 A2 A1 A0 Start Condition 0 R/W A 0 0 0 AI Data To Register 2 Data To Register 1 B3 B2 B1 B0 Acknowledge From Slave DATA 1 A 1.0 A Acknowledge From Slave A Acknowledge From Slave WRITE TO REGISTER DATA OUT FROM PORT tpv Figure 6. Write to Register Timing Diagram Slave Address S 1 1 0 0 A2 A1 A0 Acknowledge From Slave 0 R/W A Acknowledge From Slave COMMAND BYTE A S Slave Address 1 1 0 0 A2 A1 A0 Acknowledge From Slave 1 Data From Register DATA A MSB R/W At This Moment Master-Transmitter Becomes Master-receiver and Slave-Receiver Becomes Slave-Transmitter Acknowledge From Master LSB A First Byte Auto-increment Register Address If Al = 1 Data From Register MSB DATA No Acknowledge From Master LSB NA P Note: Transfer can be stopped at any time by a STOP condition. Last Byte Figure 7. Read from Register Timing Diagram Doc. No. MD-9005 Rev B 10 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 External Reset Operation The CAT9552 registers and the I2C state machine are initialized to their default state when the RESET input is held low for a minimum of tW. CAT9552’s registers will be held in their default state until RESET returns to a logic HIGH state. The external Reset timing is shown in Figure 9. Slave Address SDA S 1 1 0 0 A2 Start Condition Power-On Reset Operation The CAT9552 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device is in a reset state for VCC less than the internal POR threshold level (VPOR). When VCC exceeds the VPOR level, the reset state is released and the CAT9552 internal state machine and registers are initialized to their default state. Thereafter VCC must be taken below 0.2V to reset the device. Data From Port A1 A0 DATA 1 A R/W Data From Port DATA 4 A Acknowledge From Slave Acknowledge From Master NA No Acknowledge From Master P Stop Condition READ FROM PORT DATA INTO PORT DATA 1 DATA 2 DATA 3 tph DATA 4 tps Figure 8. Read Input Port Register Timing Diagram START ACK OR READ CYCLE SCL SDA 30% tRESET RESET 50% 50% tREC 50% tW tRESET LEDx 50% LED OFF Figure 9. RESET ¯¯¯¯¯¯ Timing Diagram © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 11 Doc. No. MD-9005 Rev B CAT9552 APPLICATION INFORMATION Programming Example The following programming sequence is an example how to set: – LED0 to LED3: ON – LED4 to LED7: Blink at 1Hz with a 50% duty cycle (Blink 0) – LED8 to LED11: Blink at 4Hz with a 20% duty cycle (Blink 1) – LED12 to LED15: OFF 1 2 3 4 5 6 7 8 9 10 11 12 Command Description START Send Slave address, A0-A2 = low Command Byte: AI=”1”; PSC0 Addr Set Blink 0 at 1Hz, T_Blink1 = (PSC0+1)/44 = 1 Write PSC0 = 43 Set PWM0 duty cycle to 50% (256-PWM0) / 256 = 0.5 Write PWM0=128 Set Blink 1 at 4Hz, T_Blink1 = (PSC1+1)/44 = 0.25 Write PSC1 = 10 Set PWM1 duty cycle to 25% (256-PWM1) / 256 = 0.25 Write PWM1=192 Write LS0: LED0 to LED3 = ON Write LS1: LED4 to LED7 at Blink0 Write LS2: LED8 to LED11 at Blink1 Write LS3: LED12 to LED15 = OFF STOP I2C Data C0h 12h 2Bh 80h 0Ah C0h 00h AAh FFh 55h 5V 5V VCC 10kΩ (x 3) VCC SDA SDA SCL SCL LED0 LED1 LED2 LED3 LED4 RESET LED5 RESET LED6 GND I2C/SMBus MASTER CAT9552 LED7 LED8 LED9 A2 LED10 A1 LED11 A0 LED12 VSS LED13 GPIOs LED14 LED15 Note: LED0 to LED11 are used as LED drivers and LED12 to LED15 are used as regular GPIOs. Figure 10. Typical Application Doc. No. MD-9005 Rev B 12 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 PACKAGE OUTLINE DRAWINGS SOIC 24-Lead (W) (1)(2) SYMBOL E1 E MIN e PIN#1 IDENTIFICATION MAX A 2.35 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 c 0.20 0.33 D 15.20 15.40 E 10.11 10.51 E1 7.34 e b NOM 7.60 1.27 BSC h 0.25 0.75 L 0.40 1.27 θ 0° 8° θ1 5° 15° TOP VIEW h D A2 A A1 SIDE VIEW h θ1 θ θ1 L c END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 13 Doc. No. MD-9005 Rev B CAT9552 TSSOP 24-Lead 4.4mm (Y) (1)(2) b SYMBOL MIN NOM A A1 E1 E MAX 1.20 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 D 7.70 0.20 7.80 7.90 E 6.25 6.40 6.55 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.70 8° e TOP VIEW D c A2 A θ1 L1 A1 L SIDE VIEW END VIEW For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. Doc. No. MD-9005 Rev B 14 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 TQFN 24-Lead 4 x 4mm (HV6) (1)(2) A D DETAIL A E E2 PIN#1 ID PIN#1 INDEX AREA D2 A1 TOP VIEW SIDE VIEW BOTTOM VIEW b SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 b DETAIL A 0.18 0.25 D 3.90 4.00 4.10 D2 2.40 – 2.90 E 3.90 4.00 4.10 E2 2.40 – 2.90 L L 0.20 REF e e 0.30 A 0.50 BSC 0.30 0.40 0.50 FRONT VIEW A3 For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC standard MO-220. © 2008 SCILLC. All rights reserved Characteristics subject to change without notice 15 Doc. No. MD-9005 Rev B CAT9552 EXAMPLE OF ORDERING INFORMATION (1) Prefix Device # Suffix CAT 9552 HV6 Company ID Product Number I Package W: SOIC, JEDEC Y: TSSOP HV6: TQFN G T2 Lead Finish Blank: Matte-Tin G: NiPdAu Tape & Reel T: Tape & Reel 1: 1,000/Reel SOIC only 2: 2,000/Reel – 9552 Temperature Range I = Industrial (-40ºC to 85ºC) ORDERING PART NUMBER Part Number Package Lead Finish CAT9552WI SOIC Matte-Tin CAT9552WI-T1 SOIC Matte-Tin CAT9552YI TSSOP Matte-Tin CAT9552YI-T2 TSSOP Matte-Tin CAT9552HV6I-G TQFN NiPdAu CAT9552HV6I-GT2 TQFN NiPdAu For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard plated finish is Matte-Tin for SOIC and TSSOP packages. The standard plated finish is NiPdAu for TQFN package. (3) The device used in the above example is a CAT9552HV6I-GT2 (TQFN, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). (4) For additional temperature options, please contact your nearest ON Semiconductor Sales office. Doc. No. MD-9005 Rev B 16 © 2008 SCILLC. All rights reserved Characteristics subject to change without notice CAT9552 REVISION HISTORY Date Revisio Description 23-Jun-08 A Initial Issue 03-Dec-08 B Update A.C. Characteristics table to include Standard I2C and Fast I2C. Change logo and fine print to ON Semiconductor ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] © 2008 SCILLC. All rights reserved Characteristics subject to change without notice N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 17 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-9005, Rev. B