MP7612 Octal 12-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address µP Control Logic ...the analog plus company TM FEATURES APPLICATIONS • Eight Independent 12-Bit DACs with Output Amplifiers • Low Power 320 mW (typ.) • Serial Digital Data and Address Port (3-Wire Standard) • 12-Bit Resolution, 11 Bit Accuracy • Extremely Well Matched DACs • Extremely Low Analog Ground Current (<60µA/Channel) • +10 V Output Swing with +11.4 V Supplies • Zero Volt Output Preset (Data = 10 .. 00) • Rugged Construction – Latch-Up Free • Parallel Version: MP7613 • • • • • • • April 1996-4 Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS GENERAL DESCRIPTION sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30µs (typ.). The MP7612 provides eight independent 12-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a 3-wire standard serial digital address and data port. µ-processor logic interface to reduce pin count, package size, Typical DAC matching for B grade versions is 0.7 LSB across all codes. Accuracy of +0.75 LSB for DNL and +1 LSB for INL is also achieved for B grades. The output amplifier is capable of The MP7612 is equipped with a serial data (3-wire standard) and board space. Built using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR’s patented thin-film resistor process which exhibits excellent long term stability and reliability. SIMPLIFIED BLOCK DIAGRAM VRP VRP – + D VRN Q 12 LAT0 XR XE RST + – VO7 VRP 8 8 4 to 16 Decoder LAT D Q EN SDI VO0 VRN LD Not Used + – XE0 XE0 - XE7 12 DAC0 4 D Q LAT7 XR XE 12 DAC7 VRN XE7 LD D0 to D11 A0 to A3 16-Bit Shift Register EN CLK D LAT Q Tri-State Buffer VRP VEE VEE VCC VCC AGND SDO LD AGND VREF DGND DVDD Rev. 3.00 1996 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7010 MP7612 ORDERING INFORMATION Package Type Temperature Range Part No. Res. (Bits) INL (LSB) DNL (LSB) FSE (LSB) PLCC –40 to +85°C MP7612BP 12 –40 to +85°C 1 0.75 6 PLCC MP7612AP 12 1 8 SOIC –40 to +85°C 2 MP7612BS 12 –40 to +85°C 1 0.75 6 SOIC MP7612AS 12 2 1 8 PIN CONFIGURATIONS AGND VO0 VO1 VO2 VO3 VEE VCC VREF VCC VEE VO4 VO5 VO6 VO7 1 See the following page for pin descriptions 44 Pin PLCC 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DGND N/C N/C DVDD DGND N/C SDO SDI CLK LD N/C RST N/C AGND 28 Pin SOIC (Jedec, 0.346”) Rev. 3.00 2 MP7612 PIN DESCRIPTION SOIC Pin # PLCC Pin # Symbol 1 2 AGND 2 3 VO0 DAC 0 Output 3 4 VO1 DAC 1 Output 4 5 VO2 DAC 2 Output 5 6 VO3 DAC 3 Output 6 7 VEE Analog Negative Power Supply (–12 V) Description Analog Ground 7 9 VCC Analog Positive Power Supply (+12 V) 8 12 VREF Voltage Reference Input (+5 V) 9 13 VCC Analog Positive Power Supply (+12 V) 10 15 VEE Analog Negative Power Supply (–12 V) 11 18 VO4 DAC 4 Output 12 19 VO5 DAC 5 Output 13 20 VO6 DAC 6 Output 14 21 VO7 DAC 7 Output 15 24 AGND Analog Ground N/C No Connection RST Reset all DACs to 0 V Output N/C No Connection Load Signal; Load Data to Selected DAC 16 17 26 18 19 29 LD 20 31 CLK Serial Data Clock 21 32 SDI Serial Data Input 22 34 SDO Shift Register Serial Output N/C No Connection 23 24 37 DGND Digital Ground 25 40 DVDD Digital Positive Power Supply (+5 V) 26 N/C No Connection 27 1, 8, 10, 11, 14, 16, 17, 22, 23, 25, 27, 28, 30, 33, 35, 36, 38, 39, 41, 42, 43 N/C No Connection 28 44 DGND Digital Ground Rev. 3.00 3 MP7612 ELECTRICAL CHARACTERISTICS VCC = +12 V, VEE = –12 V, VREF = 5 V, DVDD = 5.0 V, T = 25°C, Output Load = 5kΩ (unless otherwise noted) Parameter Symbol Min N 12 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B INL Differential Non-Linearity A B DNL Positive Full Scale Error A B +FSE Negative Full Scale Error A B –FSE Bipolar Zero Offset A B ZOFS INL Matching A B All Channels Maximum Error with DAC 0 adjusted to minimum error A B Bipolar Zero Matching A B Full Scale Error Matching A B Bits LSB 2 1 2 1 1 0.75 1 0.75 6 4 8 6 8 6 6 4 8 6 8 6 4 3 4 3 2 1.5 2 1.5 End Point Linearity Spec LSB LSB LSB LSB ∆INL LSB ME LSB 4 2 4 2 4 3 4 3 4 3 4 3 50 50 ∆ZOFS LSB FSE LSB DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk1, 6 Digital Feedthrough1, 6 Power Supply Rejection Ratio tsd 30 CT Q PSRR 0.04 –70 5 µsec ZS to FS (20 V Step) LSB dB ppm/% DC CLK and Data to VOUTi ∆VEE & ∆VCC = +5%, ppm of FS Ω See Application Hints for driving the reference input REFERENCE INPUTS Impedance of VREF REF 350 VREF Voltage1, 2 VREF 3.5 700 1.05k 6 Rev. 3.00 4 350 1.05k V MP7612 ELECTRICAL CHARACTERISTICS (CONT’D) Parameter Symbol Min VIH VIL IL CL 2.4 25°C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 V V µA pF 0.8 +10 8 ANALOG OUTPUTS Output Swing Output Drive Current Output Impedance Output Short Circuit Current –VEE +1.4 –5 VCC –1.4 RO ISC 1 25 30 40 55 V mA Ω mA mA mA mA VOH VOL 4.5 0.5 V V VCC VEE DVDD ICC IEE IDD PDISS VREF+1.5 12 –12.75 –12 4.5 5 8 15 IAGND ±60 5 +FS to AGND +FS to VEE –FS to AGND –FS to VCC DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation 320 12.75 –5 5.5 10 20 2 420 VREF+1.5 12.75 –12.75 –5 4.5 5.5 10 20 2 450 V V V mA mA mA mW Bipolar zero Bipolar zero Bipolar zero Bipolar zero µA See Application Notes ANALOG GROUND CURRENT Per Channel1 DIGITAL TIMING SPECIFICATIONS1,4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Preset Pulse Width Clock Edge to Load Time LD Falling Edge to SDO Tri-state Enable LD Rising Edge to SDO Tri-state Disable LD Rising Edge to CLK Enable LD Set-up Time with Respect to CLK VIL = 0, VIH = 5.0, CL = 20 pF tCH, tCL tDS tDH tPD tLD tPR tCKLD1 tCKLD2 tHZ1 35 15 15 35 50 140 0 50 tHZ2 50 ns tLDCK tLDSU 50 30 ns ns 40 ns ns ns ns ns ns ns ns Rev. 3.00 5 Note: tLD and tCKLD2 cannot both be min. since tCKLD1=tCKLD2+tLD MP7612 ELECTRICAL CHARACTERISTICS (CONT’D) NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < 2VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V Analog Inputs & Outputs . . . . . . . Indefinite Shorts to VCC, VEE, DVDD, AGND, DGND (provided that power dissipation of the package spec is not exceeded) VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –16.5 V Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . –40°C to +85°C DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V Maximum Junction Temperature . . . –65°C to 150°C VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for 0.5 V only) Lead Temperature (Soldering, 10 sec) . . . . . +300°C Package Power Dissipation Rating @ 75°C SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 1150mW Derates above 75°C . . . . . . . . . . . . . . . . . 15mW/°C Digital Input & Output Voltage to DGND –0.5 to DVDD +0.5V NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. APPLICATION NOTES Refer to Section 8 in the 1995 Data Acquisition products Databook for Applications Information NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to 300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than 1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths. Rev. 3.00 6 MP7612 MSB SDI 1 A3 (Data In) 0 CLK LD A2 A1 A0 D11 D10 D9 D8 D7 D6 D0 1 0 1 0 SDO 1 DAC Register Loaded A3 (1) Previous Data 0 VOUT Notes: (1) Because A3 is available immediately after 16th clock edge of DATA Shift-in, only 15 clock cycles are needed to complete the readback. Figure 1. Serial Data Timing and Loading SDI tDS 1 0 tDH SDO tHZ1 tHZ2 HIGH Z 1 0 CLK tCH 1 0 tCL LD tLDCK tLDSU tPD tCKLD2 tCKLD1 1 0 tLD +FS VOUT –FS tSD +1/2 LSB Band Notes: (1) CLK should be high during the falling edge of LD to insure proper function of the shift register. Figure 2. Serial Data Input Timing (RST = “1”) RST 1 0 tPR VOUT VOUT = 0 V Note: Reset settling time is <tSD +1/2 LSB Error Band Figure 3. Reset Operation Rev. 3.00 7 MP7612 The MP7612 is equipped with a serial data (3-wire standard) The LD signal going low also disables the serial data (SDI), output (SDO 3-stated) and the CLK input. This design tremendously reduces digital noise and glitch transients into the DACs due to free running CLK and SDI. Note also that the preset signal (RST) resets all analog outputs to 0 volt regardless of digital inputs. µ-processor logic interface to reduce pin count, package size, and board wire (space). If the LD signal is high, the CLK signal loads the digital input bits (SDI) into the shift register (4 bits address A3 to A0 plus 12 bits data DB11 to DB0 for the MP7612). The LD signal going low loads the data into the selected DAC. Function A3 A2 A1 A0 Shift Data In and Out X X Stop Shifting Data In and Out X X X X 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 No Operation 1→0 1→0 1→0 1→0 1→0 1→0 1→0 1→0 No Operation 1 1 1 1 1 1 0 1 X X X X Load DACs DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 Reset all DACs to 0 V X X LD CLK RST SDI SDO 0→1 1 Data Input Valid Data Output Valid X 1 X Hi-Z 1 1 1 1 1 1 1 1 X X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z No Operation No Operation X X X X X X X X X X X X X 1 1 X X Hi-Z Hi-Z X X 0 X X 1 Repeat Table 1. Digital Function Truth Table Serial In/Serial Out Note: For timing information see Electrical Characteristics Rev. 3.00 8 MP7612 Hex Code Binary Code Output Voltage = 2 • Vr (–1 + 2•D ) 4096 (Vr = +5 V) 000 000000000000 10 • (–1 + 0) = –10 7FF 011111111111 800 100000000000 801 100000000001 FFF 111111111111 10 • (–1 + 4094 ) = –4.88 mV 4096 10 • (–1 + 4096 ) = 0 4096 10 • (–1 + 4098 ) = 4.88 mV 4096 10 • (–1 + 8190 ) = 9.99512 4096 Table 2. MP7612 Ideal DAC Output vs. Input Code Note: See Electrical Characteristics for real system accuracy SERIAL INTERFACE DIAGRAMS Rev. 3.00 9 MP7612 VRI1 VOI1 1 VRI2 1 8 VOI2 8 IC(1) µPC SDI LD VRIn 1 VOIn 8 IC(2) SDO SDI LD IC(n) SDO SDI LD SDO Data LD CLK Figure 4. Simplified Diagram VRI1 VOI1 1 VRI2 8 VOI2 1 8 IC(1) µPC SDI LD VRIm VOIm 1 8 IC(2) SDO SDI LD SDO IC(n) SDI LD SDO Data Out Data n CS or LD CLK #1 #2 #n Figure 5. Simplified Diagram VRI1 VOI1 VRI2 VOI2 IC(1) IC(2) VRIn VOIn Address µPC n Address Decoder 1 SDO 2 2n SDI LD SDO1 SDI LD SDO2 WR (SDI) Data In CLK Figure 6. Simplified Diagram Rev. 3.00 10 IC(n) SDI LD SDOm MP7612 16 16 Address Bus A0 to A15 3 E1 A0 to A2 02 E3 R/W E2 74LS138 Address Decoder MC6800 8 Data Bus 8 DBO to DB7 LD DB7 CLK SDI RST From SYSTEM RESET NOTES 1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each WRITE presents the next bit. 2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to memory location 2000, R/W, and 02. A WRITE to address 4000 transfers data from input shift register to DAC register. Figure 7. MC6800 Interface Address Bus 8 8 8085 ALE 8212 3 +5 E1 A0 to A2 E3 74LS138 Address Decoder E2 WR 8 Data Bus SOD LD CLK SDI RST From SYSTEM RESET NOTES: 1. Clock generated by WR and decoding address 8000. 2. Data is clocked in the DAC shift register by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction to address 4000. 3. Serial data must be present in the right justified format in registers H & L of the microprocessor. Figure 8. 8085 Interface Rev. 3.00 11 MP7612 PERFORMANCE CHARACTERISTICS 11 V 0V –11 V VOUT 2.5mV 0V –2.5mV VOUT Settling 50µs/Division Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output. Graph 2. Linearity with VREF = 5 V, All DACs, All Codes Rev. 3.00 12 MP7612 Graph 3. DAC 0 INL vs. VREF Graph 4. DAC 0 DNL vs. VREF Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = 10 Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = 9 Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = 8 Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = 7 Rev. 3.00 13 MP7612 VOUT MP7610 Family 50 5k VO 500pF I CL 2mA CL = 500pF, 5nF, 50nF, 500nF Figure 9. Circuit for Determining Typical Analog Output Pulse Response 2.0mA I 0.0 400mV VO –400mV 200mV CL = 500pF CL = 5nF CL = 50nF CL = 500nF VOUT –200mV 0s 1.0µs 2.0µs 3.0µs 4.0µs 5.0µs Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See Figure 9. above) Rev. 3.00 14 6.0µs MP7612 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) C D D1 Seating Plane 45° x H1 45° x H2 A2 2 1 44 B1 D D1 B D 2 D3 e R D3 A1 A INCHES SYMBOL MIN MILLIMETERS MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 A2 0.020 –––. 0.51 ––– B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column Rev. 3.00 15 MP7612 28 LEAD SMALL OUTLINE (350 MIL JEDEC SOIC) D 28 15 E H 1 14 C A Seating Plane α B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.706 0.718 17.93 18.24 E 0.340 0.350 8.64 8.89 e 0.050 BSC MAX 1.27 BSC H 0.460 0.485 11.68 12.32 L 0.016 0.050 0.40 1.27 α 0° 8° 0° 8° Note: The control dimension is the millimeter column Rev. 3.00 16 MP7612 Notes Rev. 3.00 17 MP7612 Notes Rev. 3.00 18 MP7612 Notes Rev. 3.00 19 MP7612 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1996 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.00 20