HC55171 Data Sheet July 1998 File Number 4323.4 5 REN Ringing SLIC for ISDN Modem/TA and WLL Features The HC55171 is backward compatible to the HC5517 with the added capability of driving 5 REN loads. The HC55171 is ideal for any modem or remote networking access application that requires plain old telephone service POTS, capability. The linear amplifier design allows a choice of Sinusoidal, Square wave or Trapezoidal ringing. The voltage feed architecture eliminates the need for a high current gain node achieving improved system noise immunity, an advantage in highly integrated systems. • Trapezoid, Square and Sinusoid Ringing Capability • 5 REN Thru SLIC Ringing Capability to 75VPEAK • Bellcore Compliant Ringing Voltage Levels • Lowest Component Count Trapezoidal Solution • Single Additional +5V Supply • Pin For Pin Compatible With HC5517 • DI Provides Latch-Up Immunity Applications The device is manufactured in a high voltage Dielectric Isolation (DI) process with an operating voltage range from -16V, for off-hook operation and -80V for ring signal injection. The DI process provides substrate latch up immunity, resulting in a robust system design. • ISDN Internal/External Modems • ISDN Terminal Adapters/Routers • Wireless Local Loop Subscriber Terminals • Cable Telephony Set-Top Boxes Ordering Information PART NUMBER • Digital Added Main Line TEMP. RANGE (oC) PKG. NO. PACKAGE HC55171IM -40 to 85 28 Ld PLCC N28.45 HC55171CM 0 to 75 28 Ld PLCC N28.45 HC55171IB -40 to 85 28 Ld SOIC M28.3 HC55171CB 0 to 75 28 Ld SOIC M28.3 • Integrated LAN/PBX • Related Literature - AN9606, Operation of the HC5517/171 Evaluation Board - AN9607, Impedance Matching Design Equations - AN9628, AC Voltage Gain - AN9608, Implementing Pulse Metering - AN9636, Implementing an Analog Port for ISDN Using the HC5517 - AN549, The HC-5502X/4X Telephone Subscriber Line Interface Circuits (SLIC) Block Diagram TIP FEED TIP SENSE RING FEED VRX 4-WIRE INTERFACE 2-WIRE INTERFACE LOOP CURRENT DETECTOR RING SENSE 1 VTX VRING - IN 1 + FAULT DETECTOR RING SENSE 2 VREF OUT 1 CURRENT LIMIT RTI VBAT SHD ALM ILMT RING TRIP DETECTOR VCC BIAS RTD AGND IIL LOGIC INTERFACE BGND F1 62 F0 RS TST RELAY DRIVER RDO RDI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HC55171 Absolute Maximum Ratings TA = 25oC Thermal Information Maximum Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V VCC - VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V Operating Conditions Temperature Range HC55171IM, HC55171IB . . . . . . . . . . . . . . . . . . . . -40oC to 85oC HC55171CM, HC55171CB . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V Positive Power Supply, VCC . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Negative Power Supply, VBAT . . . . . . . . . . . . . . . . . . . .-16V to -80V Thermal Resistance (Typical, Note 1) θJA (oC/W) PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC, PLCC - Lead Tips Only) Die Characteristics Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 x 144 Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RINGING TRANSMISSION PARAMETERS VRING Input Impedance (Note 2) - 5.4 - kΩ 4-Wire to 2-Wire Gain VRING to VT-R (Note 2) - 40 - V/V RX Input Impedance 300Hz to 3.4kHz (Note 2) - 108 - kΩ OUT1 Positive Output Voltage Swing RL = 10kΩ (Note 2) +2.5 - - V OUT1 Negative Output Voltage Swing RL = 10kΩ (Note 2) -4.5 - - V 4-Wire Input Overload Level 300Hz to 3.4kHz RL = 1200Ω, 600Ω Reference (Note 2) - +3.1 - VPEAK 2-Wire Return Loss Matched for 600Ω, f = 300Hz (Note 2) 37 - - dB Matched for 600Ω, f = 1000Hz (Note 2) 40 - - dB Matched for 600Ω, f = 3400Hz (Note 2) 30 - - dB 2-Wire Longitudinal to Metallic Balance Off Hook Per ANSI/IEEE STD 455-1976 300Hz to 3400Hz (Note 2) 58 63 - dB 4-Wire Longitudinal Balance Off Hook 300Hz to 3400Hz (Note 2) - 55 - dB Longitudinal Current Capability ILINE = 40mA, TA = 25oC (Note 2) - 40 - mARMS Insertion Loss, 2W-4W 0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3 - ±0.05 ±0.2 dB Insertion Loss, 4W-2W 0dBmO,1kHz - ±0.05 ±0.2 dB Insertion Loss, 4W-4W 0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3 - - ±0.25 dB Frequency Response 300Hz to 3400Hz Referenced to Absolute Level at 1kHz, 0dBm Referenced 600Ω - ±0.02 ±0.06 dB AC TRANSMISSION PARAMETERS 63 HC55171 Electrical Specifications Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS +3 to 0dBm, Referenced to -10dBm (Note 2) - - ±0.10 dB 0 to -40dBm, Referenced to -10dBm (Note 2) - - ±0.12 dB -40 to -55dBm, Referenced to -10dBm (Note 2) - - ±0.30 dB Absolute Delay, 2W-4W 300Hz to 3400Hz (Note 2) - - 1.0 µs Absolute Delay, 4W-2W 300Hz to 3400Hz (Note 2) - - 1.0 µs Absolute Delay, 4W-4W 300Hz to 3400Hz (Note 2) - 0.95 - µs Transhybrid Loss VIN = 1VP-P at 1kH (Note 2) 36 40 - dB Total Harmonic Distortion 2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire Reference Level 0dBm at 600Ω 300Hz to 3400Hz (Note 2) - - -50 dB Idle Channel Noise 2-Wire and 4-Wire C-Message (Note 2) - 3 - dBrnC Psophometric (Note 2) - -87 - dBmp 30 35 - dB PSRR, VCC to 4W 45 47 - dB PSRR, VBAT to 2W 23 28 - dB PSRR, VBAT to 4W 33 38 - dB 33 35 - dB PSRR, VCC to 4W 44 46 - dB PSRR, VBAT to 2W 40 50 - dB PSRR, VBAT to 4W 50 60 - dB 30 34 - dB PSRR, VCC to 4W 35 40 - dB PSRR, VBAT to 2W 30 40 - dB PSRR, VBAT to 4W 40 50 - dB 20 - 60 mA -10 - +10 % Level Linearity PSRR, VCC to 2W 30Hz to 200Hz, RL = 600Ω (Note 2) PSRR, VCC to 2W 200Hz to 3.4kHz, RL = 600Ω (Note 2) PSRR, VCC to 2W 3.4kHz to 16kHz, RL = 600Ω (Note 2) DC PARAMETERS Loop Current Programming Range (Note 3) Loop Current Programming Accuracy Loop Current During Power Denial RL = 200Ω, VBAT = -48V - ±4 - mA Fault Current, Tip to Ground (Note 2) - 90 - mA - 100 - mA - 130 - mA 9 12 15 mA -0.28 -0.24 -0.22 V Fault Current, Ring to Ground Fault Current, Tip and Ring to Ground (Note 2) Switch Hook Detection Threshold Ring Trip Comparator Voltage Threshold Thermal ALARM Output Safe Operating Die Temperature Exceeded (Note 2) - 160 - oC Dial Pulse Distortion (Note 2) - 0.1 0.5 ms 64 HC55171 Electrical Specifications Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600Ω 2-Wire terminating impedance. (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 0.2 0.5 V - ±10 ±100 µA Logic Low Input Voltage 0 - 0.8 V Logic High Input Voltage 2.0 - 5.5 V UNCOMMITTED RELAY DRIVER On Voltage, VOL IOL (RDO) = 30mA Off Leakage Current TTL/CMOS LOGIC INPUTS (F0, F1, RS, TST, RDI) Input Current IIH , 0V ≤ VIN ≤ 5V - - -1 µA Input Current IIL , 0V ≤ VIN ≤ 5V - - -100 µA Logic Low Output Voltage ILOAD = 800µA - 0.1 0.5 V Logic High Output Voltage ILOAD = 40µA 2.7 - 5.5 V - - - LOGIC OUTPUTS (SHD, RTD, ALM) POWER DISSIPATION Power Dissipation On Hook VCC = +5V, VBAT = -80V, RLOOP = ∞ - 300 - mW VCC = +5V, VBAT = -48V, RLOOP = ∞ - 150 - mW - 280 - mW Power Dissipation Off Hook VCC = +5V, VBAT = -24V, RLOOP = 600Ω, IL = 25mA ICC VCC = +5V, VBAT = -80V, RLOOP = ∞ - 3 6 mA VCC = +5V, VBAT = -48V, RLOOP = ∞ - 2 5 mA VCC = +5V, VBAT = -24V, RLOOP = ∞ - 1.9 5 mA IBAT VCC = +5V, VB- = -80V, RLOOP = ∞ - 3.6 7 mA VCC = +5V, VB- = -48V, RLOOP = ∞ - 2.6 6 mA VCC = +5V, VB- = -24V, RLOOP = ∞ - 2.3 4.5 mA NOTES: 2. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 3. This parameter directly affects device junction temperature. Refer to Power Dissipation discussion of data sheet for design information. 65 HC55171 Functional Diagram R TF 25 TF OUT 1 VRX R + 17 -IN 1 12 R 13 + VRING 24 VCC VTX 19 AGND 1 2 BIAS NETWORK OP AMP R/2 22 27 +2V BGND VBAT R/20 R TIP SENSE - 5 TA R + R 2R SH SHD THERM LTD 4.5K 25K 100K RING SENSE 1 RING SENSE 2 100K 15 16 TSD + 100K 25K GK RTD RA 100K 6 IIL LOGIC INTERFACE R 14 4 2R 7 8 RFC 90K RF 26 10 - GM 90K + R = 108kΩ 3 VREF VB/2 REF 18 NU 11 28 RTI 21 RF2 - + ILMT RS TST 90K RF F0 9 FAULT DET 4.5K F1 SHD RTD ALM RDO 20 RDI HC55171 DEVICE TRUTH TABLE Power Dissipation F1 F0 0 0 Loop power Denial Active 0 1 Power Down Latch RESET, Power on RESET Careful thermal design is required to guarantee that the maximum junction temperature of 150oC of the device is not exceeded. The junction temperature of the SLIC can be calculated using: 1 0 RD Active T J = T A + θ JA ( I CC V CC + I BAT V BAT – ( ( I LOOP ) • R LOOP ) ) 1 1 Normal Loop feed STATE The truth table for the internal logic of the HC55171 is provided in the above table. This family of ringing SLICS can be configured to support traditional unbalanced ringing and thru SLIC balanced ringing. Refer to the HC5509A1R3060 for unbalanced ringing application information. The device operating states used by thru SLIC ringing applications are loop power denial and normal feed. During loop power denial, the tip and ring amplifiers are disabled (high impedance) and the DC voltage of each amplifier approaches ground. The SLIC will not provide current to the subscriber loop during this mode and will not detect loop closure. Voice transmission occurs during the normal loop feed mode. During normal loop feed the SLIC is completely operational and performs all transmission and supervisory functions. 66 2 (EQ. 1) Where TA is maximum ambient temperature and θJA is junction to air thermal resistance (and is package dependent). The entire term in parentheses yields the SLIC power dissipation. The power dissipation of the subscriber loop does not contribute to device junction temperature and is subtracted from the power dissipation term. Operating at 85oC, the maximum PLCC SLIC power dissipation is 1.18W. Likewise, the maximum SOIC SLIC power dissipation is 0.92W. HC55171 Circuit Operation and Design Information Introduction Full Duplex Analog Transmission The HC55171 is a high voltage Subscriber Line Interface Circuit (SLIC) specifically designed for through SLIC ringing applications. Through SLIC ringing applications are broadly defined as any application that requires ringing capability but does not have the standard wired central office interface. The most common implementation of the ringing SLIC is in the analog pots port. The analog pots port provides the ringing function as well as interface compatibility with answering and fax machines. Familiarity with the signal paths of the SLIC is critical in understanding the full duplex transmission capability of the device. The analog interfaces of the SLIC are categorized as 2-wire interfaces and 4-wire interfaces. Subscriber Line Interface Basics The basic SLIC provides DC loop current to power the handset, supports full duplex analog transmission between the handset and CODEC, matches the impedance of the SLIC to the impedance of the handset and performs loop supervision functions to detect when the handset is off hook. The ringing SLIC adds through the SLIC ringing capability to this suite of features. The analog interfaces of the SLIC are categorized as the 2-wire interface (high voltage DC, differential AC) and the 4-wire interface (low voltage DC, single ended AC). The 2-wire interface of the SLIC consists of the bidirectional Tip and Ring terminals of the device. A differential transmitter drives AC signals out of the Tip and Ring terminals to the handset. A differential receiver across Tip and Ring receives AC signals from the handset. The differential receiver is connected across sense resistors that are in the Tip and Ring signal paths. The differential transmitter and receiver concept is depicted in Figure 2. DIFFERENTIAL TRANSMITTER -1 - + - DC Loop Current + - The Tip and Ring terminals of the subscriber line circuit are biased at negative potentials with respect to ground. The Tip terminal DC potential is slightly negative with respect to ground, and the ring terminal DC potential is slightly positive with respect to the battery voltage (resulting in a large negative voltage). The HC55171 typical Tip DC voltage is -4V and the typical ring DC voltage is defined as VBAT + 4V. For example, when the battery voltage is -24V the ring voltage is -20V. To clearly comprehend the Tip and Ring interface it is helpful to understand that the handset and the SLIC constitute a DC and AC current loop as shown in Figure 1. The loop is often referred to as the subscriber loop. TIP LOOP CURRENT SLIC RING FIGURE 1. SUBSCRIBER LOOP When the handset is on hook (idle) the phone is an open circuit load and the DC loop current is zero. The SLIC can still provide AC transmission in this condition, which supports caller id services. The DC resistance of the off hook handset is typically 400Ω. Since the Tip DC voltage is more positive than the ring DC voltage, DC loop current flows from Tip to Ring when the handset is off hook. The SLIC is designed with feedback to limit the maximum loop current when the handset is off hook. 67 + DIFFERENTIAL RECEIVER FIGURE 2. DIFFERENTIAL TRANSMIT/RECEIVE CONCEPT Since the receiver is connected across the transmit signal path, one may deduce that in addition to receiving signals from the handset, the receiver will detect part of the transmit signal. Indeed this does occur and is the reason that all SLIC circuits require a hybrid balance or echo cancellation function. The 4-wire interface of the SLIC consists of the receive (VRX) and transmit (OUT1) terminals. The 4-wire interfaces are single ended signal paths. The receiver is a dedicated input port and the transmitter is a dedicated output port. The 4-wire receive input of the SLIC drives the 2-wire differential transmitter and the 2-wire differential receiver drives the 4wire transmit output. The complete signal path for voice signals includes two digital data busses, a CODEC and a SLIC. There is a receive data bus and transmit data bus, each with an independent 3wire serial interface. The CODEC contains a coder and decoder. The coder converts the SLIC analog transmit output to digital data for the transmit data bus. The receive digital data bus is converted to analog data and drives the SLIC receive input. The CODECs use logarithmic compression schemes to extend the resolution of the 8-bit data to 14 bits. The accepted compression schemes are A-law (Intersil CODEC CD22357A) and µ-law (Intersil CODEC - CD22354A). The complete signal path from the handset to the CODEC is shown in Figure 3. HC55171 SLIC LOAD IMPEDANCE CODEC RSYNTH TIP VRX OUT1 RING RX OUT TX IN ANALOG PCM IN RP RS PCM OUT RP RS TIP RING RSYNTH SLIC SOURCE IMPEDANCE DIGITAL FIGURE 3. COMPLETE VOICE SIGNAL PATH FIGURE 4. SLIC IMPEDANCE DIAGRAM Impedance Matching showing the impedance terms is shown in Figure 4. Impedance matching is used to match the AC source impedance of the SLIC to the AC source impedance of the load. When the impedance is matched, the voltage level at the receive input of the SLIC will be the same voltage level that is at the 2-wire differential output (i.e., Tip and Ring). Impedance matching applies only to the 2-wire interface, not the 4-wire interface. Loop Supervision Slic AC signal power levels are most commonly assigned the units dBmO. The term dBmO refers to milliwatts in a 600Ω load. The typical AC power level is 0dBmO which is 1mW referenced to a 600Ω load. The relationship between dBmO and VRMS is provided in Equation 2. 2 ( V RMS ) dBmO = 10 ⋅ log 1000 ⋅ ------------------------ 600 (EQ. 2) Substituting 0dBmO into the equation should result in 0.7746 VRMS . For sinusoidal signals, multiply the RMS voltage by 1.414 to obtain the peak sinusoidal voltage. The SLIC impedance matching is achieved by applying a feed back loop from the transmit output of the SLIC to the receive input of the SLIC. The transmit output voltage of the HC55171 is proportional to the loop current (DC + AC) flowing in the subscriber loop. The impedance matching feedback only uses the AC portion of the transmit output voltage. Applying a voltage gain to the feedback term and injecting it into the receive signal path, will cause the SLIC to “synthesize” a source impedance that is nonzero. Recall that the impedance matching sets the SLIC source impedance equal to the load impedance. The SLIC application circuit requires external sense resistors in the Tip and Ring signal paths to achieve the differential receive function. The sense resistors contribute to the source impedance of the SLIC and are accounted for in the design equations. Specifically, if the load impedance is 600Ω and each sense resistor is 50Ω, the SLIC must synthesize an additional source impedance of 500Ω (i.e., 600Ω - 2(50Ω)). In addition to the sense resistors, some applications may use a protection resistor in each of the Tip and Ring leads as part of a surge protection network. These resistors also contribute to the SLIC source impedance and can be easily accounted for in the design equations. If 50Ω protection resistors are added to the prior example, the SLIC would then have to synthesize 400Ω to match the load (i.e., 600Ω - 2(50Ω) - 2(50Ω)). A diagram 68 -1 The SLIC must detect when the subscriber picks up the handset when the SLIC is not ringing the phone and when the SLIC is ringing the phone. The HC55171 uses a switch hook detector output to indicate loop closure when the SLIC is not ringing the phone. When the SLIC is ringing the phone, loop closure is indicated by the ring trip detector. (Recall from earlier discussions that the subscriber loop is open when the handset is on hook and closed when off hook. The DC impedance of the handset when off hook is typically 400Ω.) When the handset is off hook, DC loop current flows from Tip to Ring and the transmit output voltage increases to a negative value. In addition to interfacing to the CODEC and providing the feedback for impedance matching, the transmit output also drives the input to a voltage comparator. When the comparator threshold is exceeded, the SHD output goes to a logic low, indicating the handset is off hook. When the call is terminated and the handset is returned on hook, the transmit voltage decreases to zero, crossing the comparator threshold and setting SHD to a logic high. Loop closure must also be detected when the SLIC is ringing the handset. The balanced ringing output of the SLIC coincides with a zero DC potential between Tip and Ring. Therefore the ring trip must be designed around an AC only waveform at the transmit output. When the SLIC is ringing and the handset is on hook, the echo of the ringing signal is at the transmit output. When the handset goes off hook, the amplitude of the ringing echo increases. The increase in amplitude is detected by an envelope detector. When the echo increases, the envelope detector output increases and exceeds the ring trip comparator threshold. Then RTD goes to a logic low, indicating the handset is off hook. When the system controller detects a logic low on RTD, the ringing is turned off and the Tip and Ring terminals return to their typical negative DC potentials. Design Equations and Operational Theory The following discussion separates the SLICS’s operation into its DC and AC path, then follows up with additional circuit design and application information. HC55171 DC Operation of Tip and Ring Amplifiers SLIC in the Active Mode The tip and ring amplifiers are voltage feedback op amps that are connected to generate a differential output (e.g., if tip sources 20mA then ring sinks 20mA). Figure 5 shows the connection of the tip and ring amplifiers. The tip DC voltage is set by an internal +2V reference, resulting in -4V at the output. The ring DC voltage is set by the tip DC output voltage and an internal VBAT/2 reference, resulting in VBAT +4V at the output. (See Equation 3, Equation 4 and Equation 5.) R V TIPFEED = V C = – 2V ----------- = – 4V R ⁄ 2 (EQ. 3) V BAT R R V RINGFEED = V D = --------------- 1 + ---- – V TIPFEED ---- R 2 R (EQ. 4) V RINGFEED = V D = V BAT + 4 (EQ. 5) R R VRX TIP FEED RS1 R/20 VRING - + R/2 - V + C TRANSVERSAL AMP TA + INTERNAL - +2V REF - RIL1 - GM + RIL2 RF2 90kΩ RING FEED RING RP2 RS2 - 90kΩ + VOUT1, VRX GROUNDED FOR DC ANALYSIS + CIL - VD ( 0.6 ) ( R IL1 + R IL2 ) I LIMIT = -------------------------------------------------( 200xR IL2 ) - + VBAT (EQ. 7) 0 VTX + 90kΩ Current limiting is achieved by a feedback network (Figure 5) that modifies the ring feed voltage (VD) as a function of the loop current. The output of the Transversal Amplifier (TA) has a DC voltage that is directly proportional to the loop current. This voltage is scaled by RIL1 and RIL2 . The scaled voltage is the input to a transconductance amplifier (GM) that compares it to an internal reference level. When the scaled voltage exceeds the internal reference level, the transconductance amplifier sources current. This current charges CIL in the positive direction causing the ring feed voltage (VD) to approach the tip feed voltage (VC). This effectively reduces the tip feed to ring feed voltage (VT-R). and holds the maximum loop current constant. VTIP FEED = -4V TIP AND RING VOLTAGE (V) RP1 The tip feed to ring feed voltage (Equation 3 minus Equation 5) is equal to the battery voltage minus 8V. Thus, with a 48 (24) volt battery and a 600Ω loop resistance, including the feed resistors, the loop current would be 66.6mA (26.6mA). On short loops the line resistance often approaches zero and there is a need to control the maximum DC loop current. The maximum loop current is programed by resistors RIL1 and RIL2 as shown in Equation 7 (Note: RIL1 is typically 100kΩ). R OUT1 TIP Current Limit -5 CONSTANT VOLTAGE REGION -10 -15 VRING FEED = -20V -20 CURRENT LIMIT REGION ILOOP = 25mA 2 -25 0 250 500 750 LOOP RESISTANCE (Ω) ∞ FIGURE 5. OPERATION OF THE TIP AND RING AMPLIFIERS FIGURE 6. VT-R vs RL (VBAT = -24V, ILIMIT = 25mA) Transmit Output Voltage The transmit output voltage in terms of loop current is expressed as 200x ILOOP. The 200 term is actually formed by the sum of twice the sense resistors and is shown in the following equation. 200 × I LOOP = ( 2 ⋅ R S1 + 2 ⋅ R S2 ) × I LOOP (EQ. 6) This is a relationship that is critical when modifying the sense resistor (RS1, RS2). The 200 term factors into the loop current limit and loop detector functions of the SLIC. 69 Figure 6 illustrates the relationship between VT-R and the loop resistance. The conditions are shown for a battery voltage of -24V and the loop current limit set to 25mA. For an open circuit loop the tip feed and ring feed are at -4V and -20V respectively. When the loop resistance decreases from infinity to about 640Ω the loop current (obeying Ohm’s Law) increases from 0mA to the set loop current limit. As the loop resistance continues to decrease, the ring feed voltage approaches the tip feed voltage as a function of the programmed loop current limit (Equation 7). HC55171 AC Voltage Gain Design Equations The HC55171 uses feedback to synthesize the impedance at the 2-wire tip and ring terminals. This feedback network defines the AC voltage gains for the SLIC. The 4-wire to 2-wire voltage gain (VRX to VTR) is set by the feedback loop shown in Figure 7. The feedback loop senses the loop current through resistors RS1 and RS2 , sums their voltage drop and multiplies it by 2 to produce an output voltage at the VTX pin equal to +4RS∆IL . The VTX voltage is then fed into the -IN1 input of the SLIC’s internal op amp. This signal is multiplied by the ratio RZ0/RRF and fed into the tip current summing node via the OUT1 pin. (Note: the internal VBAT/2 reference (ring feed amplifier) and the internal +2V reference (tip feed amplifier) are grounded for the AC analysis.) The current into the summing node of TF amp is equal to: 4R S ∆I L R Z0 I OUT1 = – -------------------- ----------- R R RF (EQ. 8) Equation 9 is the node equation for the tip amplifier summing node. The current in the tip feedback resistor (IR) is given in Equation 7. 4R S ∆I L R Z0 V RX – I R – -------------------- ----------- + ----------- = 0 R R RF R 4R S ∆I L R Z0 V RX I R = – -------------------- ----------- + ----------R R RF R (EQ. 9) (EQ. 10) The AC voltage at VC is then equal to: (EQ. 15) Equation 15 simplifies to 2V RX – 400 ∆I L ∆I L = ---------------------------------------800 (EQ. 16) Solving for ∆IL results in V RX ∆I L = ----------600 (EQ. 17) Equation 17 is the loop current with respect to the feedback network. From this, the 4-wire to 2-wire and the 2-wire to 4-wire AC voltage gains are calculated. Equation 18 shows the 4-wire to 2-wire AC voltage gain is equal to 1.00. V RX ----------- ( 600 ) V TR ∆I L ( R L ) 600 A 4W – 2W = ----------- = --------------------- = --------------------------- = 1 V RX V RX V RX (EQ. 18) Equation 19 shows the 2-wire to 4-wire AC voltage gain is equal to -0.333. R Z0 V RX – 4 R S ∆I L ----------- – 200 ----------- ( 1 ) V OUT1 R RF 600 1 A 2W – 4W = ------------------- = ------------------------------------------ = ---------------------------------- = – --∆I L ( R L ) V TR V RX 3 ----------- ( 600 ) 600 (EQ. 19) Impedance Matching VC = ( IR ) ( R ) (EQ. 11) R Z0 V C = – 4 R S ∆I L ----------- + V RX R RF (EQ. 12) and the AC voltage at VD is: R Z0 V D = 4R S ∆I L ----------- – V RX R RF R Z0 2 × – 4 R S ∆I L ----------- + V RX R RF ∆I L = -----------------------------------------------------------------------------R L + R P1 + R P2 + R S1 + R S2 (EQ. 13) The feedback network, described above, is capable of synthesizing both resistive and complex loads. Matching the SLIC’s 2-wire impedance to the load is important to maximize power transfer and maximize the 2-wire return loss. The 2-wire return loss is a measure of the similarity of the impedance of a transmission line (tip and ring) and the impedance at it’s termination. It is a ratio, expressed in decibels, of the power of the outgoing signal to the power of the signal reflected back from an impedance discontinuity. Requirements for Impedance Matching The values for RZ0 and RRF are selected to match the impedance requirements on tip and ring, for more information refer to AN9607 “Impedance Matching Design Equations for the HC5509 Series of SLICs”. The following loop current calculations will assume the proper RZ0 and RRF values for matching a 600Ω load. The loop current (∆IL) with respect to the feedback network, is calculated in Equations 14 through 17. Where RZ0 = 40kΩ, RRF = 40kΩ, RL = 600Ω, RP1 = RP2 = RS1 = RS1 = 50Ω. VC – VD ∆I L = -----------------------------------------------------------------------------R L + R P1 + R P2 + R S1 + R S2 Substituting the expressions for VC and VD 70 (EQ. 14) Impedance matching of the HC55171 application circuit to the transmission line requires that the impedance be matched to points “A” and “B” in Figure 7. To do this, the sense and protection resistors RP1 , RP2 , RS1 and RS2 must be accounted for by the feedback network to make it appear as if the output of the tip and ring amplifiers are at points “A” and “B”. The feedback network takes a voltage that is equal to the voltage drop across the sense resistors and feeds it into the summing node of the tip amplifier. The effect of this is to cause the tip feed voltage to become more negative by a value that is proportional to the voltage drop across the sense resistors RP1 and RS1. At the same time the ring amplifier becomes more positive by the same amount to account for resistors RP2 and RS2 . The net effect cancels out the voltage drop across the feed resistors. By nullifying the effects of the feed resistors the HC55171 feedback circuitry becomes relatively easy to match the impedance at points “A” and “B”. RL LOAD Impedance Matching Design Equations Matching the impedance of the SLIC to the load is accomplished by writing a loop equation starting at VD and going around the loop to VC . The loop equation to match the impedance of any load is as follows (note: VRX = 0 for this analysis): R Z0 R Z0 – 4R S ∆I L ----------- + 2R S ∆I L – ∆V IN + R L ∆I L + 2R S ∆I L – 4R S ∆I L ----------- R RF R RF ∆VIN + - SLIC R Z0 8RS ------------- + 4R S R RF FIGURE 8. SCHEMATIC REPRESENTATION OF EQUATION 20 The result is shown in Equation 23. Figure 8 is a schematic representation of Equation 18. To match the impedance of the SLIC to the impedance of the load, set: (EQ. 20) R Z0 8R S ----------- + 4R S = R L R RF R Z0 ∆V IN = – 8R S ∆I L ----------- + 4R S ∆I L + R L ∆I L R RF (EQ. 21) If RRF is made to equal 8RS then: R Z0 ∆V IN = ∆I L – 8R S ----------- + 4R S + R L R RF (EQ. 22) (EQ. 25) R Z0 + 4R S = R L Equation 22 can be separated into two terms, the feedback (-8RS(RZ0/RRF)) and the loop impedance (+4RS+RL). ∆V IN R Z0 ------------- = – 8 R S ----------- + [ 4R S + R L ] ∆I L R RF (EQ. 23) (EQ. 24) Therefore to match the HC5517, with RS equal to 50Ω, to a 600Ω load: R RF = 8R S = 8 ( 50Ω ) = 400Ω (EQ. 26) and R Z0 = R L – 4 R S = 600Ω – 200Ω = 400Ω (EQ. 27) To prevent loading of the VTX output, the value of RZ0 and RRF are typically scaled by a factor of 100: KR Z0 = 40kΩ R – 4 ( R S ∆I L ) R V Z0 RX I R = ------------------------------ ------------- + ------------R R R RF + ∆IL - IR R (EQ. 28) Since the impedance matching is a function of the voltage gain, scaling of the resistors to achieve a standard value is recommended. R For complex impedances the above analysis is the same. + ∆IL - RP1 KR RF = 40kΩ R/20 RS1 - TIP Reactive ( KR RF = 40kΩ ) KR Z0 = 100 ( Resistive – 200 ) + -------------------------- 100 (EQ. 29) R/2 + - + VC A VC = –4 RS ∆ VTR Through SLIC Ringing ∆IL + RL ∆VIN RP1 = RP2 = RS1 = RS2 = RS + - Refer to application note AN9607 (“Impedance Matching Design Equations for the HC5509 Series of SLICs”) for the values of KRRF and KRZ0 for many worldwide typical line impedances. ∆IL + 90kΩ 90kΩ B RP2 RS2 - RING + - ∆IL + - ∆IL + + - VD V D = 4R S FIGURE 7. AC VOLTAGE GAI 71 The HC55171 uses linear amplification to produce the ringing signal. As a result the ringing SLIC can produce sinusoid, trapezoid or square wave ringing signals. Regardless of the wave shape, the ringing signal is balanced. The balanced waveform is another way of saying that the tip and ring DC potentials are the same during ringing. The following figure shows the Tip and Ring waveforms for sinusoid and trapezoid wave shapes as can be displayed using an oscilloscope. Pertinent Bellcore Ringing Specifications Bellcore has defined bounds around the existing unbalanced ringing signal that is supplied by the central office. The HC55171 circuit published in the HC5517 and HC55171 data sheet. GROUND TABLE 1. RING TRIP COMPONENT DIFFERENCES TIP COMPONENT RING BATTERY (A) SINUSOID GROUND TIP RING BATTERY (B) TRAPEZOID FIGURE 9. BALANCED RINGING WAVESHAPES HC55171 ringing SLIC meets the REN drive requirement, the crest factor limitations and the minimum RMS ringing voltage. The foremost requirement is that the ringing source must be able to drive 5 REN. A REN is a ringer equivalence number modeled by a 6.93kΩ resistor in series with a 8µF capacitor (see Figure 10). The impedance of 1 REN at 20Hz is approximately 7kΩ. 5 REN is equivalent to five of the networks in parallel. Figure 10 provides the Bellcore REN models. The crest factor of the ringing waveform is the ratio of the peak voltage to the RMS voltage. For reference, the crest factor of a sinusoid is 1.414 and of a square wave is 1.0. Bellcore defines the crest factor range from 1.2 to 1.6. A signal with a crest factor between 1.2 and 1.414 resembles the trapezoid of Figure 9. A signal with a crest factor between 1.414 and 1.6 resembles a “rounded triangular” wave shape and is an inefficient waveform for the ringing SLIC. 40µF 1386Ω 5 REN 8µF HC5517 COMPONENT HC55171 R15 47kΩ RRT3 51.1kΩ R17 56.2kΩ RRT1 49.9kΩ C10 1.0µF CRT 0.47µF The sinusoidal circuit published in the HC5517 can be used as an additional reference circuit for the HC55171. To generate a sinusoid ringing signal, two conditions must be met on the ringing (VRING) input of the SLIC. The first condition is that a positive DC voltage, which is directly related to the battery voltage, must be present at the ringing input. The DC voltage is used to force the Tip and Ring DC outputs to half the battery voltage. Having both the Tip and Ring amplifiers biased at the same DC voltage during ringing is one characteristic of balanced ringing. The centering voltage (VC) can be calculated from the following equation. V BAT V C = -------------– 4 ⁄ 20 2 (EQ. 30) Substituting values of battery voltage, the centering voltage is +1.8V for a -80V battery and +1.3V for a -60V battery. The second condition that must be met for sinusoidal ringing is a low level ringing signal must be applied to the ringing input of the SLIC. The AC signal that is present at VRING will be amplified by a gain of 20 through the Tip amplifier and a then inverted through the ring amplifier, resulting in a differential gain of 40. The maximum low level amplitude that can be injected for a given battery voltage can be determined from the following equation. V RING ( Max ) = ( V BAT – 8 ) ⁄ 20 (EQ. 31) The maximum output swing may be increased by driving the VRING negative by 200mV. Equation 31 can then by rewritten as: V RING ( Max ) = ( V BAT – 5 ) ⁄ 20 (EQ. 32) 6930Ω 1 REN FIGURE 10. BELLCORE RINGER EQUIVALENCE MODELS The third pertinent Bellcore requirement is the that RMS ringing voltage must be greater than 40VRMS at the telephone instrument. The HC5517 is able to deliver 40VRMS at the end of 500Ω loops. The 500Ω loop drive capability of the HC5517 is achieved with trapezoidal ringing. Sinusoidal Ringing The HC55171 uses the same sinusoidal application circuit as the HC5517. The only difference being the values of three components in the ring trip filter. The following table lists the components and the different values required by each device. All reference designators refer to the application 72 Exceeding the maximum signal calculated from the above equation will cause the peaks of the sinusoid to clip at ground and battery. The compression will reduce the crest factor of the waveform, producing a trapezoidal waveform. This is just one method, though inefficient, for achieving trapezoidal ringing. The application circuit provided with the HC55171 has been specifically developed for trapezoidal ringing and may also be used with the HC5517. Trapezoidal Ringing The trapezoidal ringing waveform provides a larger RMS voltage to the handset. Larger RMS voltages to the handset provide more power for ringing and also increase the loop length supported by the ringing SLIC. The HC55171 trapezoidal ringing application circuit will operate for loop lengths ranging from 0Ω to 500Ω. In addition, one HC55171 set of component values will satisfy the entire ringing loop range of the SLIC. A single resistor sets the open circuit RMS ringing voltage, which will set the crest factor of the ringing waveform. The crest factor of the HC55171 ringing waveform is independent of the ringing load (REN) and the loop length. Another robust feature of the HC55171 ringing SLIC is the ring trip detector circuit. The suggested values for the ring trip detector circuit cover quite a large range of applications. The assumptions used to design the trapezoidal ringing application circuit are listed below: • • • • • Loop current limit set to 25mA. Impedance matching is set to 600Ω resistive. 2-wire surge protection is not required. System able to monitor RTD and SHD. Logic ringing signal is used to drive RC trapezoid network. Crest Factor Programming As previously mentioned, a single resistor is required to set the crest factor of the trapezoidal waveform. The only design variable in determining the crest factor is the battery voltage. The battery voltage limits the peak signal swing and therefore directly determines the crest factor. A set of tables will be provided to allow selection of the crest factor setting resistor. The tables will include crest factors below the Bellcore minimum of 1.2 since many ringing SLIC applications are not constrained by Bellcore requirements. TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -80V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 65.0 825Ω 1.25 57.6 389Ω 1.15 62.6 964Ω 1.30 55.4 640Ω 1.20 60.0 1095Ω 1.35 53.3 The RMS voltage listed in the table is the open circuit RMS voltage generated by the SLIC. TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -75V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 60.9 1010Ω 1.25 53.7 500Ω 1.15 58.3 1190Ω 1.30 51.6 791Ω 1.20 55.9 1334Ω 1.35 49.7 TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -65V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 52.5 1330Ω 1.25 45.9 660Ω 1.15 49.8 1600Ω 1.30 44.1 1040Ω 1.20 47.8 1800Ω 1.35 42.5 73 TABLE 5. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -60V RTRAP CF RMS RTRAP CF RMS 0Ω 1.10 48.2 1460Ω 1.25 42.0 740Ω 1.15 45.6 1760Ω 1.30 40.4 1129Ω 1.20 43.7 2030Ω 1.35 38.8 Ringing Voltage Limiting Factors As the load impedance decreases (increasing REN), the feedback used for impedance synthesis slightly attenuates the ringing signal. Another factor that attenuates the ringing signal is the voltage divider formed by the sense resistors and the impedance of the ringing load. As the load impedance decreases, the 100Ω of sense resistors becomes a larger percentage of the load impedance. If surge protection resistance must be used with the trapezoidal circuit, the loop length performance of the circuit will decrease. The decrease in ringing loop length is caused by the addition of protection resistors in series with the Tip and Ring outputs. The amount of protection resistance that is added will subtract directly from the loop length. For example if 30Ω protection resistors is used in each of the Tip and Ring leads, the ringing loop length will decrease by a total of 60Ω. Therefore, subtracting 60Ω from the graphs will provide the reduced loop length data. Lab Measurements The lab measurements of the trapezoidal ringing circuit were made with the crest factor programming resistor set to 0Ω and the battery voltage set to -80V. The Bellcore suggested REN model was used to simulate the various ringing loads. A resistor in series with the Tip terminal was used to emulate loop length. A logic gate is used to drive the RC shaping network. When the crest factor programming resistor is set to 0Ω, the output impedance of the logic gate results in a 0.8V/ms slewing voltage on CTRAP. Each graph shows the RMS ringing voltage into a fixed REN load versus loop length. The ringing voltage was measured across the test load. Each test also verified proper operation of the ring trip detector. Proper ring trip detector operation is defined as a constant logic high while ringing and on hook and a constant logic low when off hook is detected. The component values in the application circuit provide a ring trip response in the 100ms to 150ms range. HC55171 55 RMS RINGING VOLTAGE RMS RINGING VOLTAGE 60 59 58 57 52 49 46 43 56 0 0 100 200 300 400 100 500 200 300 400 500 LOOP IMPEDANCE LOOP IMPEDANCE FIGURE 14. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 4 FIGURE 11. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 1 56 RMS RINGING VOLTAGE RMS RINGING VOLTAGE 58 56 54 52 52 48 44 40 50 0 0 100 200 300 400 500 FIGURE 12. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 2 300 400 500 LOOP IMPEDANCE Low Level Ringing Interface The trapezoidal application circuit only requires a cadenced logic signal applied to the wave shaping RC network to achieve ringing. When not ringing, the logic signal should be held low. When the logic signal is low, Tip will be near ground and Ring will be near battery. When the logic signal is high, Tip will be near battery and Ring will be near ground. 58 RMS RINGING VOLTAGE 200 FIGURE 15. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 5 LOOP IMPEDANCE 55 52 49 46 0 100 100 200 300 400 500 LOOP IMPEDANCE FIGURE 13. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 3 74 HC55171 Loop Detector Interface Tip-to-Ring Open Circuit Voltage The RTD output should be monitored for off hook detection during the ringing period. At all other times, the SHD should be monitored for off hook detection. The application circuit can be modified to redirect the ring trip information through the SHD interface. The change can be made by rewiring the application circuit, adding a pullup resistor to pin 23 and setting F0 low for the entire duration of the ringing period. The modifications to the application circuit for the single detector interface are shown in Figure 16. The tip-to-ring open-circuit voltage, VOC, of the HC55171 may be programmed to meet a variety of applications. The design of the HC5517 defaults the value of VOC to: HC55171 ADDITIONAL PULL UP RESISTOR VCC NU 23 RDI 20 RDO 21 RTRAP VRING VRING 24 DTRAP V OC ≅ V BAT – 8 Using a zener diode clamping circuit, the default open circuit voltage of the SLIC may be defeated. Some applications that have to meet Maintenance Termination Unit (MTU) compliance have a few options with the HC55171. One option is to reduce the ringing battery voltage until MTU compliance is achieved. Another option is to use a zener clamping circuit on VREF to over ride the default open circuit voltage when operating from a high battery. If a clamping network is used it is important that it is disabled during ringing. The clamping network must be disabled to allow the SLIC to achieve its full ringing capability. A zener clamping circuit is provided in Figure 18. CTRAP HC55171 FIGURE 16. APPLICATION CIRCUIT WIRING FOR SINGLE LOOP DETECTOR INTERFACE CIL VREF 3 +5V SLIC Operating State During Ringing The SLIC control pin F1 should always be a logic high during ringing. The control pin F0 will either be a constant logic high (two detector interface) or a logic low (single detector interface). Figure 17 shows the control interface for the dual detector interface and the single detector interface. (DUAL DETECTOR INTERFACE) ACTIVE RINGING ACTIVE (LOGIC HI) F1 SHD RTD ACTIVE RINGING ACTIVE (LOGIC HI) V BAT V RDC = 2 --------------- + 4 2 (EQ. 33) V BAT --------------- ≥ V Z 2 V RDC = 2 ( – V Z + ( V CE – V BE ) ) + 4 (EQ. 34) V BAT --------------- < V Z 2 V BAT V OC = V TDC – 2 --------------- – 4 2 V BAT --------------- ≥ V Z 2 V OC = V TDC – 2 ( – V Z + ( V CE – V BE ) ) – 4 (EQ. 35) (EQ. 36) (LOGIC HI) F0 VRING VALID DET V BAT --------------- < V Z 2 SHD (SINGLE DETECTOR INTERFACE) F1 FIGURE 18. ZENER CLAMP CIRCUIT WITH DISABLE Where VZ is the zener diode voltage and VCE and VBE are the saturation voltages of the pnp transistor. Using Equations 31 and 32, the tip-to-ring open-circuit voltage can be calculated for any value of zener diode and battery voltage. VRING MODE EN (LOGIC HI) F0 VALID DET 2N2907 The following equations are used to predict the DC output of the ring feed amplifier when using the zener clamping network, VRDC. Additional Application Information MODE 47kΩ SHD SHD FIGURE 17. DETECTOR LOGIC INTERFACES 75 SHD When the base of the pnp transistor is pulled high (+5V), the transistor is off and the zener clamp is disabled. When the base of the transistor is pulled low (0V) the transistor is on and the zener will clamp as long as half the battery voltage is greater than the zener voltage. HC55171 Polarity Reversal The HC55171 supports applications that use polarity reversal outside the speech phase of a call connection. The most common implementation of this type of polarity reversal is used with pay phones. By reversing the polarity of the tip and ring terminals of a pay phone, DC current changes direction in a solenoid and the coins are released from the phone. To reverse the polarity of the HC55171, simply toggle the VRING input high. Setting the VRING input high will cause Tip and Ring to reverse polarity. Transhybrid Balance Since the receive signal and its echo are 180 degrees out of phase, the summing node of an operational amplifier can be used to cancel the echo. Nearly all CODECs have an internal amplifier for echo cancellation. The following Figure 19 shows the cancellation amplifier circuit. RA RF RB - + VO FIGURE 19. TRANHYBRID AMPLIFIER CIRCUIT When the SLIC is matched to a 600Ω load, the echo amplitude is 1/3 the receive input amplitude. Therefore, by configuring the transhybrid amplifier with a gain of 3 in the echo path, cancellation can be achieved. The following equations: R F R F V O = – V RX -------- + V OUT1 -------- R A R B (EQ. 37) Substituting the fact that VOUT1 is -1/3 of VRX R F 1 R F V O = – V RX -------- – V RX --- -------- R 3 R B A (EQ. 38) Since cancellation implies that under these conditions, the output VO should be zero, set Equation 37 equal to zero and solve for RB. RA R B = -------3 (EQ. 39) Another outcome of the transhybrid gain selection is the 2wire to 4-wire gain of the SLIC as seen by the CODEC. The 1/3 voltage gain in the transmit path is relevant to the receive input as well as any signals from the 2-wire side. Therefore by setting the VOUT1 gain to three in the previous analysis, the 2-wire to 4-wire gain was set to unity. Single Supply Codec Interface The majority of CODECs that interface to the ringing SLIC operate from a single +5V supply and ground. Figure 20 shows the circuitry required to properly interface the ringing SLIC to the single supply CODEC. The CODEC signal names may vary from different manufacturers, but the function provided will be the same. 76 Layout Guidelines and Considerations The printed circuit board trace length to all high impedance nodes should be kept as short as possible. Minimizing length will reduce the risk of noise or other unwanted signal pickup. The short lead length also applies to all high gain inputs. The set of circuit nodes that can be categorized as such are: • • • • VRX pin 27, the 4-wire voice input. -IN1 pin 13, the inverting input of the internal amplifier. VREF pin 3, the noninverting input to ring feed amplifier. VRING pin 24, the 20V/V input for the ringing signal. For multi layer boards, the traces connected to tip should not cross the traces connected to ring. Since they will be carrying high voltages, and could be subject to lightning or surge depending on the application, using a larger than minimum trace width is advised. VRX VOUT1 The DC reference from the CODEC is used to bias the analog signals between +5V and ground. The capacitors are required so that the DC gain is unity for proper biasing from the CODEC reference. Also, the capacitors block DC signals that may interfere with SLIC or CODEC operation. The 4-wire transmit and receive signal paths should not cross. The receive path is any trace associated with the VRX input and the transmit path is any trace associated with VTX output. The physical distance between the two signal paths should be maximized to reduce crosstalk. The mode control signals and detector outputs should be routed away from the analog circuitry. Though the digital signals are nearly static, care should be taken to minimize coupling of the sharp digital edges to the analog signals. The part has two ground pins, one is labeled AGND and the other BGND. Both pins should be connected together as close as possible to the SLIC. If a ground plane is available, then both AGND and BGND should be connected directly to the ground plane. A ground plane that provides a low impedance return path for the supply currents should be used. A ground plane provides isolation between analog and digital signals. If the layout density does not accommodate a ground plane, a single point grounding scheme should be used. CODEC VRX RX OUT RA RF RB + TX IN VOUT1 HC55171 +2.5V + - FIGURE 20. SINGLE SUPPLY CODEC INTERFACE HC55171 Pin Descriptions PLCC SYMBOL DESCRIPTION 1 AGND 2 VCC Positive Voltage Source - Most Positive Supply. 3 VREF An external voltage connected to this pin will override the internal VBAT/2 reference. 4 F1 Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will ramp close to the output voltage of the tip amplifier. 5 F0 TTL compatible logic control input that must be tied high for proper SLIC operation. 6 RS TTL compatible logic control input that must be tied high for proper SLIC operation. 7 SHD Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition. 8 RTD Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is ringing. 9 TST A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller. 10 ALM A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die temperature has been exceeded. 11 ILMT Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions. 12 OUT1 The analog output of the spare operational amplifier. 13 -IN1 The inverting analog input of the spare operational amplifier. The non-inverting input is internally connected to AGND. 14 TIP SENSE An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions with the RING terminal to receive voice signals and for loop monitoring purpose. 15 RING SENSE 1 An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions with the TIP terminal to receive voice signals and for loop monitoring purposes. 16 RING SENSE 2 This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation. 17 VRX Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers deferentially. 18 NU Not used in this application.This pin should be left floating. 19 VTX Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary. 20 RDI TTL compatible input to drive the uncommitted relay driver. 21 RDO This is the output of the uncommitted relay driver. 22 BGND 23 NU 24 VRING 25 TF This is the output of the tip amplifier. 26 RF This is the output of the ring amplifier. 27 VBAT 28 RTI Analog Ground - Serves as a reference for the transmit output and receive input terminals. Battery Ground - All loop current and some quiescent current flows into this terminal. Not used in this application. This pin should be either grounded or left floating. Ring signal input. The negative battery source. Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection. 77 HC55171 Pinouts 3 1 28 VBAT RTI AGND VCC 2 HC55171 (SOIC) TOP VIEW 27 RF 4 VREF F1 HC55171 (PLCC) TOP VIEW AGND 1 26 VCC 2 28 RTI 27 VBAT VREF 3 26 RF F1 4 25 TF F0 5 25 TF RS 6 24 VRING F0 5 24 VRING SHD 7 23 NU RS 6 23 NU RTD 8 22 BGND SHD 7 22 BGND RTD 8 21 RDO TST 9 21 RDO ALM 10 20 RDI ILMT 11 12 13 14 15 16 17 18 OUT 1 -IN 1 TIP SENSE RING SENSE 1 RING SENSE 2 VRX NU 19 VTX TST 9 20 RDI ALM 10 19 VTX ILMT 11 18 NU 17 VRX OUT 1 12 -IN 1 13 16 RING SENSE 2 TIP SENSE 14 15 RING SENSE 1 Trapezoidal Ringing Application Circuit U1 HC55171 14 TIP SENSE TIP RS1 CRX VRX 17 V-REC 25 TF RIL2 ILIMT 11 RIL1 26 RF 16 RING SENSE 2 VTX 19 RS2 CAC 15 RING SENSE 1 RING RRF -IN1 13 RZO OUT1 12 V-XMIT 2 VCC VCC CPS1 1 AGND RRT2 RRT1 RTI 28 22 BGND RRT3 DRT CRT CPS2 27 VBAT VBAT RTRAP VRING VRING 24 CIL DTRAP CTRAP VREF 3 F1 4 F1 F0 5 F0 VCC TST 6 RS 9 TST SHD 7 SHD RTD 8 RTD ALM 10 ALM 20 RDI FIGURE 21. TRAPEZOIDAL RINGING APPLICATION CIRCUIT 78 HC55171 HC55171 Trapezoidal Ringing Application Circuit Parts List COMPONENT VALUE TOLERANCE RATING U1 - Ringing Slic HC55171 N/A N/A RS1, RS2 49.9Ω 1% RZO, RIL1 56.2kΩ RRT1 COMPONENT VALUE TOLERANCE RATING RIL2 7.68kΩ 1% 1/8W 1/2W RTRAP App Driven 1% 1/8W 1% 1/8W CPS1, CPS2 0.1µF 10% 100V 49.9kΩ 1% 1/8W CIL, CRT, CAC, CRX 0.47µF 10% 50V RRT2 1.5MΩ 1% 1/8W CTRAP 4.7µF 10% 10V RRT3 51.1kΩ 1% 1/8W DRT, DTRAP 1N914 RRF 45.3kΩ 1% 1/8W Generic Rectifier Diode All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 79 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029