AKM AKD4523 20bit stereo adc & dac Datasheet

ASAHI KASEI
[AK4523]
AK4523
20Bit Stereo DS ADC & DAC
GENERAL DESCRIPTION
The AK4523 has a dynamic range of 100dB and is well-suited middle-range MD, surround system,
musical instruments and car audio. Signal inputs and outputs are single-ended. The DAC outputs are
analog filtered to remove out of band noise. External components are minimized.
FEATURES
o DS Stereo ADC
- 64x Oversampling
- Sample Rate Ranging from 16kHz to 48kHz
- S/(N+D): 92dB
- Dynamic range, S/N: 100dB
- Digital HPF for offset cancellation
o DS Stereo DAC
- 128x Oversampling
- Sampling Rate Ranging from 16kHz to 48kHz
- 2nd order SCF + 2nd order CTF
- Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling
- S/(N+D): 90dB
- Dynamic Range, S/N: 100dB
- Soft Mute
o High Jitter Tolerance
o Master Clock: 256fs, 384fs, 512fs
o Analog Power Supply: 4.5 to 5.5V, Digital Power Supply: 3.0 to 5.5V
VA
AINL+
AINLAINR+
AINR-
AGND
VD DGND
CMODE
DS
Modulator
Decimation
Filter
HPF
DS
Modulator
Decimation
Filter
HPF
AOUTL
AOUTR
Common Voltage
LPF
LPF
MCKI
LRCK
VREFH
VCOM
Clock
Divider
SCLK
Serial I/O
Interface
SDTO
SDTI
DS
Modulator
8x
Interpolator
DIF0
DS
Modulator
8x
Interpolator
SMUTE
DIF1
DEM0 DEM1
PD
M0021-E-03
1999/12
-1-
ASAHI KASEI
[AK4523]
n Ordering Guide
-40 ~ +85°C
28pin VSOP (0.65mm pitch)
Evaluation Board for AK4523
AK4523VF
AKD4523
n Pin Layout
VREFH
1
28
VCOM
AINR+
2
27
AOUTR
AINR-
3
26
AOUTL
AINL+
4
25
CMODE
AINL-
5
VA
6
AGND
7
NC
24
PD
23
DGND
22
VD
8
21
NC
NC
9
20
NC
DIF0
10
19
MCKI
DIF1
11
18
DEM1
LRCK
12
17
DEM0
SCLK
13
16
SMUTE
SDTI
14
15
SDTO
AK4523
Top
View
n Difference between AK4523 and AK4522
Digital Power Supply
Ambient Operating
Package
AK4523
3.0~5.5V
-40~85°C
28pin VSOP
AK4522
2.7~5.5V
-10~70°C
24pin VSOP
M0021-E-03
1999/12
-2-
ASAHI KASEI
[AK4523]
PIN/FUNCTION
No.
Pin Name
I/O
1
VREFH
I
2
3
4
5
6
7
8
AINR+
AINRAINL+
AINLVA
AGND
NC
I
I
I
I
-
9
NC
-
10
11
12
13
14
15
16
DIF0
DIF1
LRCK
SCLK
SDTI
SDTO
SMUTE
I
I
I
I
I
O
I
17
18
19
20
DEM0
DEM1
MCKI
NC
I
I
I
-
21
NC
-
22
23
24
25
VD
DGND
PD
CMODE
I
I
26
27
28
AOUTL
AOUTR
VCOM
O
O
O
Function
Positive Voltage Reference Input Pin, VA
Used as a positive voltage reference by ADC & DAC. VREFH should be connected
externally to filtered VA.
Rch Analog Positive Input Pin
Rch Analog Negative Input Pin
Lch Analog Positive Input Pin
Lch Analog Negative Input Pin
Analog Power Supply Pin
Analog Ground Pin
No connect
No internal bonding.
No connect
No internal bonding.
Audio Data Interface Format 0 Pin
Audio Data Interface Format 1 Pin
Input Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
Audio Serial Data Output Pin
Soft Mute Pin
When this pin goes “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
De-emphasis Frequency Select 0 Pin
De-emphasis Frequency Select 1 Pin
Master Clock Input Pin
No connect
No internal bonding.
No connect
No internal bonding.
Digital Power Supply Pin
Digital Ground Pin
Power-Down Mode Pin
Master Clock Select Pin
(Internal biased pin)
“H”: 384fs, “L”: 256fs, “NC”: 512fs
Lch Analog Output Pin
Rch Analog Output Pin
Common Voltage Output Pin, VA/2
Note: All input pins except for CMODE pin should not be left floating.
M0021-E-03
1999/12
-3-
ASAHI KASEI
[AK4523]
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
|AGND-DGND|
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
(Note 2)
Symbol
VA
VD
DGND
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-40
-65
max
6.0
6.0
0.3
±10
VA+0.3
VD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
Note:1. All voltages with respect to ground.
2. AGND and DGND must be same voltage.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 3)
Digital
Voltage Reference
Symbol
VA
VD
VREFH
min
4.5
3.0
90%VA
typ
5.0
5.0
max
5.5
VA
VA
Units
V
V
V
Note:1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
M0021-E-03
1999/12
-4-
ASAHI KASEI
[AK4523]
ANALOG CHARACTERISTICS
(Ta=25°C; VA, VD=5V; AGND=DGND=0V; VREFH=VA; fs=44.1kHz; SCLK=64fs;
Signal Frequency =1kHz; 20bit Data; Measurement Frequency=10Hz ~ 20kHz; unless otherwise specified)
Parameter
min
typ
max
ADC Analog Input Characteristics: Differential Inputs; Analog Source Impedance=470W
Resolution
20
S/(N+D)
(-0.5dB Input)
(Note 4)
84
92
DR
(-60dB Input, A-Weighted)
(Note 5)
94
100
S/N
(A-Weighted)
(Note 5, 6)
94
100
Interchannel Isolation
90
110
Interchannel Gain Mismatch
0.1
0.3
Gain Drift
20
Input Voltage
(AIN=0.6 x VREFH)
(Note 7)
2.85
3.0
3.15
Input Resistance
15
25
Power Supply Rejection
(Note 8)
50
DAC Analog Output Characteristics:
Resolution
20
S/(N+D)
80
90
DR
(-60dB Output, A-Weighted)
(Note 5)
94
100
S/N
(A-Weighted)
(Note 6, 9)
94
100
Interchannel Isolation
90
110
Interchannel Gain Mismatch
0.2
0.5
Gain Drift
20
Output Voltage
(AOUT=0.58 x VREFH)
2.65
2.9
3.15
Load Resistance
5
Load Capacitance
25
Power Supply Rejection
(Note 8)
50
Units
Bits
dB
dB
dB
dB
dB
ppm/°C
Vpp
kW
dB
Bits
dB
dB
dB
dB
dB
ppm/°C
Vpp
kW
pF
dB
Power Supplies
Power Supply Current (VA=VD=5V)
Analog, VA
PD = “H”
Digital, VD
PD = “H”
Power Down PD = “L”
(Note 10)
42
10
0.4
55
20
2
mA
mA
mA
Note: 4. In case of single ended input, S/(N+D)=80dB(typ, @VA=5V).
5. In case of 16bit, DR and S/N of ADC are 98dB. DR of DAC is 98dB.
6. S/N measured by CCIR-ARM is 96dB at each converter and 94dB at ADC to DAC loopback.
7. Full scale input for each AIN+/- pin is 1.5Vpp in differential mode.
8. PSR is applied to VA, VD with 1kHz, 50mVpp. VREFH pin is held a constant voltage.
9. As the input data is “0”, S/N is 100dB regardless of resolution.
10. All digital input pins are held VD or DGND.
M0021-E-03
1999/12
-5-
ASAHI KASEI
[AK4523]
FILTER CHARACTERISTICS
(Ta=25°C; VA=4.5 ~ 5.5V, VD=3.0 ~ 5.5V; DEM0=”1”, DEM1=”0”)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
PB
0
Passband
(Note 11) -0.005dB
0
-0.02dB
0
-0.06dB
0
-6.0dB
Stopband
SB
24.34
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay
(Note 12)
GD
Group Delay Distortion
DGD
ADC Digital Filter (HPF):
Frequency Response
(Note 5) -3dB
FR
-0.5dB
-0.1dB
DAC Digital Filter:
Passband
(Note 11) -0.06dB
PB
0
-6.0dB
0
Stopband
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
43
Group Delay
(Note 12)
GD
DAC Digital Filter + Analog Filter:
FR
Frequency Response:
0 ~ 20.0kHz
typ
max
Units
19.76
20.02
20.20
22.05
29.3
0
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
0.9
2.7
6.0
Hz
Hz
Hz
±0.005
20.0
22.05
±0.06
14.7
±0.2
-
kHz
kHz
kHz
dB
dB
1/fs
dB
Note:11. The passband and stopband frequencies scale with fs.
For example, 20.02kHz at -0.02dB is 0.454 x fs. The reference frequency of these responses is 1kHz.
12. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 20bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 20bit data of both channels on input register to the output of analog
signal.
M0021-E-03
1999/12
-6-
ASAHI KASEI
[AK4523]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=4.5 ~ 5.5V, VD=3.0 ~ 5.5V)
Parameter
High-Level Input Voltage (Except CMODE pin)
Low-Level Input Voltage (Except CMODE pin)
High-Level Input Voltage
(CMODE pin)
Low-Level Input Voltage
(CMODE pin)
Hight-Level Output Voltage
(Iout=-80µA)
Low-Level Output Voltage
(Iout=80µA)
Input Leakage Current
(Note 13)
Symbol
VIH
VIL
VIH
VIL
VOH
VOL
Iin
min
70%VD
95%VD
VD-0.4
-
typ
-
Max
30%VD
10%VD
0.4
±10
Units
V
V
V
V
V
V
µA
Note: 13. CMODE pin has internal pull-up and pull-down devices, nominally 50kohm.
M0021-E-03
1999/12
-7-
ASAHI KASEI
[AK4523]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=4.5 ~ 5.5V; VD=3.0 ~ 5.5V; CL=20pF)
Parameter
Symbol
Master Clock Timing
256fs:
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
384fs:
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
512fs:
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Timing
Frequency
fs
Duty Cycle
dfs
Serial Interface Timing
SCLK Period
tSCK
SCLK Pulse Width Low
tSCKL
Pulse Width High
tSCKH
tLRS
LRCK Edge to SCLK “­”
(Note 14)
tSLR
SCLK “­” to LRCK Edge
(Note 14)
tLRM
LRCK to SDTO (MSB)
tSSD
SCLK “¯” to SDTO
tSDH
SDTI Hold Time
tSDS
SDTI Setup Time
Reset Timing
PD Pulse Width
PD “­” to SDTO valid
(Note 15)
(Note 16)
tPD
tPDV
min
typ
max
Units
4.096
27
27
6.144
20
20
8.192
15
15
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
16
45
48
55
18.432
24.576
320
65
65
45
45
40
70
40
25
150
516
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note 14. SCLK rising edge must not occur at the same time as LRCK edge.
15. The AK4523 can be reset by bringing PD “L”.
When the state of CMODE change during operation, the AK4523 should be reset by PD .
16. These cycles are the number of LRCK rising from PD rising.
M0021-E-03
1999/12
-8-
ASAHI KASEI
[AK4523]
n Timing Diagram
50%VD
LRCK
tSLR
tSLKL
tLRS
tSLKH
SCLK
50%VD
tLRM
tSSD
50%VD
SDTO
tSDH
tSDS
50%VD
SDTI
Serial Interface Timing
tPD
70%VD
PD
30%VD
tPDV
SDTO
Reset & Initialize Timing
M0021-E-03
1999/12
-9-
ASAHI KASEI
[AK4523]
OPERATION OVERVIEW
n System Clock
The master clock (MCLK) can be external clock input to the MCKI pin. CMODE is used to select either MCLK=256fs,
384fs or 512fs. The relationship between the MCLK and the desired sample rate is defined in Table 1. The LRCK clock
input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon
power-up. All external clocks must be present unless PD = “L”, otherwise excessive current may result from abnormal
operation of internal dynamic logic.
fs
32.0kHz
44.1kHz
48.0kHz
256fs
CMODE = “L”
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
CMODE = “H”
12.2880MHz
16.9344MHz
18.4320MHz
SCLK
512fs
CMODE = “NC”
16.384MHz
22.579MHz
24.576MHz
64fs
2.048MHz
2.822MHz
3.072MHz
Table 1. System Clock Example
When the state of CMODE change under operation, the AK4523 should be reset by PD . At that case, the analog outputs
should be muted externally because some click noise may occur.
M0021-E-03
1999/12
- 10 -
ASAHI KASEI
[AK4523]
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes selected by the DIF0 and
DIF1 pins are supported as shown in Table 2. In all modes the serial data has MSB first, 2’s compliment format. The data
is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least
significant bits will be truncated.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS (I2S)
SDTI (DAC)
16bit, LSB justified
20bit, LSB justified
20bit, MSB justified
IIS (I2S)
L/R
H/L
H/L
H/L
L/H
SCLK (Slave)
³ 32fs
³ 40fs
³ 40fs
32fs or ³ 40fs
Table 2. Serial Data Modes
LRCK(i)
0
1
2
3
9
10
11
12
13
14
15
0
1
2
9
10
11
12
13
14
15
0
1
SCLK(i:32fs)
SDTO(o)
19 18 17
11 10
9
8
7
6
5
4
19 18 17
11 10
9
8
7
6
5
4
19
SDTI(i)
15 14 13
7
6
5
4
3
2
1
0
15 14 13
7
5
4
3
2
1
0
15
0
1
2
3
17
18
19
20
30
31
0
1
2
3
6
17
18
19
20
31
0
1
SCLK(i:64fs)
SDTO(o)
19 18 17
SDTI(i)
3
Don’t Care
2
1
15 14 13
0
19 18 17
12 11
2
1
3
Don’t Care
0
2
1
0
19
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
2
1
0
Rch Data
Figure 1. Mode 0 Timing
LRCK(i)
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
1
SCLK(i:64fs)
SDTO(o)
SDTI(i)
19 18
8
Don’t Care
7
6
19 18
0
19 18
12 11
1
0
Don’t Care
8
7
6
19 18
0
12 11
19
1
0
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
M0021-E-03
1999/12
- 11 -
ASAHI KASEI
[AK4523]
LRCK(i)
0
1
2
17
18
19
20
21
0
1
2
17
18
19
20
21
0
1
SCLK(i:64fs)
SDTO(o)
19 18
3
2
1
0
SDTI(i)
19 18
3
2
1
0
19:MSB, 0:LSB
Don’t Care
19 18
3
2
1
0
23 22
3
2
1
0
Lch Data
19
Don’t Care
19
Rch Data
Figure 3. Mode 2 Timing
LRCK(i)
0
1
2
3
9
10
11
12
13
14
15
0
1
2
9
10
11
12
13
14
15
0
1
SCLK(i:32fs)
SDTO(o)
SDTI(i)
4
0
19 18
1
2
12 11 10
3
17
18
9
19
8
20
7
21
6
5
31
4
0
19 18
1
2
12 11 10
3
17
18
9
19
8
20
7
21
6
5
31
4
0
1
SCLK(i:64fs)
SDTO(o)
19 18
4
3
2
1
0
SDTI(i)
19 18
4
3
2
1
0
19:MSB, 0:LSB
Don’t Care
19 18
4
3
2
1
0
19 18
4
3
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 4. Mode 3 Timing
n Digital High Pass Filter
The ADC of AK4523 has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at
fs=44.1kHz and also scales with sampling rate (fs).
M0021-E-03
1999/12
- 12 -
ASAHI KASEI
[AK4523]
n De-emphasis Filter
The DAC of AK4523 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 is enabled for input audio
data. The de-emphasis is also disabled at DEM0=”1” and DEM1=”0”.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Table 3. De-emphasis filter control
n Soft Mute Operation
Soft mute operation is performed at digital domain. When SMUTE goes to “H”, the output signal is attenuated by -¥
during 1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually
changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the
operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source
without stopping the signal transmission.
S M UTE
1 0 2 4 /fs
0dB
1 0 2 4 /fs
(1 )
(3 )
A tten u ation
-¥
GD
(2 )
N oise level
GD
-1 0 0 d B
Notes:
(1) The output signal is attenuated by -¥ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
Figure 5. Soft Mute Operation
M0021-E-03
1999/12
- 13 -
ASAHI KASEI
[AK4523]
n Power-Down & Reset
The ADC and DAC of AK4523 are placed in the power-down mode by bringing a power down pin, PD “L” and each
digital filter is also reset at the same time.This reset should always be done after power-up. In case of the ADC, an analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after
516 cycles of LRCK clock. This initialization cycle does not affect the DAC operation. Figure 6 shows the power-up
sequence.
PD
516/fs
ADC Internal
State
Normal Operation
Power-down
DAC Internal
State
Normal Operation
Power-down
(1)
Init Cycle
Normal Operation
Normal Operation
GD (2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
(4)
(2)
GD
GD
(5)
DAC Out
(Analog)
(5)
Clock In
MCLK,LRCK,SCLK
The clocks may be stopped.
External
Mute
(6)
Mute ON
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Small click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(5) Click noise occurs at the edge of PD .
(6) Please mute the analog output externally if the click noise (5) influences system application.
Figure 6. Power-up sequence
M0021-E-03
1999/12
- 14 -
ASAHI KASEI
[AK4523]
SYSTEM DESIGN
Figure 7 shows the system connection diagrams. This is an example which analog signal is input by single ended circuit. In
case of differential input, please refer to Figure 10. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
4.5 ~ 5.5V
Analog Supply
3.0 ~ 5.5V
Digital Supply
10u +
0.1u
0.1u
+
10u
470
2.2n
470
4.7u
2.2n
4.7u
0.1u
+
0.1u
+
1
VREFH
VCOM
28
2
AINR+
AOUTR
27
26
3
AINR-
AOUTL
4
AINL+
CMODE
5
AINL-
6
VA
25
PD
24
DGND
23
0.1u
Format
Setting
Audio
Controller
VD
22
NC
21
NC
20
MCKI
19
7
AGND
8
NC
9
NC
10
DIF0
11
DIF1
DEM1
18
12
LRCK
DEM0
17
13
SCLK
SMUTE
16
14
SDTI
SDTO
15
AK4523
0.1u
5
+
10u
Mode
Setting
Figure 7. Typical Connection Diagram
M0021-E-03
1999/12
- 15 -
ASAHI KASEI
[AK4523]
A nalog G rou nd
1
V RE FH
V CO M
28
2
A INR+
A OU TR
27
3
A INR-
A OU TL
26
4
A INL+
CM O DE
25
5
A INL-
6
VA
7
A GN D
8
NC
9
NC
NC
20
19
PD
24
DG ND
23
VD
22
NC
21
AK 4523
10
DIF 0
M CK I
11
DIF 1
DE M 1
18
12
LRCK
DE M 0
17
13
S CLK
S M UTE
16
14
S DTI
S DTO
15
Digital Ground
System
Controller
Figure 8. Ground Layout
5V analog
VA
5V digital
VD
VD
System
Controller
AK4523
Case 1. 5V system
5V analog
VA
3V digital
VD
VD
System
Controller
AK4523
Case 2. 5V/3V system
Figure 9. Power Supply Arrangement
M0021-E-03
1999/12
- 16 -
ASAHI KASEI
[AK4523]
1. Grounding and Power Supply Decoupling
The AK4523 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical.
AGND and DGND of the AK4523 should be connected to analog ground plane. System analog ground and digital ground
should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors
should be as near to the AK4523 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The differential voltage between VREFH and AGND sets the analog input/output range. VREFH pin is normally
connected to VA with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10µF
parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load
current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM
pins in order to avoid unwanted coupling into the AK4523.
3. Analog Inputs
The ADC inputs are differential and internally biased to the common voltage (VA/2) with 25kW (typ) resistance. Figure 7
is a circuit example which analog signal is input by single end. The signal can be input from either positive or negative
input and the input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. In case of single ended
input, the distortion around full scale degrades compared with differential input. Figure 10 is a circuit example which
analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and
nominally 0.3 x VREFH Vpp. The AK4523 can accept input voltages from AGND to VA. The ADC output data format is
2’s complement. The output code is 7FFFFH(@20bit) for input above a positive full scale and 80000H(@20bit) for input
below a negative fill scale. The ideal code is 00000H(@20bit) with no input signal. The DC offset is removed by the
internal HPF.
The AK4523 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have
significant energy at 64fs.
4.7k
10k
1.5Vpp
AK4523
1.5nF
330
AINR+ 2
330
AINR-
3
AINL+
4
AINL-
5
+
NJM2100
1.5Vpp
Vop
10k
10k
+
22u
Signal
Vop
3.2Vpp
4.7k
Vop=VA=5V
0.1u BIAS
4.7k
+
10u
Same circuit
Figure 10. Differential Input Buffer Example
M0021-E-03
1999/12
- 17 -
ASAHI KASEI
[AK4523]
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the
supply voltage and nominally 0.58 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a
positive full scale for 7FFFFH(@20bit) and a negative full scale for 80000H(@20bit). The ideal output is VCOM voltage
for 00000H(@20bit). The internal switched-capacitor filter and continuous-time filter remove most of the noise generated
by the delta-sigma modulator of DAC beyond the audio passband.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. Figure 11
shows the example of external op-amp circuit with 6dB gain. The output signal is inverted by using the circuit in this case.
27u
AOUTL
2.9Vpp
10k
Vop=12V
Vop
4.7k
BIAS
10u +
18k
+
0.1u
Vop
+
10u
Lch Out
5.22Vpp
+
NJM5532
27k
4.7k
Rch Op-amp
Optional amp with 6dB gain
Figure 11. External analog circuit example (gain=6dB)
M0021-E-03
1999/12
- 18 -
ASAHI KASEI
[AK4523]
PACKAGE
28pin VSOP (Unit: mm)
*9.8±0.2
1.25±0.2
0.675
28
15
7.6±0.2
*5.6±0.2
A
14
1
+0.1
0.15-0.05
0.65
0.22±0.1
0.1±0.1
0.5±0.2
Detail A
0.10
1.0
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0-10°
n Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
M0021-E-03
1999/12
- 19 -
ASAHI KASEI
[AK4523]
MARKING
AKM
AK4523VF
XXXBYYYYC
XXXBYYYYC:
XXXB:
YYYYC:
data code identifier
Lot number (X: Digit number, B: Alpha character)
Assembly data (Y: Digit number, C: Alpha character)
IMPORTANT NOTICE
· These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
· AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
· Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
· AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
· It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
M0021-E-03
1999/12
- 20 -