Order this document by MC141543/D SEMICONDUCTOR TECHNICAL DATA P SUFFIX PLASTIC DIP CASE 648 CMOS The MC141543 is a high performance HCMOS device designed to interface with a microcontroller unit to allow colored symbols or characters to be displayed on a color monitor. The on–chip PLL allows both multi–system operation and self–generation of system timing. It also minimizes the MCU’s burden through its built–in 493 bytes RAM. By storing a full screen of data and control information, this device has a capability to carry out ‘screen–refresh’ without MCU supervision. Since there is no spacing between characters, special graphics–oriented characters can be generated by combining two or more character blocks. There are three different resolutions that users can choose. By changing the number of dots per horizontal line to 320 (CGA), 480 (EGA) or 640 (VGA), smaller characters with higher resolution can be easily achieved. Special functions such as character bordering or shadowing, multi–level windows, double height and double width, and programmable vertical length of character can also be incorporated. Furthermore, neither massive information update nor extremely high data transmission rate are expected for normal on– screen display operation, and serial protocols are implemented in lieu of any parallel formats to achieve minimum pin count. • Three Selectable Resolutions: 320 (CGA), 480 (EGA) or 640 (VGA) Dots per Line • Fully Programmable Character Array of 15 Rows by 30 Columns • 493 Bytes Direct Mapping Display RAM Architecture • Internal PLL Generates a Wide–Ranged System Clock • For High–End Monitor Application, Maximum Horizontal Frequency is 110 kHz (70.4 MHz Dot Clock at 640 Mode) • Programmable Vertical Height of Character to Meet Multi–Sync Requirement • Programmable Vertical and Horizontal Positioning for Display Center • 128 Characters and Graphic Symbols ROM (Mask ROM is Optional) • 10 x 16 Dot Matrix Character • Character–by–Character Color Selection • A Maximum of Four Selectable Colors per Row • Double Character Height and Double Character Width • Character Bordering or Shadowing • Three Fully Programmable Background Windows with Overlapping Capability • Provides a Clock Output Synchronous to the Incoming H Sync for External PWM • M_BUS (IIC) Interface with Address $7A • Single Positive 5 V Supply ORDERING INFORMATION MC141543P Plastic DIP PIN ASSIGNMENT VSS(A) 1 16 VSS VCO 2 15 R RP 3 14 G VDD(A) 4 13 B HFLB 5 12 SS 6 11 SDA(MOSI) 7 10 FBKG HTONE/ PWMCK VFLB SCL(SCK) 8 9 VDD REV 2 2/97 TN97022700 Motorola, Inc. 1997 MOTOROLA MC141543 1 BLOCK DIAGRAM 5 SDA(MOSI) SCL(SCK) SS 7 8 6 BSEN SHADOW OSD_EN VERD HORD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 8 8 54 DATA DATA RECEIVER MEMORY AND DATA MANAGEMENT 3 15 WCOLOR AND CONTROL 13 CCOLORS AND SELECT RA,CA,DA RFG MCLK BUS ARBITRATION LOGIC 26 RDATA 8 9 ADDRC Z 26 Y ROW BUFFER NROW VFLB CHS 4 10 VERD 8 CWS R VERTICAL CONTROL CIRCUIT CHS WADDR 6 CRS CRADDR 5 CH 4 HFLB 5 CHAR SC CCLK 54 WADDR BACKGROUND GENERATOR 13 COLOR ENCODER 15 WCOLOR AND CONTROL 16 14 R 15 MC141543 2 13 12 CCOLORS AND SELECT 11 HTONE/ PWMCK VSS 3 FBKG VDD 9 W B VSS(A) 1 OSD_EN 4 10–BIT SHIFT REGISTERS G VDD(A) CWS 10 HORD BSEN HORIZONTAL CONTROL AND PLL SHADOW 2 5 BLACKEDGE VCO 3 LUMINANCE RP CHARACTER ROMS DHOR MCLK LP MOTOROLA ABSOLUTE MAXIMUM RATINGS Voltage Referenced to VSS Characteristic Value Unit Supply Voltage – 0.3 to + 7.0 V Vin Input Voltage VSS – 0.3 to VDD + 0.3 V Id Current Drain per Pin Excluding VDD and VSS 25 mA Ta Operating Temperature Range 0 to 85 °C – 65 to + 150 °C Symbol VDD Tstg Storage Temperature Range This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. NOTE: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. AC ELECTRICAL CHARACTERISTICS (VDD = VDD(A) = 5.0 V, VSS = VSS(A) = 0 V, TA = 25°C, Voltage Referenced to VSS) Symbol tr tf FHFLB Min Typ Max Unit Output Signal (R, G, B, FBKG and HTONE/PWMCK) Cload = 30 pF, see Figure 1 Rise Time Fall Time Characteristic — — — — 6 6 ns ns HFLB Input Frequency — — 110 kHz DC CHARACTERISTICS VDD = VDD(A) = 5.0 V ± 10%, VSS = VSS(A) = 0 V, TA = 25°C, Voltage Referenced to VSS Symbol Characteristic Min Typ Max Unit VOH High Level Output Voltage Iout = – 5 mA VDD – 0.8 — — V VOL Low Level Output Voltage Iout = 5 mA — — VSS + 0.4 V VIL VIH Digital Input Voltage (Not Including SDA and SCL) Logic Low Logic High — 0.7 VDD — — 0.3 VDD — V V VIL VIH Input Voltage of Pin SDA and SCL in SPI Mode Logic Low Logic High — 0.7 VDD — — 0.3 VDD — V V VIL VIH Input Voltage of Pin SDA and SCL in M_BUS Mode Logic Low Logic High — 0.7 VDD — — 0.3 VDD — V V III High–Z Leakage Current (R, G, B and FBKG) – 10 — + 10 µA III Input Current (Not Including RP, VCO, R, G, B, FBKG and HTONE/PWMCK) – 10 — + 10 µA — — + 15 mA IDD Supply Current (No Load on Any Output) 90% 90% 10% tf 10% tr Figure 1. Switching Characteristics MOTOROLA MC141543 3 PIN DESCRIPTIONS VFLB (Pin 10) VSS(A) (Pin 1) Similar to Pin 5, this pin inputs a negative polarity vertical synchronize signal pulse. This pin provides the signal ground to the PLL circuitry. Analog ground for PLL operation is separated from digital ground for optimal performance. HTONE/PWMCK (Pin 11) VCO (Pin 2) Pin 2 is a control voltage input to regulate an internal oscillator frequency. See the Application Diagram for the application values used. RP (Pin 3) An external RC network is used to bias an internal VCO to resonate at the specific dot frequency. The maximum voltage at Pin 3 should not exceed 3.5 V at any condition. See the Application Diagram for the application values used. VDD(A) (Pin 4) Pin 4 is a positive 5 V supply for PLL circuitry. Analog power for PLL is separated from digital power for optimal performance. HFLB (Pin 5) This pin inputs a negative polarity horizontal synchronize signal pulse to phase lock an internal system clock generated by the on–chip VCO circuit. SS (Pin 6) This input pin is part of the SPI serial interface. An active low signal generated by the master device enables this slave device to accept data. This pin should be pulled high to terminate the SPI communication. If M_BUS is employed as the serial interface, this pin should be tied to either VDD or VSS. This is a multiplexed pin. When the PWMCK_EN bit is cleared after power–on or by the MCU, this pin is HTONE and outputs a logic high during windowing except when graphics or characters are being displayed. It is used to lower the external R, G, and B amplifiers’ gain to achieve a transparent windowing effect. If the PWMCK_EN bit is set to 1 via M_BUS or SPI, this pin is changed to a mode–dependent clock output with 50/50 duty cycle and is synchronous with the input horizontal synchronization signal at Pin 5. The frequency is dependent on the mode in which the AMOSD is currently running. The exact frequencies in the different resolution modes are described in Table 1. ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Table 1. PWM CLK Frequency Resolution Frequency Duty Cycle 320 dots/line 32 x Hf 50/50 480 dots/line 48 x Hf 50/50 640 dots/line 64 x Hf 50/50 NOTE: Hf is the frequency of the input H sync on Pin 5. Typically, this clock is fed into an external pulse width modulation module as its clock source. Because of the synchronization between PWM clock and H sync, a better performance on the PWM controlled functions can be achieved. FBKG (Pin 12) Data and control messages are being transmitted to this chip from a host MCU via one of the two serial bus systems. With either protocol, this wire is configured as a uni–directional data line. (Detailed description of these two protocols will be discussed in the M_BUS and SPI sections). This pin outputs a logic high while displaying characters or windows when the FBKGC bit in the frame control register is 0, and output a logic high only while displaying characters when the FBKGC bit is 1. It is defaulted to high–impedance state after power–on, or when there is no output. An external 10 kΩ resistor pulled low is recommended to avoid level toggling caused by hand effect when there is no output. SCL (SCK) (Pin 8) B,G,R (Pins 13,14,15) A separate synchronizing clock input from the transmitter is required for either protocol. Data is read at the rising edge of each clock signal. AMOSD color output is TTL level RGB to the host monitor. These three signals are active high output pins that are in a high–impedance state when AMOSD is disabled. VDD (Pin 9) VSS (Pin 16) SDA (MOSI) (Pin 7) This is the power pin for the digital logic of the chip. MC141543 4 This is the ground pin for the digital logic of the chip. MOTOROLA SYSTEM DESCRIPTION MC141543 is a full–screen memory architecture. Refresh is performed by the built–in circuitry after a screenful of display data has been loaded through the serial bus. Only changes to the display data need to be input afterward. Serial data, which includes screen mapping address, display information, and control messages, are transmitted via one of the two serial buses: M_BUS or SPI (mask option). These two sets of buses are multiplexed onto a single set of wires. Standard parts offer M_BUS transmission. Data is received from the serial port and stored by the memory management circuit. Line data is stored in a row buffer for display and refreshing. During this storing and retrieving cycle, bus arbitration logic patrols the internal traffic to make sure that no crashes occur between the slower serial bus receiver and the fast ‘screen–refresh’ circuitry. After the full–screen display data is received through one of the serial communication interfaces, the link can be terminated if a change of the display is not required. The bottom half of the block diagram contains the hardware functions for the entire system. It performs all the AMOSD functions such as programmable vertical length (from 16 lines to 63 lines), display clock generation (which is phase locked to the incoming horizontal sync signal at Pin 5 HFLB), bordering or shadowing, and multiple windowing. COMMUNICATION PROTOCOLS M_BUS Serial Communication This is a two–wire serial communication link that is fully compatible with the IIC bus system. It consists of an SDA bidirectional data line and an SCL clock input line. Data is sent from a transmitter (master) to a receiver (slave) via the SDA line, and is synchronized with a transmitter clock on the SCL line at the receiving end. The maximum data rate is limited to 100 kbps and the default chip address is $7A. Operating Procedure Figure 2 shows the M_BUS transmission format. The master initiates a transmission routine by generating a start condition followed by a slave address byte. Once the address is properly identified, the slave will respond with an acknowledge signal by pulling the SDA line low during the ninth SCL clock. Each data byte that follows must be eight bits long, plus the acknowledge bit, for a total of nine bits. Appropriate row and column address information and display data can be downloaded sequentially in one of the three transmission formats described in the Data Transmission Formats section. In the cases of no acknowlege or completion of data transfer, the master will generate a stop condition to terminate the transmission routine. Note that the OSD_EN bit must be set after all the display information has been sent, in order to activate the AMOSD circuitry of MC141543 so that the received information can be displayed. MOTOROLA DATA BYTES CHIP ADDRESS SDA ACK ACK SCL 1 2–7 8 9 STOP CONDITION START CONDITION Figure 2. M_BUS Format DATA TRANSMISSION FORMATS After the proper identification by the receiving device, a data train of arbitrary length is transmitted from the master. There are three transmission formats from (a) to (c) as stated below. The data train in each sequence consists of row address (R), column address (C), and display information (I), as shown in Figure 3. In format (a), display information data must be preceded with the corresponding row address and column address. This format is particularly suitable for updating small amounts of data between different rows. However, if the current information byte has the same row address as the one before, format (b) is recommended. ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ row addr col addr info Figure 3. Data Packet For a full–screen pattern change that requires a massive information update, or during power–up, most of the row and column addresses of either (a) or (b) formats will be consecutive. Therefore, a more efficient data transmission format (c) should be applied. This sends the RAM starting row and column addresses once only, and then treats all subsequent data as display information. The row and column addresses will be automatically incremented internally for each display information data from the starting location. The data transmission formats are: (a) R – > C – > I – > R – > C – > I – > . . . . . . . . . (b) R – > C – > I – > C – > I – > C – > I. . . . . . . (c) R – > C – > I – > I – > I – > . . . . . . . . . . . . . To differentiate the row and column addresses when transferring data from master, the MSB (most significant bit) is set, as in Figure 4: ‘1’ to represent row, and ‘0’ for column address. Furthermore, to distinguish the column address between formats (a), (b), and (c), the sixth bit of the column address is set to ‘1’ which represents format (c), and ‘0’ for format (a) or (b). However, there is some limitation on using mixed formats during a single transmission. It is permissible to change the format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b). MC141543 5 5 X BIT 4 X 3 D 2 D 1 D 0 D COLUMN COLUMN 0 0 0 1 X X D D D D D D D D D D X: don’t care FORMAT a, b, c a, b c D: valid data Figure 4. Row & Column Address Bit Patterns MEMORY MANAGEMENT Internal RAM is addressed with row and column (coln) numbers in sequence. The spaces between Row 0 and Coln 0 to Row 14 and Coln 29 are called display registers, and each contains a character ROM address corresponding to a display location on the monitor screen. Every data row is associated with two control registers, which are located at Coln 30 and 31 of their respective rows, to control the character display format of that row. In addition, three window control registers for each of the three windows, together with three frame control registers, occupy the first 13 columns of Row 15. The user should handle the internal RAM address location with care, especially those rows with double length alphanumeric symbols. For example, if Row n is destined to be double height on the memory map, the data displayed on screen Rows n and n+1 will be represented by the data contained in the memory address of Row n only. The data of the MC141543 6 next Row n+1 on the memory map will appear on the screen as n+2 and n+3 row space, and so on. Hence, it is not necessary to load a row of blank data to compensate for the double row. The user should minimize excessive rows of data in memory in order to avoid overrunning the limited amount of row space on the screen. For rows with double width alphanumeric symbols, only the data contained in the even numbered columns of the memory map are shown. Odd numbered columns are treated in the same manner as double height rows. 0 14 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 27 28 29 30 31 DISPLAY REGISTERS 0 15 COLUMN 0 ROW CONTROL REGISTERS ROW 6 X ROW ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ 7 1 ADDRESS 2 3 5 6 8 9 WINDOW 1 WINDOW 2 WINDOW 3 12 FRAME CRTL REG WINDOW AND FRAME CONTROL REGISTERS Figure 5. Memory Map MOTOROLA REGISTERS Display Register ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ 7 6 5 4 3 2 1 0 CCS0 CRADDR Bit 7 CCS0 — This bit defines a specific character color out of the two preset colors. Color 1 is selected if this bit is cleared, and Color 2 otherwise. Bit 6–0 CRADDR — These seven bits address the 128 characters or symbols residing in the character ROM. Bits 2–0 R, G and B — These bits control the color of Window 1. Window 1 occupies Columns 0–2 of Row 15; Window 2 occupies Columns 3–5; and Window 3 occupies Columns 6–8. Window 1 has the highest priority, and Window 3 the least. If window overlapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap window area. If the start address is greater than the end address, this window will not be displayed. Window 2 Registers Row 15 Coln 3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Row Control Registers 7 Coln 30 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN 30 7 6 5 4 3 2 1 0 R1 G1 B1 R2 G2 B2 CHS CWS Bits 7–2 — Color 1 is determined by R1, G1, and B1; Color 2 by R2, G2, and B2. Bit 1 CHS — This bit determines the height of a display symbol. When it is set, the symbol is displayed in double height. Bit 0 CWS — Bit 0 is similar to Bit 1; when this bit is set, the character is displayed in double width. Coln 31 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ COLN 31 7 6 5 4 3 2 1 R3 G3 B3 R4 G4 B4 ROW 15 COLN 3 6 5 4 ROW START ADDR MSB 2 1 ROW END ADDR LSB MSB 0 LSB Row 15 Coln 4 7 ROW 15 COLN 4 6 MSB 5 4 3 COL START ADDR 2 1 LSB WEN 0 CCS1 Bit 2 WEN — This bit enables the background Window 2 generation when it is set. Bit 1 CCS1 — This additional color select bit provides the characters residing within Window 2 with two extra color selections, making a total of four selections for that row. 0 Bits 7–2 — Color 3 is determined by R3, G3, and B3; Color 4 by R4, G4, and B4. 3 Row 15 Coln 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 7 ROW 15 COLN 5 MSB 6 5 COL END ADDR 4 3 2 1 0 LSB R G B Window 1 Registers Row 15 Coln 0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 7 ROW 15 COLN 0 6 5 4 3 2 1 ROW START ADDR ROW END ADDR LSB MSB MSB 0 LSB Row 15 Coln 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 7 ROW 15 COLN 1 6 MSB 5 4 COL START ADDR 3 2 1 LSB WEN CCS1 0 Bit 2 WEN — This bit enables the background Window 1 generation when it is set. Bit 1 CCS1 — This additional color select bit provides the characters residing within Window 1 with two extra color selections, making a total of four selections for that row. Bit 2–0 R, G and B — These bits control the color of Window 2. Window 1 occupies Columns 0–2 of Row 15; Window 2 occupies Columns 3–5; and Window 3 occupies Columns 6–8. Window 1 has the highest priority, and Window 3 the least. If window overlapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap window area. If the start address is greater than the end address, this window will not be displayed. Window 3 Registers ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Row 15 Coln 6 7 ROW 15 COLN 6 MSB ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 7 ROW 15 COLN 2 6 5 4 COL END ADDR MSB MOTOROLA 3 2 1 0 LSB R G B 3 2 1 ROW END ADDR 0 LSB LSB MSB Row 15 Coln 7 7 Row 15 Coln 2 6 5 4 ROW START ADDR ROW 15 COLN 7 MSB 6 5 4 COL START ADDR 3 LSB 2 1 0 WEN CCS1 PWMCK_EN Bit 2 WEN — This bit enables the background Window 3 generation when it is set. MC141543 7 Bit 1 CCS1 — This additional color select bit provides the characters residing within Window 3 with two extra color selections, making a total of four selections for that row. Bit 0 PWMCK_EN — When this bit is set to 1, the HTONE/ PWMCK pin will be switched to a clock output which is synchronous to the H sync and used as an external PWM (pulse width modulation) clock source. Refer to the pin description of HTONE/PWMCK for more information. After power–on, the default value is 0. Row 15 Coln 8 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ 7 ROW 15 COLN 8 MSB 6 5 4 COL END ADDR 3 2 1 0 R G B LSB Bit 2–0 R, G and B — These bits control the color of Window 3. Window 1 occupies Columns 0–2 of Row 15; Window 2 occupies Columns 3–5; and Window 3 occupies 6–8. Window 1 has the highest priority, and Window 3 the least. If window overlapping occurs, the higher priority window will cover the lower one, and the higher priority color will take over on the overlap window area. If the start address is greater than the end address, this window will not be displayed. Frame Control Register Row 15 Coln 12 ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ 6 7 5 4 3 2 0 1 FBKGC COLN 12 OSD_EN BSEN SHADOW X64 X32B Bit 7 OSD_EN — The OSD circuit is activated when this bit is set. Bit 6 BSEN — This bit enables the character bordering or shadowing function when it is set. Bit 5 SHADOW — Characters with black–edge shadowing are selected if this bit is set; otherwise bordering prevails. Bit 4 X64, Bit 3 X32B — This bit determines the number of dots per horizontal line. There are 320 dots per horizontal line if Bit X32B is clear, which is also the default power–on state. Otherwise, 480 dots per horizontal sync line is chosen when Bit X64 is clear, and 640 dots per horizontal sync line when Bit X64 is set to 1. Refer to Table 2 for details. Bit 0 FBKGC — Bit 0 determines the configuration of the FBKG output pin. When it is clear, the FBKG pin outputs high while displaying characters or windows; otherwise, the FBKG pin outputs high only while displaying characters. ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ Frame Control Registers Frame Control Register Row 15 Coln 9 7 6 5 COLN 9 4 3 VERTD 2 1 (0,0) (1,0) (0,1) (1,1) Dots / Line 320 320 480 640 Resolution CGA CGA EGA VGA LSB Bit 7–0 VERTD — These eight bits define the vertical starting position. There are a total of 256 steps, with an increment of four horizontal lines per step for each field. The value cannot be zero anytime, and the default value is 4. Frame Control Register Row 15 Coln 10 COLN 10 (X64, X32B) 0 MSB 7 Table 2. Resolution Setting 6 5 4 3 2 1 0 HORD MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 lines Built–in font (10x16 matrix) when CH=16 Bit 6–0 HORD — These bits define the horizontal starting position for character display. Seven bits give a total of 128 steps and each increment represents a five–dot shift to the right on the monitor screen. The value cannot be zero anytime, the default value is 15. 22 lines Display character when CH=22 25 lines 34 lines Frame Control Register Row 15 Coln 11 7 COLN 11 6 5 4 3 CH5 CH4 CH3 2 CH2 1 0 CH1 CH0 Bit 5–0 CH5–CH0 — These six bits determine the displayed character height. It is possible to have a proper character height by setting a value greater than or equal to 16 on a different horizontal frequency monitor. Setting a value below 16 will not have a predictable result. Figure 6 illustrates how this chip expands the built–in character font to the desired height. MC141543 8 Display character when CH=25 Display character when CH=34 Figure 6. Variable Character Height An IBM PC program called “AMOSD Font Editor” was written for MC141543 editing purposes. This program generates a set of S–Record or Binary record for the desired display patterns to be masked onto the character ROM of the MC141543. MOTOROLA vertical delay = VERTD x 4 + 1 H scan lines MOTOROLA area not interfered by display characters display character CH5–0 = 0x21 & double height CH5–0 = 0x21 & double width col 28 col 14 . . . . . . . . . . . . . . . . Display Frame Format col 12 col 10 col 8 col 6 col 4 col 2 14 6 5 ...... HFLB Figure 8 illustrates the positions of all display characters on the screen relative to the leading edge of horizontal and vertical flyback signals. The shaded area indicates the area outside “safe viewing area” for the display characters. Notice that there are two components in the equations stated in Figure 8 for horizontal and vertical delays: fixed delays from the leading edge of HFLB and VFLB signals, regardless of the values of HORD and VERTD (47 dots + phase detection pulse width) and one H scan line for horizontal and vertical delays, respectively; and variable delays determined by the values of HORD and VERTD. Refer to Frame Control Registers Coln 9 and 10 for the definitions of VERTD and HORD. Phase detection pulse width is a function of the external charge–up resistor, which is the 330 kΩ resistor in a series with 2 kΩ to VCO pin in the Application Diagram. Dot frequency is determined by the equation H freq x 320 if Bit X32B is clear, and H freq x 480 if Bit X32B is set to 1 and Bit X64 is 0, and H freq x 640 if both Bit X32B and Bit X64 are set to 1. For example, dot frequency is 10.24 MHz if H freq is 32 kHz while Bit X32B is 0. If Bit X32B is 1 and Bit X64 is 0, the dot frequency will be 15.36 MHz (one and a half of the original one). If Bit X32B is 1 and Bit X64 is also 1, the dot frequency will be 20.48 MHz (double of the original one). HFLB Frame Format and Timing col 0 Figure 7. Character Bordering and Shadowing double width standard size 10x16 double height 26 27 28 29 Shadowing 1 Bordering ÎÎÎÎÎ ÏÏ ÏÏ ÏÏ ÏÏ ÎÎÎÎÎ ÏÏ ÏÏ ÏÏ ÏÏ ÎÎÎÎÎ ÏÏ ÏÏ ÏÏ ÏÏ ÎÎÎÎÎ ÏÏ ÏÏ ÏÏ ÏÏ ÎÎÎÎÎ ÏÏ ÎÎÎÎÎ ÏÏ ÎÎÎÎÎ ÏÏ ÎÎÎÎÎ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 horizontal delay = (HORD x 5 + 47) dots + phase detection pulse width COLUMN 0 1 2 3 ROW 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎ ÎÎÎÎÎÎÎÎÎÎÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎ ÎÎÎÎÎÎÎÎÎÎÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏ 10x30 dots fixed ÎÎÎÎÎÎ ÏÏ ÏÏ Ï ÏÏ ÏÏ ÎÎÎÎÎÎ ÏÏ ÏÏÏÏ ÏÏ ÎÎÎÎÎÎ ÏÏ ÏÏÏ ÏÏ ÎÎÎÎÎÎ ÏÏ ÏÏ ÏÏ Ï ÎÎÎÎÎÎ ÏÏ ÎÎÎÎÎÎ ÏÏ ÎÎÎÎÎÎ ÏÏ ÎÎÎÎÎÎ variable number of H scan lines VFLB 2 3 4 In order to have better character display within windows, it is suggested that the designed character font be placed in the center of the 10 x 16 matrix with equal space on all four sides. The character $00 is predefined for blank characters, the character $7F is predefined for full–filled characters, and the character $7E is a random dot pattern reserved for testing. In order to avoid submersion of displayed symbols or characters into a background of comparable colors, a feature of bordering which encircles all four sides, or shadowing which encircles only the right and bottom sides of an individual display character, are provided. Figure 7 shows how a character is jacketed differently. To make sure that a character is bordered or shadowed correctly, at least one blank dot should be reserved on each side of the character font. Figure 8. Display Frame Format When double character width is selected for a row, only the even–numbered characters will be displayed, as shown in Row 2. Notice that the total number of horizontal scan lines in the display frame is variable, depending on the chosen character height of each row. Care should be taken while configuring each row character height so that the last horizontal scan line in the display frame always comes out before the leading edge of VFLB of the next frame, to avoid wrapping display characters of the last few rows in the current frame into the next frame. The number of display dots in a horizontal scan line is always fixed at 300, regardless of row character width and the setting of Bits X32B and X64. MC141543 9 Although there are 30 character display registers that can be programmed for each row, not every programmed character can be shown on the screen in 320–dot resolution. Usually only 24 characters can be shown in this resolution at most. This is induced by the time that is required to retrace the H scan line. In other resolutions, 480–dot and 640–dot, a total of 30 characters can be displayed on the screen if the horizontal delay register is set properly. Figure 9 illustrates the timing of all output signals as a function of window and fast–blanking features. Line 3 of all three characters is used to illustrate the timing signals. The shaded area depicts the window area. The characters on the left and right appear identical except for the FBKGC bit. The middle character does not have a window as its background. Notice that signal HTONE/PWMCK is active only in the window area. Timing of the signal FBKG depends on the configuration of the FBKGC bit. The configuration of the FBKGC bit affects only the FBKG signal timing; it has no effect on the timing of HTONE/PWMCK. Waveform ‘R, G, or B’, which is the actual waveform at R, G, or B pin, is the logical OR of waveform ‘character R, G, or B’ and waveform ‘window R, G, or B’. ‘Character R, G, or B’ and ‘window R, G, or B’ are internal signals for illustration purpose only. Also notice that HTONE/PWMCK has exactly the same waveform as ‘window R, G, or B’. Character Inside a Window Character Outside a Window Character Inside a Window FBKGC Bit = 1 FBKGC Bit = 0 ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ 3 Line 3 R, G, or B Window R, G, or B Character R, G, or B FBKG HTONE/PWMCK ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌ Figure 9. Timing of Output Signals as a Function of Window and FBKGC Bit Features MC141543 10 FONT Icon Combination MC141543 contains 128–character ROM. The user can create an on–screen menu based on those characters and icons. Refer to Table 3 for icon combinations. Addresses $00 and $7F are predefined characters, and $7E is for testing. They cannot be modified in any AMOSDs. ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Table 3. Combination Map ICON ROM ADDRESS (HEX) Volume Bar I 01, 02, 03, 04, 05, 06, 4A Volume Bar II 48, 49, 57 Volume Bar III 47 Size 4F, 50 Position 51, 52 Geometry 53, 54, 55, 56 Contrast 58,59 Brightness 5A, 5B Horizontal Position 5C, 5D Horizontal Sizing 5E, 5F Vertical Position 60, 61 Vertical Sizing 62, 63 Pin Cushion 64, 65 Deguassing 66, 67 Video Mode 68, 69 Trapezoid 6A, 6B Parallelogram 6C, 6D Rotation 6E, 6F Color Select 70, 71 Video Level 72, 73 Input Select 74, 75 Recall 76,77 Save 78, 79 Left/Right Arrows 7A, 7B INC/DEC sign 7C, 7D Speaker 07, 08 ROM CONTENT Figures 10 – 13 show the ROM content of MC141543. Mask ROM is optional for custom parts. MOTOROLA Figure 10. ROM Address ($00 – $1F) MOTOROLA Figure 11. ROM Address ($20 – $3F) MC141543 11 Figure 12. ROM Address ($40 – $5F) MC141543 12 Figure 13. ROM Address ($60 – $7F) MOTOROLA DESIGN CONSIDERATIONS • Distortion • Motorola’s MC141543P has a built–in PLL for multi–system application. Pin 2 voltage is dc–based for the internal VCO in the PLL. When the input frequency (HFLB) to Pin 5 increases, the VCO frequency will increase accordingly. This forces the PLL to a higher locked frequency output. The frequency should be equal to 320/480/640 x HFLB (depending on resolution). This is the pixel dot clock. Display distortion is caused by noise on Pin 2. Positive noise increases the VCO frequency above normal. The corresponding scan line will be shorter accordingly. In contrast, negative noise causes the scan line to be longer. The net result will be distortion on the display, especially on the right hand side of the display window. In order to have distortion–free display, the following recommendations should be considered: • Only analog part grounds (Pin 2 to Pin 4) can be connected to Pin 1(VSS(A)). VSS and other grounds should be connected to PCB common ground. The VSS(A) and VSS grounds should be totally separated (i.e. VSS(A) is floating). Refer to the Application Diagram for the ground connections. • • The dc supply path for Pin 9 (VDD) should be separated from other switching devices. The LC filter should be connected between Pin 9 and Pin 4. Refer to the values used in the Application Diagram. Biasing and filter networks should be connected to Pin 2 and Pin 3. Refer to the recommended networks in the Application Diagram. Two small capacitors can be connected between Pins 2 and 3, and between Pins 3 and 4. Jittering Most display jittering is caused by HFLB jittering on Pin 5. Care must be taken if the HFLB signal comes from the flyback transformer. A short path and shielded cable are recommended for a clean signal. A small capacitor can be added between Pin 5 and Pin 16 to smooth the signal. Refer to the value used in the Application Diagram. Display Dancing Most display dancing is caused by interference of the serial bus. It can be avoided by adding series resistors to the serial bus. APPLICATION DIAGRAM VCC ANALOG GROUND – FLOATING 0.1 µF 100 µH 100 µF 1 2k 3.3 k 330 pF 0.01 µF 2k 0.047 µF 33 pF 330 k 33 pF 2 3 4 5 HFLB 330 pF IIC(SPI) BUS 100 100 100 VSS(A) VDD 9 VCO VSS 16 RP R VDD(A) G HFLB B 10 µF 15 1k 14 1k 13 1k 0.1 VCC µF 7 8 SS SDA(MOSI) 100 240 100 240 100 R G B MPS2369 AMOSD 6 240 FBKG 12 HTONE 11 FBKG HTONE ANALOG GROUND SCL(SCK) VFLB 10 VFLB DIGITAL GROUND DIGITAL GROUND – COMMON GROUND MOTOROLA MC141543 13 PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP CASE 648–08 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET: http://www.mot.com/SPS/ MC141543 14 ◊ MC141543/D MOTOROLA