NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 3A ULTRA LOW DROPOUT LINEAR REGULATOR WITH ENABLE Description Pin Assignments (Top View) The AP7175 is a 3.0A ultra low-dropout (LDO) linear regulator that features an enable input and a power-good output. The enable input and power-good output allow users to configure power management solutions that can meet the sequencing requirements of FPGAs, DSPs, and other applications with different start-up and power-down requirements. The AP7175 features two supply inputs, for power conversion supply and control. With the separation of the control and the power input very low dropout voltages can be reached and power dissipation is reduced. GND 1 8 EN FB 2 7 PG VOUT 3 6 VCNTL VOUT 4 5 VIN SO-8EP (Top View) A precision reference and feedback control deliver 1.5% accuracy over load, line, and operating temperature ranges. GND 1 8 EN FB 2 7 PG VOUT 3 6 VCNTL VOUT 4 5 VIN MSOP-8EP The AP7175 is available in SO-8EP and MSOP-8EP package with an exposed PAD to reduce the junction to case resistance and extend the temperature range it can be used in. Features Applications VIN Range: 1.2V to 3.65V VCNTL 3.0V to 5.5V Adjustable output voltage Continuous Output Current IOUT = 3A Fast transient response Power on reset monitoring on VCNTL and VIN Internal Softstart Stable with Low ESR MLCC Capacitors Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) Notes: = PAD (connected to VIN) Notebook PC Netbook Wireless Communication Server Motherboard Dongle Front Side Bus VTT (1.2V/3.3A) 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. Typical Applications Circuit VOUT PG R3 5.1KΩ R1 12KΩ VCNTL CCNTL 1µF VIN FB R2 24KΩ AP7175 C1 *Optional COUT 10µF CIN 10µF ON OFF EN GND Figure 1. Typical Application Circuit AP7175 Document number: DS35606 Rev. 4 - 3 1 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Pin Descriptions Pin Name Pin Number SO-8EP MSOP-8EP Function GND 1 1 Ground FB 2 2 VOUT 3/4 3/4 VIN 5 5 VCNTL 6 6 Feedback to set the output voltage via an external resistor divider between V OUT and GND. Power Output Pin. Connect at least 10µF capacitor to this pin to improve transient response and required for stability. When the part is disabled the output is discharged via an internal pull-low MOSFET. Power Input Pin for current supply. Connect a decoupling capacitor (≥10µF) as close as possible to the pin for noise filtering. BIAS supply for the controller, recommended 5V. Connect a decoupling capacitor (≥1µF) as close as possible to the pin for noise filtering. PG 7 7 EN 8 8 PAD EP EP Power Good output open drain to indicate the status of VOUT via monitoring the FB pin. This pin is pulled low when the voltage is outside the limits, during thermal shutdown and if either V CNTL or VIN go below their thresholds. Enable pin. Driving this pin low will disable the part. When left floating an internal current source will pull this pin high and enable it. Exposed pad connect this to VIN for good thermal conductivity. Functional Block Diagram VIN Power On Reset (POR) VCNTL 5µA Thermal Shutdown EN Control Logic SoftStart 0.8V Ref Error Amp 0.8V Ref VOUT Current Limit and Short Circuit FB GND PG Delay 90%VRef POR AP7175 Document number: DS35606 Rev. 4 - 3 2 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Absolute Maximum Ratings (Note 4) (@TA = +25°C, unless otherwise specified.) Symbol Rating Unit VIN Supply Voltage (VIN to GND) -0.3 to +4.0 V VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 to +7.0 V VOUT VOUT to GND Voltage -0.3 to VIN +0.3 V -0.3 to +7.0 V VIN Parameter — PG to GND Voltage — EN, FB to GND Voltage -0.3 to VCNTL +0.3 V PD Power Dissipation (SO-8EP) Power Dissipation (MSOP-8EP) 1.7 1.5 W W TJ Maximum Junction Temperature +150 °C -65 to +150 °C +260 °C TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds Note: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time. Recommended Operating Conditions (@TA = +25°C, unless otherwise specified.) Symbol Parameter Min Max Unit VCNTL Supply Voltage 3.0 5.5 V VIN Supply Voltage 1.2 3.65 V VOUT VOUT Output Voltage (when VCNTL-VOUT >1.9V) 0.8 VIN - VDROP V Continuous Current 0 3 IOUT VOUT Output Current Peak Current 0 4 IOUT = 3A at 25% nominal VOUT 8 1100 COUT VOUT Output Capacitance IOUT = 2A at 25% nominal VOUT 8 1700 IOUT = 1A at 25% nominal VOUT 8 2400 VCNTL VIN A µF 0 200 mΩ TA Ambient Temperature -40 +85 °C TJ Junction Temperature -40 +125 °C ESRCOUT ESR of VOUT Output Capacitor AP7175 Document number: DS35606 Rev. 4 - 3 3 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Electrical Characteristics (VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40 to +85°C, @TA = +25°C, unless otherwise specified.) Symbol Parameter Test Conditions Min AP7175 Typ Max Unit SUPPLY CURRENT VCNTL Supply Current EN = VCNTL, IOUT=0A — 1.0 1.5 mA ISD VCNTL Supply Current at Shutdown EN = GND — 15 30 µA — VIN Supply Current at Shutdown EN = GND, VIN=3.65V — — 1 µA IVCNTL POWER-ON-RESET (POR) — Rising VCNTL POR Threshold — 2.5 2.7 2.95 V — VCNTL POR Hysteresis — — 0.4 — V — Rising VIN POR Threshold — 0.8 0.9 1.0 V — — 0.5 — V Reference Voltage FB = VOUT — 0.8 — V Output Voltage Accuracy VCNTL =3.0 V to 5.5V, IOUT = 0 to 3A, TJ = -40 to +125°C -1.5 — +1.5 % Load Regulation IOUT =0A to 3A — 0.06 0.25 % Line Regulation IOUT =10mA, VCNTL = 3.0 to 5.5V -0.15 — +0.15 %/V VOUT Pull-low Resistance VCNTL = 3.3V, VEN = 0V, VOUT < 0.8V — 10 — Ω FB Input Current VFB = 0.8V -100 — 100 nA TJ = +25°C — 0.26 0.31 TJ = -40 to +125°C — — 0.42 TJ = +25°C — 0.24 0.29 TJ = -40 to +125°C — — 0.40 TJ = +25°C — 0.23 0.28 — VIN POR Hysteresis OUTPUT VOLTAGE VREF DROPOUT VOLTAGE VOUT = 2.5V VDROP VIN-to-VOUT Dropout Voltage (Note 5) VCNTL = 5.0V, VOUT = 1.8V IOUT = 3A VOUT = 1.2V ILIM V — — 0.38 TJ = +25°C, VOUT = 80% VNOMINAL 4.5 5.7 6.7 A TJ = -40 to +125°C 4.2 — — A Short Current-Limit Level VFB < 0.2V — 1.1 — A Thermal Shutdown Temperature TJ rising — +170 — °C Thermal Shutdown Hysteresis — — +50 — °C Current-Limit Level TJ = -40 to +125°C PROTECTIONS ISHORT TSD — ENABLE AND SOFT-START — EN Logic High Threshold Voltage VEN rising 0.5 0.8 1.1 V — — EN Hysteresis EN Pull-High Current — EN = GND — — 0.1 5 — — V µA tSS Soft-Start Interval — 0.3 0.6 1.2 ms — Turn On Delay From being enabled to VOUT rising 10% 200 350 500 µs Rising PG Threshold Voltage VFB rising 90 92 95 % — PG Threshold Hysteresis — — 8 — % — PG Pull-low Voltage PG sinks 5mA — 0.25 0.4 V — PG Debounce Interval VFB < falling PG voltage threshold — 10 — µs — PG Delay Time From VFB = VTHPG to rising edge of the VPG 1 2 4 ms POWER-GOOD AND DELAY VTHPG Note: 5. Dropout voltage is the voltage difference between the inut and the output at which the output voltage drops 2% below its nominal value. AP7175 Document number: DS35606 Rev. 4 - 3 4 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Electrical Characteristics (Cont.) (VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V and TA = -40 to +85°C, @TA = +25°C, unless otherwise specified.) Symbol Parameter Min AP7175 Typ Max SO-8EP (Note 6) — 70 — C/W MSOP-8EP (Note 7) — 80 — C/W SO-8EP (Note 6) — 30 — C/W MSOP-8EP (Note 7) — 30 — C/W Test Conditions Unit THERMAL CHARACTERISTIC θJA θJC Notes: Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Case 6. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and thermal vias to bottom layer ground plane. 7. Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. Typical Characteristics AP7175 Document number: DS35606 Rev. 4 - 3 5 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Typical Characteristics (Cont.) AP7175 Document number: DS35606 Rev. 4 - 3 6 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Operating Waveforms (@ VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V, TA = +25°C, unless otherwise specified.) Power On Power Off VCNTL VCNTL VIN VIN VOUT VOUT VPOK VPOK COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 2ms/Div COUT=10µF, CIN=10µF, RL=0.4Ω CH1: VCNTL, 5V/Div, DC CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC CH4: VPOK, 5V/Div, DC TIME: 2ms/Div Load Transient Response Over Current Protection VOUT VOUT IOUT IOUT IOUT = 10mA to 3A to10mA (rise / fall time =1µs) COUT = 10µF, CIN = 10µF CH1: VOUT, 50mV/Div, AC CH2: IOUT, 1A/Div, DC TIME: 50µs/Div AP7175 Document number: DS35606 Rev. 4 - 3 COUT = 10µF, CIN = 10µF, IOUT = 2A to 5.6A CH1: VOUT, 0.5V/Div, DC CH2: IOUT, 2A/Div, DC TIME: 0.2ms/Div 7 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Operating Waveforms (Cont.) (@ VCNTL = 5V, VIN = 1.8V, VOUT = 1.2V, TA = +25°C, unless otherwise specified.) Shutdown Enable VEN VEN VOUT VOUT VPOK VPOK IOUT IOUT COUT = 10µF, CIN = 10µF, RL = 0.4Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 4µs/Div AP7175 Document number: DS35606 Rev. 4 - 3 COUT = 10µF, CIN = 10µF, RL = 0.4Ω CH1: VEN, 5V/Div, DC CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC CH4: IOUT, 2A/Div, DC TIME: 1ms/Div 8 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Application Information Power Good and Delay AP7175 monitors the feedback voltage VFB on the FB pin. An internal delay timer is started after the PG voltage threshold (VTHPG) on the FB pin is reached. At the end of the delay time an internal NMOS of the PG is turned off to indicate that the power at the output is good (PG). This monitoring function is continued during operation and if VFB falls 8% (typ) below VTHPG, the NMOS of the PG is turned on after a delay time of typical 10µs to avoid oscillating of the PG signal. Power On Reset AP7175 monitors both supply voltages, VCNTL and VIN to ensure operation as intended. A Soft-Start process is initiated after both voltages exceed their POR threshold during power on. During operation the POR component continues to monitor the supply voltage and pulls the PG low to indicate an out of regulation supply. This function will engage without regard to the status of the output. Soft-Start AP7175 incorporates an internal Soft-Start function. The output voltage rise is controlled to limit the current surge during start-up. The typical Soft-Start time is 0.6ms. Current-Limit Protection AP7175 monitors the current flow through the NMOS and limits the maximum current to avoid damage to the load and AP7175 during overload conditions. Short Circuit Current-Limit Protection AP7175 incorporates a current limit function to reduce the maximum current to 1.1A (typ) when the voltage at FB falls below 0.2V (typ) during an overload or short circuit situation. During start-up period, this function is disabled to ensure successful heavy load start-up. Enable Control If the enable pin (EN) is left open, an internal current source of ~5µA pulls the pin up and enables the AP7175. This will reduce the bill of material saving an external pull up resistor. Driving the enable pin low disables the device. Driving the pin high subsequently initiates a new Soft-Start cycle. Output Voltage Regulation Output Voltage is set by resistor divider from VOUT via FB pin to GND. Internally VFB is compared to a 0.8V temperature compensated reference voltage and the NMOS pass element regulates the output voltage while delivering current from VIN to VOUT. Setting the Output Voltage A resistor divider connected to FB pin programs the output voltage. R1 V VOUT VREF * 1 R 2 R1 is connected from VOUT to FB with Kelvin sensing connection. R2 is connected from FB to GND. To improve load transient response and stability, a bypass capacitor can be connected in parallel with R1. (optional in typical application circuit) Power Sequencing AP7175 requires no specific sequencing between VIN and VCNTL. However, care should be taken to avoid forcing VOUT for prolonged time without the presence of VIN. Conduction through internal parasitic diode (from VOUT to VIN) could damage AP7175. Thermal Shutdown The PCB layout and power requirements for AP7175 under normal operation condition should allow enough cooling to restrict the junction temperature to +125°C. The packages for AP7175 have an exposed PAD to support this. These packages provide better connection to the PCB and thermal performance. Refer to the layout considerations. If AP7175 junction temperature reaches +170°C a thermal protection block disables the NMOS pass element and lets the part cool down. After its junction temperature drops by 50°C (typ), a new Soft-Start cycle will be initiated. A new thermal protection will start, if the load or ambient conditions continue to raise the junction temperature to +170°C. This cycle will repeat until normal operation temperature is maintained again. AP7175 Document number: DS35606 Rev. 4 - 3 9 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Application Information (Cont.) Output Capacitor An output capacitor (COUT) is needed to improve transient response and maintain stability. The ESR (equivalent series resistance) and capacitance drives the selection. Care needs to be taken to cover the entire operating temperature range. The output capacitor can be an Ultra-Low-ESR ceramic chip capacitor or a low ESR bulk capacitor like a solid tantalum, POSCap or aluminum electrolytic capacitor. COUT is used to improve the output stability and reduces the changes of the output voltage during load transitions. The slew rate of the current sensed via the FB pin in AP7175 is reduced. If the application has large load variations, it is recommended to utilize low-ESR bulk capacitors. It is recommended to place ceramic capacitors as close as possible to the load and the ground pin and care should be taken to reduce the impedance in the layout. Input Capacitor To prevent the input voltage from dropping during load steps it is recommended to utilize an input capacitor (C IN). As with the output capacitor the following are acceptable, Ultra-Low-ESR ceramic chip capacitor or low ESR bulk capacitor like a solid tantalum, POSCap or aluminum electrolytic capacitor. Typically it is recommended to utilize an capacitance of at least 10µF to avoid output voltage drop due to reduced input voltage. The value can be lower if VIN changes are not critical for the application. Layout Considerations For good ground loop and stability, the input and output capacitors should be located close to the input, output, and ground pins of the device. No other application circuit is connected within the loop. Avoid using vias within ground loop. If vias must be used, multiple vias should be used to reduce via inductance. The regulator ground pin should be connected to the external circuit ground to reduce voltage drop caused by trace impedance. Ground plane is generally used to reduce trace impedance. Wide trace should be used for large current paths from VIN to VOUT, and load circuit. Place the R1, R2, and C1 (optional) near the LDO as close as possible to avoid noise coupling. R2 is placed close to device ground. Connect the ground of the R2 to the GND pin by using a dedicated trace. Connect the pin of the R1 directly to the load for Kelvin sensing. No high current should flow through the ground trace of feedback loop and affect reference voltage stability. For the packages with exposed pads, heat sinking is accomplished using the heat spreading capability of the PCB and its copper traces. Suitable PCB area on the top layer and thermal vias(0.3mm drill size with 1mm spacing, 4~8 vias at least) to the Vin power plane can help to reduce device temperature greatly. Reference Layout Plots Top Layer Bottom Layer Cin Vin Cout Vout Vin GND Vcntl FB R1 PG PG GND 1 GND Ccntl EN AP7175 Document number: DS35606 Rev. 4 - 3 R2 C1 EN 10 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Ordering Information AP7175 XX - 13 Package Packing 13 : Tape & Reel SP : SO-8EP MP : MSOP-8EP Part Number Package Code Packaging AP7175SP-13 AP7175MP-13 SP MP SO-8EP MSOP-8EP Quantity 13” Tape and Reel Part Number Suffix 2500/Tape & Reel 2500/Tape & Reel -13 -13 Marking Information (1) SO-8EP ( Top View ) 5 8 Logo 1 (2) YY : Year : 08, 09,10~ WW : Week : 01~52; 52 represents 52 and 53 week X : Internal Code SO-8EP G : Green AP7175 YY WW X X E Part No 4 MSOP-8EP ( Top View ) 8 7 Logo AP7175 1 Document number: DS35606 Rev. 4 - 3 5 YWXE Part Number AP7175 6 2 3 A~Z : Internal Code MSOP-8EP Y : Year : 0~9 W : Week : A~Z : 1~26 week; a~z : 27~52 week; z represents 52 and 53 week 4 11 of 14 www.diodes.com January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Package Outline Dimensions Please see http://www.diodes.com/package-outlines.html for the latest version. (1) SO-8EP EXPOSED PAD SO-8EP Dim Min Max Typ A 1.40 1.50 1.45 A1 0.00 0.13 b 0.30 0.50 0.40 C 0.15 0.25 0.20 D 4.85 4.95 4.90 E 3.80 3.90 3.85 E0 3.85 3.95 3.90 E1 5.90 6.10 6.00 e 1.27 F 2.75 3.35 3.05 H 2.11 2.71 2.41 L 0.62 0.82 0.72 N 0.35 Q 0.60 0.70 0.65 All Dimensions in mm H E1 F 1 b Q E 9° ( All sid e) 45° 7° C N 4° ± 3° A e L A1 R Gauge Plane Seating Plane 1 0. E0 D (2) MSOP-8EP D D1 E 10 ° 0.25 x 4X E2 Gauge Plane Seating Plane a y 1 L 4X 10 ° 8Xb e Detail C E3 A1 A3 c A2 A D E1 See Detail C AP7175 Document number: DS35606 Rev. 4 - 3 12 of 14 www.diodes.com MSOP-8EP Dim Min Max Typ A 1.10 A1 0.05 0.15 0.10 A2 0.75 0.95 0.86 A3 0.29 0.49 0.39 b 0.22 0.38 0.30 c 0.08 0.23 0.15 D 2.90 3.10 3.00 D1 1.60 2.00 1.80 E 4.70 5.10 4.90 E1 2.90 3.10 3.00 E2 1.30 1.70 1.50 E3 2.85 3.05 2.95 e 0.65 L 0.40 0.80 0.60 a 0° 8° 4° x 0.750 y 0.750 All Dimensions in mm January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 Suggested Pad Layout Please see http://www.diodes.com/package-outlines.html for the latest version. (1) SO-8EP X2 Dimensions C X X1 X2 Y Y1 Y2 Y1 Y2 X1 Value (in mm) 1.270 0.802 3.502 4.612 1.505 2.613 6.500 Y C (2) X MSOP-8EP C X Dimensions G Y Y2 C G X X1 Y Y1 Y2 Y1 X1 AP7175 Document number: DS35606 Rev. 4 - 3 13 of 14 www.diodes.com Value (in mm) 0.650 0.450 0.450 2.000 1.350 1.700 5.300 January 2017 © Diodes Incorporated NOT RECOMMENDED FOR NEW DESIGN NO ALTERNATE PART AP7175 IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. 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LIFE SUPPORT Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: A. Life support devices or systems are devices or systems which: 1. are intended to implant into the body, or 2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. Copyright © 2017, Diodes Incorporated www.diodes.com AP7175 Document number: DS35606 Rev. 4 - 3 14 of 14 www.diodes.com January 2017 © Diodes Incorporated