Fairchild CGS3322 Cmos crystal clock generator Datasheet

Revised January 2001
CGS3321 • CGS3322
CMOS Crystal Clock Generators
General Description
Features
The CGS3321 and CGS3322 devices are designed for
Clock Generation and Support (CGS) applications up to
110 MHz. The CGS332x series of devices are crystal controlled CMOS oscillators requiring a minimum of external
components. The 332x devices provide selectable output
divide ratio. The circuit is designed to operate over a wide
frequency range using fundamental mode or overtone crystals.
■ Fairchild’s CGS family of devices for high frequency
clock source applications
■ Crystal frequency operation range:
fundamental: 10 MHz to 100 MHz typical
3rd or 5th overtone: 10 MHz to 95 MHz
■ 1000V ESD protection on OCS_IN and OSC_OUT pins.
2000V ESD protection on all other pins
■ Output current drive of 48 mA for IOL/IOH
■ FACT CMOS output levels
■ Output has high speed short circuit protection
■ Intended for Pierce oscillator applications
■ Hysteresis inputs to improve noise margin
■ CGS3321 has duty cycle adjust
■ CGS3322 has 1, 2, 4 divide ratio
Ordering Code:
Order Number
Package Number
Package Description
CGS3321M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CGS3322M
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Truth Table
Division Selection
CGS3321
DIVB
OEH
Divider Output
F
X
Divide-by 1
1
1
Divide-by 2
0
1
Divide-by 4
Note: Actual value of the floating DIVB input is VCC/2
CGS3322
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS011503
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CGS3321 • CGS3322 CMOS Crystal Clock Generators
September 1195
CGS3321 • CGS3322
Pin Descriptions
Note: Pin out varies for each device.
OSC_IN
Input to Oscillator Inverter. The output of the
crystal would be connected here.
OEH
Active HIGH 3-STATE enable pin. This pin pulls
to a HIGH value when left floating and 3STATEs the output when forced LOW. This pin
has TTL compatible input levels.
OSC_OUT Resistive Buffered Output of the Oscillator
Inverter
OUT
This pin is the main clock output on the device.
DIVB
(CGS3322 only)
3-Level input used to select Binary Divide-by
value of output frequency.
OSCLO_1
The Oscillator LOW pin is the ground for the
Oscillator.
DC_ADJ
(CGS3321 only)
Active high input that controls output duty
cycle. Logic high level will delay the HL transition edge approximately 0.3 ns.
VCC
The power pin for the chip.
GND
The ground pin for all sections of the circuitry
except the oscillator and oscillator related
circuitry.
Note: Pin out varies for each device.
Block Diagrams
Note: Pin numbers vary for each device
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2
CGS3321 • CGS3322
Block Diagrams
(Continued)
Oscillator Stage
Output Stage
3
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CGS3321 • CGS3322
Absolute Maximum Ratings(Note 1)
−0.5V to 7.0V
Supply Voltage (VCC)
±9 mA
DC Input Voltage Diode Current (IIK)
Supply Voltage (VCC)
−0.5V to 7.0V
DC Input Voltage (VI)
-0.5V to VCC + 0.5V
0V to VCC V
−40° to +85°C
Operating Temperature (TA)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the DC and AC
Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation.
±70 mA
or Sink Current (IO)
0V to 5.5V
Output Voltage (VO)
DC Output Source
−55°C to 150°C
Storage Temperature (TSTG)
4.5V to 5.5V
Input Voltage (VI)
±20 mA
DC Output Diode Current (IOK)
DC Output Voltage (VO)
Recommended Operating
Conditions
Junction Temperature (TJ)
140 °C/W
SOIC
DC Electrical Characteristics
TA = +25°C
Symbol
Parameter
VCC
(V)
VIHTTL
VILTTL
VIHCMOS
VILCMOS
VIN3L_H
VIN3L_1/2
VIN3L_L
VOH
VOL
Typ
TA = −40° C to +85°C
Units
Guaranteed Limits
Min
Max
Min
Minimum HIGH Level
Input Voltage,
TTL Level Inputs (OEH, OEL)
4.5
2.0
2.0
5.5
2.0
2.0
Maximum LOW Level
Input Voltage, TTL Level
Inputs (OEH, OEL)
4.5
0.8
0.8
5.5
0.8
0.8
Minimum HIGH Level
Input Voltage. CMOS
Level Inputs (DC_ADJ)
4.5
3.15
3.15
5.5
3.85
3.85
Maximum LOW Level
Input voltage. CMOS
Level Inputs (DC_ADJ)
4.5
1.35
1.35
5.5
1.65
1.65
Minimum Logic 1 Input
for Three Level Input
(DIVB)
4.5
4.05
4.05
5.5
4.95
4.95
Minimum Logic 1/2 Input
for Three Level Input
(DIVB)
4.5
1.8
2.7
1.8
2.7
5.5
2.2
3.3
2.2
3.3
Maximum Logic 0 Input
Level Three Level Input
(DIVB)
4.5
0.45
0.45
5.5
0.45
0.45
Minimum HIGH Level
Output Voltage
Minimum LOW Level
Output Voltage
IIHRES
Input Current for Pins DIVB
IILRES
4.5
4.49
4.40
4.40
5.5
5.49
5.40
5.40
4.5
3.86
3.76
5.5
4.86
4.76
Conditions
Max
V
V
V
V
V
V
V
IOUT = −50µA
V
IOH = −48 mA
VIN = VIH or VIH
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
4.5
0.44
0.44
5.5
0.44
0.44
IOUT = 50µA
V
IOL = +48mA
VIN = VIL or VIH
5.5
220
360
200
380
µA
VIN = 5.5V
Input Current for Pins DIVB
5.5
−220
−360
−200
−380
µA
VIN = 0.0V
IIHENAB
Input Current for
Enable Pin OEL
5.5
90
160
85
175
µA
VIN = 5.5V
IILENAB
Input Current for
Enable Pin OEH
5.5
−90
−160
−85
−175
µA
VIN = 0.0V
IIHOSC
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
5.5
20
100
20
125
µA
VIN = 5.5V
IILOSC
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
5.5
−20
−100
−20
−125
µA
VIN = 0.0V
IOZH
Output Disabled Current
4.5
3.0
5.0
(Output HIGH)
5.5
3.0
5.0
IOZL
Output Disabled Current
4.5
−140
−150
(Output LOW)
5.5
−170
−180
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4
µA
µA
VOUT = VCC
VOUT = 0.0V
(Continued)
TA = +25°C
Symbol
Parameter
VCC
(V)
Typ
TA = −40° C to +85°C
Units
Guaranteed Limits
Min
Max
Min
Conditions
Max
IOLD
Minimum Dynamic
Output Current
5.5
75
75
mA
VOLD = 1.65V
IOHD
Minimum Dynamic
Output Current
5.5
−75
−75
mA
VOHD = 3.85V
ICCT
Additional Maximum ICC
per Input
(OEH, OEL Pins)
5.5
1.5
1.5
mA
VIN = VCC − 2.1V
Additional Maximum ICC
per Input
(DIVB)
5.5
1.5
1.5
mA
DIVB, OSC_DR
Inputs Equal to VCC/2
ICC3L
AC Electrical Characteristics
Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.
TA = −40°C to + 85°C
VCC
Symbol
Parameter
CL = 50 pF
(V)
(Note 2)
Min
Type
110
Units
Max
fMAX
Frequency Maximum
5.0
95
tPZH
Output HIGH Enable Time
5.0
1.0
31.5
ns
tPZL
Output LOW Enable Time
5.0
1.0
28.0
ns
tPHZ
Output HIGH Disable Time
5.0
1.0
21.5
ns
tPLZ
Output LOW Disable Time
5.0
1.0
16.0
ns
tRISE
Rise/Fall Time
tFALL
30 pF (20% to 80%)
5.0
1.0
MHz
ns
Note 2: Voltage Range 5.0 is 5.0V ± 0.5V
5
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CGS3321 • CGS3322
DC Electrical Characteristics
CGS3321 • CGS3322 CMOS Crystal Clock Generators
Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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