Holt HI-3584APCIF-15 Arinc 429 3.3v serial transmitter Datasheet

HI-3584A
GENERAL DESCRIPTION
APPLICATIONS
The HI-3584A from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-3584A design offers a highspeed host CPU interface compared with the earlier HI3584 product. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO. The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-3584A’s status
register.
•
Avionics data communication
•
Serial to parallel conversion
•
Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 13 for additional pin configuration)
See Note below
64 - N/C
63 - RIN2B
62 - RIN2A
61 - RIN1B
60 - RIN1A
59 - N/C
58 - VDD
57 - VDD
56 - VDD
55 - N/C
54 - N/C
53 - MR
52 - TXCLK
51 - CLK
50 - RSR
49 - N/C
July 2013
ARINC 429 3.3V Serial Transmitter
and Dual Receiver with High-Speed Interface
Other features include a programmable option of data or
parity in the 32nd bit, and the ability to unscramble the 32 bit
word. Also, versions are available with different values of
input resistance to allow users to more easily add external
lightning protection circuitry.
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
The HI-3584A applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
N/C - 17
BD10 - 18
BD09 - 19
BD08 - 20
BD07 - 21
BD06 - 22
GND - 23
N/C - 24
N/C - 25
N/C - 26
N/C - 27
BD05 - 28
BD04 - 29
BD03 - 30
BD02 - 31
N/C - 32
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
HI-3584APCI
HI-3584APCT
&
HI-3584APCM
48 - CWSTR
47 - ENTX
46 - 429DO
45 - N/C
44 - N/C
43 - N/C
42 - N/C
41 - 429DO
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
52 - D/R1
51 - RIN2B
50 - RIN2A
49 - RIN1B
48 - RIN1A
47 - VDD
46 - N/C
45 - N/C
44 - MR
43 - TXCLK
42 - CLK
41 - RSR
40 - N/C
Additional interface circuitry such as the Holt HI-8570 or
HI-8571 is required to translate the transmitter’s 3.3 volt
logic outputs to ARINC 429 drive levels.
FEATURES
• ARINC specification 429 compatible
•
•
•
•
•
•
3.3V logic supply operation
Dual receiver and transmitter interface
Analog line receivers connect directly to ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for transmitter
and each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & Extended temperature ranges
((DS3584A Rev. C)
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3584APQI
HI-3584APQT
&
HI-3584APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - N/C
35 - 429DO
34 - 429DO
33 - N/C
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
BD10 - 14
BD09 - 15
BD08 - 16
BD07 - 17
BD06 - 18
N/C - 19
GND - 20
N/C - 21
BD05 - 22
BD04 - 23
BD03 - 24
BD02 - 25
BD01 - 26
•
•
•
•
•
•
•
52 - Pin Plastic Quad Flat Pack (PQFP)
HOLT INTEGRATED CIRCUITS
www.holtic.com
0 7/13
HI-3584A
PIN DESCRIPTIONS
SIGNAL
FUNCTION
VDD
RIN1A
RIN1B
RIN2A
RIN2B
D/R1
FF1
HF1
D/R2
FF2
HF2
SEL
EN1
EN2
BD15
BD14
BD13
BD12
BD11
BD10
BD09
BD08
BD07
BD06
GND
BD05
BD04
BD03
BD02
BD01
BD00
PL1
PL2
TX/R
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
POWER
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
OUTPUT
HFT
FFT
429DO
429DO
ENTX
CWSTR
RSR
CLK
TX CLK
MR
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
INPUT
DESCRIPTION
+3.3V ±5% (All three VDD pins on the chip-scale package must be connect to the same supply)
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
FIFO full Receiver 1
FIFO Half full, Receiver 1
Receiver 2 data ready flag
FIFO full Receiver 2
FIFO Half full, Receiver 2
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
Data Bus control, enables receiver 1 data to outputs
Data Bus control, enables receiver 2 data to outputs if EN1 is high
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0V
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after
transmission and FIFO empty.
Transmitter FIFO Half Full
Transmitter FIFO Full
“ONES” data output from transmitter
“ZEROS” data output from transmitter
Enable Transmission
Clock for control word register
Read Status Register if SEL=0, read Control Register if SEL=1
Master Clock input
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HI-3584A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
STATUS REGISTER
The HI-3584A contains a 16-bit control register which is used to
configure the device. The control register bits CR0 - CR15 are
loaded from BD00 - BD15 when CWSTR is pulsed low. The control register contents are output on the databus when SEL = 1 and
RSR is pulsed low. Each bit of the control register has the following function:
The HI-3584A contains a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs
and transmitter. The contents of the status register are output on
BD00 - BD08 when the RSR pin is taken low and SEL = 0. Unused
bits are output as zeros. The following table defines the status register bits.
CR
Bit
CR0
CR1
CR2
CR3
CR4
CR5
CR6
SR
FUNCTION
STATE
DESCRIPTION
Bit
Receiver 1
Data clock
Select
0
Data rate = CLK/10
SR0
1
Data rate = CLK/80
Label Memory
Read / Write
0
Normal operation
1
Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
Enable Label
Recognition
(Receiver 1)
0
Disable label recognition
1
Enable label recognition
Enable Label
Recognition
(Receiver 2)
0
Disable Label Recognition
1
Enable Label recognition
Enable
32nd bit
as parity
0
Transmitter 32nd bit is data
1
Transmitter 32nd bit is parity
Self Test
0
The 429DO and 429DO digital
outputs are internally connected
to the receiver logic inputs
Receiver 1
decoder
SR1
SR2
1
Normal operation
0
Receiver 1 decoder disabled
1
ARINC bits 9 and 10 must match
CR7 and CR8
SR3
SR4
CR7
-
-
If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
CR8
-
-
If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
CR9
Receiver 2
Decoder
0
Receiver 2 decoder disabled
1
ARINC bits 9 and 10 must match
CR10 and CR11
-
If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
SR5
SR6
CR10
-
CR11
-
-
If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
CR12
Invert
Transmitter
parity
0
Transmitter 32nd bit is Odd parity
1
Transmitter 32nd bit is Even parity
Transmitter
data clock
select
0
Data rate=CLK/10, O/P slope=1.5us
1
Data rate=CLK/80, O/P slope=10us
Receiver 2
data clock
select
0
Data rate=CLK/10
1
Data rate=CLK/80
Data
format
0
Scramble ARINC data
1
Unscramble ARINC data
CR13
CR14
CR15
SR7
SR8
FUNCTION
STATE
Data ready
(Receiver 1)
0
Receiver 1 FIFO empty
1
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
0
Receiver 1 FIFO holds less than 16
words
1
Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
0
Receiver 1 FIFO not full
1
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
0
Receiver 2 FIFO empty
1
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
0
Receiver 2 FIFO holds less than 16
words
1
Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
0
Receiver 2 FIFO not full
1
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
0
Transmitter FIFO not empty
1
Transmitter FIFO empty.
0
Transmitter FIFO not full
1
Transmitter FIFO full. FFT pin is the
inverse of this bit.
0
Transmitter FIFO contains less than
16 words
1
Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
FIFO half full
(Receiver 1)
FIFO full
(Receiver 1)
Data ready
(Receiver 2)
FIFO half full
(Receiver 2)
FIFO full
(Receiver 2)
Transmitter FIFO
empty
Transmitter FIFO
full
Transmitter FIFO
half full
HOLT INTEGRATED CIRCUITS
3
DESCRIPTION
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
The HI-3584A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition (3.0V supply and 13V signal level).
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3584A
data bus during data read or write operations. The following table
describes this mapping:
BYTE 1
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
RECEIVER LOGIC OPERATION
ARINC
BIT
CR15=0
13 12 11 10
ARINC
BIT
CR15=1
16 15 14 13 12 11 10
Label
Label
Label
9
8
7
6
5
4
3
2
1
Label
Label
Label
SDI
Label
BIT TIMING
Label
Figure 2 shows a block diagram of the logic section of each receiver.
Label
8
Label
7
Label
6
Label
5
Label
4
Label
3
Label
2
Label
1
Parity
31 30 32
SDI
9
SDI
SDI
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
DATA
BUS
BYTE 2
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
CR15=0
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
ARINC
BIT
CR15=1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Parity
DATA
BUS
The ARINC 429 specification contains the following timing specification for the received data:
HIGH SPEED
LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
BIT RATE
10 ± 5 µsec
PULSE RISE TIME 1.5 ± 0.5 µsec
10 ± 5 µsec
PULSE FALL TIME 1.5 ± 0.5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec
PULSE WIDTH
The HI-3584A accepts signals that meet these specifications and rejects signals outside the tolerances. The way the logic operation
achieves this is described below:
1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended.
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
VDD
DIFFERENTIAL
AMPLIFIERS
RIN1A
OR
RIN2A
3. Each data bit must follow its predecessor by not less than 8
samples and no more than 12 samples. In this manner the bit
rate is checked. With exactly 1MHz input clock frequency, the
acceptable data bit rates are as follows:
COMPARATORS
ONES
GND
NULL
VDD
ZEROES
RIN1B
OR
RIN2B
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed.
DATA BIT RATE MIN
DATA BIT RATE MAX
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every 10
input clocks (80 for low speed) after the last data bit of a valid
reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
4
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
ARINC words which do not meet the necessary 9th and 10th
ARINC bit or label matching are ignored and are not loaded into
the receive FIFO. The following table describes this operation.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
FIFO
0
X
0
X
Load FIFO
1
No
0
X
Ignore data
Therefore, the 32nd bit retrieved from the receiver FIFO will
always be “0” when valid (odd parity) ARINC 429 words are
received.
1
Yes
0
X
Load FIFO
0
X
1
No
Ignore data
RETRIEVING DATA
0
X
1
Yes
Load FIFO
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO.
1
Yes
1
No
Ignore data
1
No
1
Yes
Ignore data
1
No
1
No
Ignore data
1
Yes
1
Yes
Load FIFO
TO PINS
SEL
EN
MUX
CONTROL
32 TO 16 DRIVER
CONTROL
BITS
R/W
CONTROL
HF
FF
D/R
32 X 32
FIFO
LOAD
CONTROL
FIFO
/
CONTROL
BIT
LABEL /
DECODE
COMPARE
CLOCK
OPTION
CONTROLBITS
CR0, CR14
CLK
CLOCK
16 x 8
LABEL
MEMORY
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
BIT CLOCK
EOS
ONES
WORD GAP
SHIFT REGISTER
WORD GAP
TIMER
BIT CLOCK
END
START
NULL
SHIFT REGISTER
ZEROS
SHIFT REGISTER
SEQUENCE
CONTROL
ERROR
ERROR
DETECTION
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
5
CLOCK
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)
will go low. The data flag for a receiver will remain low until both
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating EN with SEL, the
byte selector, low to retrieve the first byte and then activating EN
with SEL high to retrieve the second byte. EN1 retrieves data
from receiver 1 and EN2 retrieves data from receiver 2.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (EN taken low) are labels. EN1 is
used to read labels for receiver 1, and EN2 to read labels for
receiver 2. Label data is presented on BD00 - BD07.
When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.
Up to 32 ARINC words may be loaded into each receiver’s FIFO.
The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full.
Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO
contains 16 or more received ARINC words. The HF1 (HF2) pin is
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the HI3584A’s status register bits.
TRANSMITTER
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
be loaded. If TX/R is low, then only the available positions may be
loaded. If all 32 positions are full, the FFT flag is asserted and the
FIFO ignores further attempts to load data.
LABEL RECOGNITION
The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00-BD07 are
always compared to received ARINC bits 1 -8 respectively.
A transmitter FIFO half-full flag HFT is provided. When the
transmit FIFO contains less than 16 words, HFT is high,
indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.
LOADING LABELS
In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If CR4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are
treated as data and are transmitted.
After a write that takes CR1 from 0 to 1, the next 16 writes of data
(PL pulsed low) load label data into each location of the label
memory from the BD00 - BD07 pins. The PL1 pin is used to write
label data for receiver 1 and PL2 for receiver 2. Note that ARINC
word reception is suspended during the label memory write
sequence.
CR4,12
32 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
429DO
429DO
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
32 x 32 FIFO
DATA AND
NULL TIMER
SEQUENCER
START
SEQUENCE
ADDRESS
TX/R
WORD COUNTER
AND
FIFO CONTROL
LOAD
HFT
FFT
ENTX
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
PL1
PL2
DATA BUS
DATA
CLOCK
CR13
FIGURE 3.
DATA CLOCK
DIVIDER
TRANSMITTER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
6
CLK
TX CLK
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
DATA TRANSMISSION
REPEATER OPERATION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at 429DO and 429DO. The 31 or 32 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, TX/R, high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. If
control register bit CR12 is set low, the 32nd bit transmitted will
make parity odd. If the control bit is, high the parity is even.
Setting CR4 to a Zero bypasses the parity generator, and allows
32 bits of data to be transmitted.
SELF TEST
If control register bit CR5 is set low, the transmitter serial output
data are internally connected to each of the two receivers,
bypassing the analog interface circuitry. Data is passed unmodified to receiver 1 and inverted to receiver 2. The serial data from
the transmitter is always present on the 429DO and 429DO
outputs regardless of the state of CR5.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data will be overwritten if the receiver FIFO
is full and at least one location is not retrieved before the
next complete ARINC word is received.
2. The transmitter FIFO can store 32 words maximum and
ignores attempts to load additional data if full.
Repeater mode of operation allows a data word that has been
received by the HI-3584A to be placed directly into the transmitter
FIFO. Repeater operation is similar to normal receiver operation.
In normal operation, either byte of a received data word may be
read from the receiver latches first by use of SEL input. During
repeater operation however, the lower byte of the data word must
be read first. This is necessary because, as the data is being
read, it is also being loaded into transmitter FIFO which is always
loaded with the lower byte of the data word first. Signal flow for
repeater operation is shown in the Timing Diagrams section.
HI-3584A-15
The HI-3584A-15 option is similar to the HI-3584A with the exception that it allows an external 15 Kohm resistor to be added in series with each ARINC input without affecting the ARINC input
thresholds. This option is especially useful in applications where
lightning protection circuitry is also required.
Each side of the ARINC bus must be connected through a 15
Kohm series resistor in order for the chip to detect the correct
ARINC levels. The typical 10 volt differential signal is translated
and input to a window comparator and latch. The comparator
levels are set so that with the external 15 Kohm resistors, they are
just below the standard 6.5 volt minimum ARINC data threshold
and just above the standard 2.5 volt maximum ARINC null
threshold.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
HIGH SPEED OPERATION
The HI-3584A may be operated at clock frequencies beyond that
required for ARINC compliant operation. For operation at Master
Clock (CLK) frequencies up to 5MHz, please contact Holt applications engineering.
MASTER RESET (MR)
On a Master Reset data transmission and reception are
immediately terminated, all three FIFOs are cleared as are the
FIFO flags at the device pins and in the Status Register. The
Control Register is not affected by a Master Reset.
HOLT INTEGRATED CIRCUITS
7
HI-3584A
TIMING DIAGRAMS
DATA RATE - EXAMPLE PATTERN
429 DATA
ARINC BIT
429 DATA
NULL
DATA
DATA
DATA
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
RECEIVER OPERATION
BIT 31
ARINC DATA
BIT 32
D/R, HF, FF
tEND/R
tD/R
DON'T CARE
SEL
tEN
tSELEN
tSELEN
tENSEL
EN
tENEN
tD/REN
tSELEN
tENSEL
tREADEN
CLK
tCLKEN
tCLKEN
tDATAEN
tDATAEN
BYTE 2 VALID
BYTE 1 VALID
DATA BUS
tENDATA
BYTE 1
tENDATA
tENDATA
TRANSMITTER OPERATION
BYTE 2 VALID
BYTE 1 VALID
DATA BUS
tDWSET
tDWSET
tDWHLD
tDWHLD
PL1
tPL
tPL12
tPLCYC
PL2
tPL12
tPL
TX/R, HFT, FFT
LOADING CONTROL WORD
VALID
DATA BUS
tCWSET
tCWHLD
CWSTR
tCWSTR
HOLT INTEGRATED CIRCUITS
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tTX/R
HI-3584A
TIMING DIAGRAMS (cont.)
STATUS REGISTER READ CYCLE
BYTE SELECT
DON'T CARE
SEL
DON'T CARE
tSELEN
tENSEL
RSR
tDATAEN
DATA VALID
DATA BUS
tENDATA
CONTROL REGISTER READ CYCLE
BYTE SELECT
SEL
DON'T CARE
DON'T CARE
tSELEN
tENSEL
RSR
tDATAEN
DATA VALID
DATA BUS
tENDATA
LABEL MEMORY LOAD SEQUENCE
tCWSTR
CWSTR
tCWSET
DATA BUS
Set CR1=1
tCWHLD
Label #1
Label #2
Label #16
Set CR1=0
tDWSET
tDWHLD
PL1 / PL2
tPL
tLABEL
LABEL MEMORY READ SEQUENCE
tCWSTR
CWSTR
tREADEN
EN1 / EN2
tCWHLD
tDATAEN
tCWSET
DATA BUS
Set CR1=1
Label #1
Label #2
tENDATA
HOLT INTEGRATED CIRCUITS
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Label #16
Set CR1=0
HI-3584A
TIMING DIAGRAMS (cont.)
TRANSMITTING DATA
PL2
tDTX/R
tPL2EN
TXR
tENTX/R
ENTX
tENDAT
ARINC BIT
DATA
BIT 1
ARINC BIT
DATA
BIT 2
ARINC BIT
DATA
BIT 32
429DO
429DO
One
Null
Zero
Null
One
Null
REPEATER OPERATION TIMING
RIN
BIT 32
tEND/R
D/R
tD/R
tD/REN
tEN
tENEN
tEN
EN
tSELEN
SEL
tENSEL
DON'T CARE
DON'T CARE
tENPL
tSELEN
tPLEN
tENSEL
PL1
tPLEN
tENPL
PL2
tTX/R
TXR
tTX/REN
tENTX/R
ENTX
tDTX/R
tENDAT
429DO
429DO
BIT 1
BIT 32
tNULL
HOLT INTEGRATED CIRCUITS
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HI-3584A
ABSOLUTE MAXIMUM RATINGS
Supply Voltages VDD ........................................... -0.3V to +4V
Power Dissipation at 25°C .......................................... 500 mW
Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ... -120V to +120V
DC Current Drain per pin .............................................. ±10mA
Voltage at any other pin ............................... -0.3V to VDD +0.3V
Storage Temperature Range ........................ -65°C to +150°C
Solder temperature (Reflow) ............................................ 260°C
Operating Temperature Range (Industrial): .... -40°C to +85°C
(Extended): .. -55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
ARINC INPUTS
-
SYMBOL
CONDITIONS
VIH
VIL
VNUL
Common mode voltage
less than ±4V with
with respect to GND
MIN
TYP
MAX
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
80
45
45
UNIT
Pins RIN1A, RIN1B, RIN2A, RIN2B
Differential Input Voltage:
(RIN1A to RIN1B, RIN2A to RIN2B)
ONE
ZERO
NULL
Input Resistance:
Differential
To GND
To VDD
RI
RG
RH
12
12
12
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To VDD
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
Pull-down Current (TEST pin)
Pull-up Current (RSR pin)
IIH
IIL
IPD
IPU
Input Current:
Input Capacitance:
(Guaranteed but not tested)
(RIN1A to RIN1B, RIN2A to RIN2B)
V
V
V
KW
KW
KW
200
µA
µA
20
20
20
pF
pF
pF
30%
VDD
VDD
BI-DIRECTIONAL INPUTS - Pins BD00 - BD15
Input Voltage:
Input Current:
70%
1.5
-1.5
µA
µA
OTHER INPUTS
Input Voltage:
Input Current:
Input Capacitance:
(Guaranteed but not tested)
70%
30%
1.5
µA
µA
µA
µA
15
pF
10%VDD
V
V
-1.0
mA
mA
15
pF
7
mA
-1.5
330
-330
CI
V
V
OUTPUTS
Output Voltage:
Output Current:
(All Outputs & Bi-directional Pins)
Output Capacitance:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
VDD - 0.2V
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
1.6
CO
Operating Supply Current
VDD
IDD
HOLT INTEGRATED CIRCUITS
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3.5
HI-3584A
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle
PARAMETER
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
25
25
5
ns
ns
ns
RECEIVER FIFO AND LABEL READ TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
Delay - D/R LOW to EN LOW
Delay - EN HIGH to D/R HIGH
tD/REN
tEND/R
0
Setup - SEL to EN LOW
Hold - SEL to EN HIGH
tSELEN
tENSEL
0
10
Delay - EN LOW to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN LOW (Same ARINC Word)
Spacing -EN HIGH to next EN LOW (Next ARINC Word)
CLK HIGH separation from second EN pulse HIGH (SEL is HIGH)
tEN
tENEN
16
128
µs
µs
25
ns
ns
ns
ns
50
20
ns
ns
tREADEN
tCLKEN
50
70
70
25
ns
ns
ns
ns
tPL
30
ns
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
tDWSET
tDWHLD
30
10
ns
ns
Spacing - PL1 or PL2
Spacing - PL1 rising to PL2 rising
Spacing between Label Write pulses
tPL12
tPLCYC
tLABEL
40
Delay - PL2 HIGH to TX/R LOW
tTX/R
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width - Pl1 or PL2
tCLK-10
ns
ns
ns
30
ns
40
TRANSMISSION TIMING
0
µs
50
ns
Spacing - TX/R HIGH to ENTX LOW
tENTX/R
Delay - ENTX HIGH to 429DO or 429DO: High Speed
tENDAT
0
25
µs
ns
Delay - ENTX HIGH to 429DO or 429DO: Low Speed
tENDAT
200
µs
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
tENPL
0
ns
Hold - PL HIGH to EN HIGH
tPLEN
0
ns
tTX/REN
0
ns
tMR
175
ns
Delay - TX/R LOW to ENTX HIGH
MASTER RESET PULSE WIDTH
ARINC DATA RATE AND BIT TIMING
± 1%
HOLT INTEGRATED CIRCUITS
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HI-3584A
ADDITIONAL HI-3584A PIN CONFIGURATION
7 - D/R1
6 - RIN2B
5 - RIN2A
4 - RIN1B
3 - RIN1A
2 - VDD
1 - N/C
52 - N/C
51 - MR
50 - TXCLK
49 - CLK
48 - RSR
47 - N/C
(See page 1 for additional pin configurations)
FF1 - 8
HF1 - 9
D/R2 - 10
FF2 - 11
HF2 - 12
SEL - 13
EN1 - 14
EN2 - 15
BD15 - 16
BD14 - 17
BD13 - 18
BD12 - 19
BD11 - 20
BD10 - 21
BD09 - 22
BD08 - 23
BD07 - 24
BD06 - 25
N/C - 26
GND - 27
N/C - 28
BD05 - 29
BD04 - 30
BD03 - 31
BD02 - 32
BD01 - 33
HI-3584ACJI
HI-3584ACJT
&
HI-3584ACJM
46 - N/C
45 - CWSTR
44 - ENTX
43 - N/C
42 - 429DO
41 - 429DO
40 - N/C
39 - FFT
38 - HFT
37 - TX/R
36 - PL2
35 - PL1
34 - BD00
52 - Pin Cerquad J-lead
ORDERING INFORMATION
HI - 3584A xx x x - xx
PART
NUMBER
INPUT SERIES RESISTANCE
BUILT-IN REQUIRED EXTERNALLY
No dash number
35K Ohm
0
-15
20K Ohm
15K Ohm
PART
NUMBER
PACKAGE
DESCRIPTION
Blank
Tin / Lead (Sn / Pb) Solder
F
100% Matte Tin (Pb-free RoHS compliant)
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
CJ
52 PIN J-LEAD CERQUAD (52U) not available Pb-free
PC
64 PIN PLASTIC CHIP-SCALE LPCC (64PCS)
PQ
52 PIN PLASTIC QUAD FLAT PACK PQFP (52PTQS)
HOLT INTEGRATED CIRCUITS
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HI-3584A
REVISION HISTORY
P/N
Rev
DS3584A NEW
A
B
C
Date
04/28/09
04/27/10
06/29/10
07/25/13
Description of Change
Initial Release
Added CLKEN to timing parameters.
Added PLCYC to timing parameters.
Updated Receiver Parity function, QFN and PQFP package drawing, timing parameter
tSELEN and solder temperature parameters. Remove note on heat sink connection for QFN
package. Update Voltage at ARINC input pins from +/-29V to +/-120V
HOLT INTEGRATED CIRCUITS
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HI-3584A PACKAGE DIMENSIONS
inches (millimeters)
52-PIN J-LEAD CERQUAD
Package Type: 52U
7
1 52
47
8
.788 max
(20.0) SQ.
.720 ±.010
(18.29 ±.25)
.750 ±.007
(19.05 ±.18)
.190 max
(4.826)
.040 ± .005
(1.02 ± .013)
.019 ±.002
(.483 ±.051)
.050 BSC
(1.27)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
52-PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 52PQS
.0256
BSC
(.65)
.520
BSC SQ
(13.2)
.394
BSC SQ
(10.0)
.012 ± .004
(.310 ± .09)
.035 ± .006
(.88 ± .15)
.063
typ
(1.6)
.008
min
(.20)
See Detail A
.106
MAX.
(2.7)
.005
(.13) R min
.079 ± .008
(2.0 ± .20)
.005
R min
(.13)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
DETAIL A
HOLT INTEGRATED CIRCUITS
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0° £ Q £ 7°
HI-3584A PACKAGE DIMENSIONS
inches (millimeters)
64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
.354
BSC
(9.00)
Package Type: 64PCS
Electrically isolated heat
sink pad on bottom of
package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.268 ± .039
(6.80 ± .05)
.0197
BSC
(0.50)
.354
BSC
(9.00)
.268 ± .039
(6.80 ± .05)
Top View
Bottom
View
.010
typ
(0.25)
.016 ± .002
(0.40 ± .05)
.008
typ
(0.20)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.039
max
(1.00)
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