Maxim MAX3747 155mbps to 3.2gbps, low-power sfp limiting amplifier Datasheet

19-3297; Rev 0; 5/04
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
Features
♦ Pin Compatible with Micrel SY88993V
♦ 155Mbps to 3.2Gbps Operation
♦ >57dB of Gain for the MAX3747 and MAX3747A
♦ <10-12 BER with 2mVP-P Input Amplitude
♦ 18mA Supply Current
♦ Chatter-Free LOS with Programmable Threshold
♦ Output DISABLE Function
♦ PECL-Compatible Inputs
Ordering Information
PART
TEMP RANGE
PINPACKAGE
PKG
CODE
MAX3747EUB
MAX3747AEUB
-40°C to +85°C
10 µMAX
U10C-4
-40°C to +85°C
10 µMAX
U10C-4
Applications
Gigabit Ethernet SFP/SFF Optical Transceiver
Modules
1G/2G Fibre-Channel SFP/SFF Optical
Transceiver Modules
Multirate OC-3 to OC-48 FEC SFP/SFF Optical
Transceiver Modules
10G LX4 Transceiver Modules
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
SFP OPTICAL RECEIVER
3-INPUT
DIAGNOSTIC
MONITOR
DS1859
HOST BOARD
SUPPLY FILTER
HOST FILTER
VCC
VCC_RX
MAX4004
VCC
0.1µF
MAX3745
IN+
0.1µF
MAX3747
MAX3747A
OUT+
IN-
OUT-
0.1µF
50Ω
SERDES
0.1µF
50Ω
5-PIN TO-HEADER
50Ω
VREF
50Ω
TH
GND LOS
DISABLE
4.7kΩ TO 10kΩ
VCC_HOST
LOS
R1
0.1µF
0.1µF
R2
VCC
R1 + R2 ≥ 5kΩ
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3747/MAX3747A
General Description
The MAX3747/MAX3747A multirate limiting amplifiers
function as data quantizers for OC-3 through OC-48 synchronous optical network (SONET), Fibre-Channel, and
Gigabit Ethernet optical receivers. They are pin-for-pin
compatible with the SY88993V from Micrel
Semiconductor, Inc. The amplifiers accept a wide range
of input voltages and provide constant-level, currentmode logic (CML) output voltages with controlled edge
speeds. The MAX3747 output voltage level is 500mVp-p
and the MAX3747A output voltage is 800mVp-p.
The MAX3747/MAX3747A limiting amplifiers feature a
programmable loss-of-signal detect (LOS) and an
optional disable function (DISABLE). Output disable can
be used to implement squelch.
The MAX3747/MAX3747A are available in a 3mm, 10-pin
µMAX® package ideal for small form-factor receivers.
MAX3747/MAX3747A
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .................................-0.5V to +4.5V
Voltage at IN+, IN- ..........................(VCC - 2.4V) to (VCC + 0.5V)
Voltage at DISABLE, LOS, TH, VREF ..........-0.5V to (VCC + 0.5V)
Current into LOS ...................................................-1mA to +9mA
Current into VREF ..................................................................2mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-) ..............................................-25mA to +25mA
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 6.9mW/°C above +70°C) ...........552mW
Operating Junction Temperature Range (TJ) .......-55°C to +150°C
Storage Ambient Temperature Range (TS)...........-55°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C,
unless otherwise specified.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MAX3747 includes the CML output current
30
35
MAX3747A includes the CML output current
36
41
MAX3747/MAX3747A exclude the CML
output current
18
24
PSNR
f < 2MHz
30
Input Sensitivity
VIN-MIN
(Note 3)
Input Overload
VIN-MAX
(Note 3)
UNITS
POWER SUPPLY
Supply Current (Note 2)
Power-Supply Noise Rejection
ICC
mA
dB
INPUT SPECIFICATION
4
1200
mVP-P
mVP-P
OUTPUT SPECIFICATION
Output Resistance
ROUT
Differential Output Return Loss
42
DUT is powered on, f < 3GHz
CML Differential Output Voltage
50
58
15
MAX3747A 4mVP-P ≤ VIN ≤ 1200mVP-P
600
800
1000
MAX3747 4mVP-P ≤ VIN ≤ 1200mVP-P
400
500
600
Differential Output Signal When
Disabled
AC-coupled outputs, VIN-MAX applied to the
input (Note 4)
Data-Output Transition Time
20% to 80% (Note 4)
Ω
dB
mVP-P
15
mVP-P
70
120
ps
13.2
19
14
25
K28.5 pattern at 2.1Gbps
12
17
PRBS 223 - 1 equivalent pattern at 155Mbps
(Note 6)
85
150
Random Jitter
VIN = 4mVP-P (Notes 4, 7)
3.5
5
psRMS
Input-Referred Noise
VIN = 4mVP-P (Note 4)
120
150
µVRMS
TRANSFER CHARACTERISTIC
K28.5 pattern at 3.2Gbps
PRBS 223 - 1 equivalent pattern at 2.7Gbps
(Note 6)
Deterministic Jitter (Notes 4, 5)
Low-Frequency Cutoff
2
DJ
6.4
_______________________________________________________________________________________
psP-P
kHz
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
(VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C,
unless otherwise specified.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOSS OF SIGNAL
LOS Hysteresis
10log(VDEASSERT / VASSERT) (Note 4)
1.25
LOS-Assert/Deassert Time
(Notes 4, 8)
2.3
Low LOS Assert Level
VTH = -1.3V (Notes 4, 9)
2.5
Low LOS Deassert Level
VTH = -1.3V (Notes 4, 9)
Medium LOS Assert Level
VTH = -0.68V (Notes 4, 9)
Medium LOS Deassert Level
VTH = -0.68V (Notes 4, 9)
High LOS Assert Level
VTH = -0.114V (Notes 4, 9)
High LOS Deassert Level
VTH = -0.114V (Notes 4, 9)
22
36.0
dB
40.0
µs
4.1
5.9
mVP-P
6.2
9.3
mVP-P
29
31
mVP-P
44.8
57
mVP-P
53.7
63.6
mVP-P
86
115
mVP-P
VCC 1.3V
VCC 1.19
V
TTL/CMOS I/O
VCC 1.35
VREF Voltage
VREF
LOS Output High Voltage
VOH
RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3V)
LOS Output Low Voltage
VOL
RLOS = 4.7kΩ to 10kΩ to VCC_HOST (3.6V)
DISABLE Input High
VIH
DISABLE Input Low
VIL
DISABLE Input Current
2.4
V
0.4
2.0
RLOS = 4.7kΩ to 10kΩ to VCC_HOST
V
V
0.8
V
10
µA
Note 1: The data-input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 x 2.667GHz for all data rates of
2.667Gbps and below. The f-3db = 0.75 x 3.2GHz for a data rate of 3.2Gbps.
Note 2: Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1).
Note 3: Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude.
Note 4: Guaranteed by design and characterization.
Note 5: The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification.
Note 6: The PRBS 223 - 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros.
Note 7: Random jitter was measured without using a filter at the input.
Note 8: The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2.
Note 9: VTH is the voltage at pin 5 referenced to VCC (see Figure 5).
_______________________________________________________________________________________
3
MAX3747/MAX3747A
ELECTRICAL CHARACTERISTICS (continued)
MAX3747/MAX3747A
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
VCC
ICC
(SUPPLY
CURRENT)
IOUT
(CML OUTPUT
CURRENT)
VIN
SIGNAL ON
50Ω
1dB
MAXIMUM DEASSERT LEVEL
6dB
MAXIMUM POWER-DETECT WINDOW
50Ω
MINIMUM ASSERT LEVEL
SIGNAL OFF
0V
TIME
MAX3747
MAX3747A
Figure 1. Power-Supply Current Measurement
Figure 2. LOS Deassert Threshold—Set 1dB Below the
Minimum by Receiver Sensitivity
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
MAX3747/MAX3747A toc01
MAX3747/MAX3747A toc02
3.2Gbps, 223 - 1 PRBS, 4mVP-P
60mV/div
60mV/div
50ps/div
4
3.2Gbps, 223 - 1 PRBS, 1200mVP-P
50ps/div
_______________________________________________________________________________________
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
MAX3747/MAX3747A toc05
2.7Gbps, 223 - 1 PRBS, 1200mVP-P
2.7Gbps, 223 - 1 PRBS, 4mVP-P
2.125Gbps, CJTPAT, 50mVP-P
60mV/div
60mV/div
80ps/div
70ps/div
70ps/div
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES OUTPUT CURRENT)
35
30
25
20
900
800
MAX3747A
700
2.7
600
500
MAX3747
400
300
2.1
1.8
1.5
1.2
0.9
200
0.6
15
100
0.3
10
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
0
0
1
2
3
3
2
1
0
100
1000
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
10,000
13,000
12,000
11,000
10,000
9000
8000
7000
6000
5000
4000
3000
2000
1000
1
MAX3747/MAX3747A toc10
BIT-ERROR RATIO (10-12)
RANDOM JITTER (psRMS)
4
MAX3747/MAX3747A toc09
3.2Gbps
10
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
BIT-ERROR RATIO vs. INPUT VOLTAGE
RANDOM JITTER vs. INPUT AMPLITUDE
1
5
4
DIFFERENTIAL INPUT (mVP-P)
5
VIN = 50mVP-P, FREQ = 2.7Gbps
2.4
RANDOM JITTER (psRMS)
40
RANDOM JITTER vs. TEMPERATURE
3.0
MAX3747/MAX3747A toc07
45
1000
DIFFERENTIAL OUTPUT (mVP-P)
MAX3747/MAX3747A toc06
50
TRANSFER FUNCTION
(OUTPUT VOLTAGE vs. INPUT VOLTAGE)
MAX3747/MAX3747A toc08
60mV/div
SUPPLY CURRENT (mA)
OUTPUT EYE DIAGRAM AT +100°C
MAX3747/MAX3747A toc04
MAX3747/MAX3747A toc03
MAXIM
MAX3747
MICREL
SY88993V
0
1
2
3
4
5
6
7
8
9
10
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
_______________________________________________________________________________________
5
MAX3747/MAX3747A
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
15
10
5
35
MAX3747/MAX3747A toc12
20
40
DETERMINISTIC JITTER (ps)
DETERMINISTIC JITTER (psP-P)
3.2Gbps, K28.5 PATTERN
MAX3747/MAX3747A toc11
DETERMINISTIC JITTER
vs. TEMPERATURE
25
FREQ = 3.2Gbps
PATTERN = K28.5
30
25
20
15
VIN = 5mVP-P
10
5
VIN = 500mVP-P
0
0
10
100
10,000
1000
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
ASSERT/DEASSERT vs. VTH
VTH (V) = VOLTAGE AT PIN 5 (V)
WITH RESPECT TO VCC
90
80
DEASSERT
70
60
50
40
ASSERT
30
20
10
0
40
35
ASSERT/DEASSERT (mV)
30
25
DEASSERT
20
15
10
ASSERT
5
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
VTH (V)
INPUT RETURN vs. FREQUENCY (SDD11)
(INPUT SIGNAL LEVEL = -60dBm)
OUTPUT RETURN vs. FREQUENCY (SDD22)
(INPUT SIGNAL LEVEL = -60dBm)
20
10
0
30
20
10
SDD11 (dB)
MAX3747/MAX3747A toc15
30
0
-10
-10
-20
-20
-30
-30
100
1000
FREQUENCY (MHz)
6
VTH = -1.1V, FREQ = 2.7Gbps
PATTERN = PRBS 223 - 1
MAX3747/MAX3747A toc16
ASSERT/DEASSERT (mVP-P)
110
100
ASSERT/DEASSERT vs. TEMPERATURE
MAX3747/MAX3747A toc13
120
MAX3747/MAX3747A toc14
1
SDD22 (dB)
MAX3747/MAX3747A
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
10,000
100
1000
10,000
FREQUENCY (MHz)
_______________________________________________________________________________________
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
MAX3747/
MAX3747A
MICREL
SY8893V
NAME
NAME
1
DISABLE
EN
2
IN+
DIN
Noninverted Input Signal, CML
3
IN-
DIN
Inverted Input Signal, CML
4
VREF
VREF
Reference Voltage for LOS Threshold Setting
5
TH
LOSLVL
6
GND
GND
Ground
7
LOS
LOS
Loss-of-Signal, Open Collector. LOS is high when the level of the input signal drops
below the preset threshold set by the TH input. LOS is deasserted low when the signal
level is above the threshold.
8
OUT-
DOUT
9
OUT+
DOUT
10
VCC
VCC
PIN
FUNCTION
Disable Function Pin. The data outputs are held static when this pin is asserted high,
transistor-to-transistor logic (TTL).
Loss-of-Signal Level Set. A voltage on this pin created by a two-resistor divider sets
the threshold level. Connect one resistor from this pin to VCC and another from this pin
to VREF (see Figure 5).
Inverted Data Output, CML
Noninverted Data Output, CML
Positive Power Supply
Detailed Description
The limiting amplifiers consist of a multistage amplifier,
offset-correction circuitry, an output buffer, and loss-ofsignal detect circuitry (see the Functional Diagram).
Input Stage
MAX3747
MAX3747A
The input stage is shown in Figure 3. It provides 50Ω
termination to VREF for each input signal, IN+ and IN-.
The MAX3747/MAX3747A should be AC-coupled.
VCC
Multistage Amplifier
The high-bandwidth multistage amplifier provides
approximately 57dB of gain for the MAX3747 and 61dB
of gain for the MAX3747A.
ESD
STRUCTURES
Offset Correction Loop
The MAX3747/MAX3747A are susceptible to DC offsets
in the signal path because they have high gain. In communication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or generated in the transimpedance amplifier appears as an
input offset and is reduced by the offset correction loop.
The offset correction loop sets a low-frequency cutoff of
3.2kHz.
50Ω
50Ω
VREF
Figure 3. CML Input Stage
_______________________________________________________________________________________
7
MAX3747/MAX3747A
Pin Description
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
MAX3747/MAX3747A
Functional Diagram
VCC
MAX3747
MAX3747A
50Ω
50Ω
DIGITAL
OFFSET
CORRECTION
OUT+
OUT-
IN+
IN-
50Ω
DISABLE
50Ω
VREF
VREF
SIGNAL DETECT
VREF
TH
LOS
R1
R2
R1 + R2 ≥ 5kΩ
VCC
CML Output Buffer
The CML outputs of the MAX3747/MAX3747A limiting
amplifiers provide high tolerance to impedance mismatches and inductive connectors. The output current
is approximately 10mA for the MAX3747 and 16mA for
the MAX3747A. Connecting the DISABLE pin to VCC
disables the output. If the LOS pin is connected to the
DISABLE pin, the outputs OUT+ and OUT- are at a static voltage (squelch) whenever the input signal level
drops below the LOS threshold. The output buffer can
be AC- or DC-coupled to the load (Figure 4).
The MAX3747 output is 500mVP-P and the MAX3747A
output is 800mVP-P.
VCC
50Ω
50Ω
OUT+
OUTDISABLE
Q3
Q4
Q1
Q2
ESD
STRUCTURES
DATA
DISABLE
DISABLE
Figure 4. CML Output Buffer
8
_______________________________________________________________________________________
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
VCC
Applications Information
Program the LOS Assert Threshold
Program the LOS assert threshold according to Figure
5. The combination of R1 and R2 should be greater
than or equal to 5kΩ, see the Assert/Deassert vs. VTH
graph in the Typical Operating Characteristics.
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors CIN
and COUT should be selected to minimize the receiver’s deterministic jitter. Jitter is decreased as the input
low-frequency cutoff (fIN) is decreased:
fIN = 1 / [2π(50)(CIN)]
For all applications, the recommended value for CIN and
COUT is 0.1µF, which provides fIN equal to 32kHz. Refer
to Application Note HFAN-1.1: Choosing AC-Coupling
Capacitors on the Maxim website (www.maxim-ic.com).
EMI Performance
The MAX3747/MAX3747A have been designed for better EMI performance. To help reduce EMI, special care
has been taken to produce symmetrical signal outputs.
R1
TH
Pin Configuration
R2
VREF
TOP VIEW
DISABLE 1
VTH = (R1 x (VREF - VCC)) / (R2 + R1)
VTH IS VCC REFERENCED
R1 + R2 ≥ 5kΩ
IN+
Figure 5. MAX3747/MAX3747A LOS Threshold Circuit
VCC
10 VCC
2
MAX3747
MAX3747A
9
OUT+
8
OUT-
IN-
3
VREF
4
7
LOS
TH
5
6
GND
µMAX
Chip Information
LOS
TRANSISTOR COUNT: 443
PROCESS: SiGe Bipolar
ESD
STRUCTURE
Figure 6. MAX3747/MAX3747A LOS Output Circuit
_______________________________________________________________________________________
9
MAX3747/MAX3747A
Loss-of-Signal Indicator
The MAX3747/MAX3747A are equipped with LOS circuitry that indicates when the input signal is below a programmable threshold, set by a voltage on the TH pin
(see the Typical Operating Characteristics). The voltage
on the TH pin is set by two resistors, one connecting
from the TH pin to VCC and the other connecting from TH
to VREF (Figure 5). An RMS power detector compares
the input signal amplitude with this threshold and feeds
the signal-detect information to the LOS output, which
is open collector. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hysteresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level. Figure 6 shows the
LOS output circuit.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
e
10LUMAX.EPS
MAX3747/MAX3747A
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
4X S
10
10
INCHES
H
0 0.50±0.1
0.6±0.1
1
1
0.6±0.1
BOTTOM VIEW
TOP VIEW
D2
MILLIMETERS
MAX
DIM MIN
0.043
A
0.006
A1
0.002
A2
0.030
0.037
0.120
D1
0.116
0.118
0.114
D2
0.116
0.120
E1
0.118
E2
0.114
0.199
H
0.187
L
0.0157 0.0275
L1
0.037 REF
b
0.007
0.0106
e
0.0197 BSC
c
0.0035 0.0078
0.0196 REF
S
α
0°
6°
MAX
MIN
1.10
0.15
0.05
0.75
0.95
3.05
2.95
3.00
2.89
3.05
2.95
2.89
3.00
4.75
5.05
0.40
0.70
0.940 REF
0.177
0.270
0.500 BSC
0.090
0.200
0.498 REF
0°
6°
E2
GAGE PLANE
A2
c
A
b
A1
α
E1
L
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0061
REV.
I
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.