MX29F200T/B
2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
FEATURES
•
•
•
•
•
•
•
•
•
5.0V±10% for read, erase and write operation
131072x16/262144x8 switchable
Fast access time: 55/70/90/120ns
Low power consumption
- 40mA maximum active current@5MHz
- 1uA typical standby current
Command register architecture
- Byte/Word Programming (7us/12us typical)
- Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and
64K-Byte x3)
Auto Erase (chip) and Auto Program
- Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
- Automatically program and verify data at specified
address
Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
Ready/Busy pin(RY/BY)
- Provides a hardware method or detecting program
or erase cycle completion
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
- Superior inadvertent write protection
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/
12V system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 44-pin SOP
- 48-pin TSOP
• Erase suspend/ Erase Resume
- Suspends an erase operation to read data from, or
program data to a sector that is not being erased, then
resume the erase operation.
• Hardware RESET pin
- Resets internal state mechine to the read mode
• 20 years data retention
GENERAL DESCRIPTION
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maximum EPROM compatibility.
The MX29F200T/B is a 2-mega bit, single 5 Volt Flash
memory organized as 1M word x16 or 2M bytex8 MXIC's
Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory.
The MX29F200T/B is packaged in 44-pin SOP and 48pin TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
The standard MX29F200T/B offers access time as fast
as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the
MX29F200T/B has separate chip enable (CE) and output
enable (OE ) controls.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F200T/B uses a 5.0V ± 10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F200T/B uses a command register to manage this
functionality. The command register allows for 100%
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0549
REV. 1.3, DEC. 24, 2001
1
MX29F200T/B
PIN CONFIGURATIONS
44 SOP(500mil)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MX29F200T/B
NC
RY/BY
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
48 TSOP(TYPE I) (12mm x 20mm)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX29F200T/B
(NORMAL TYPE)
MX29F200T/B
(REVERSE TYPE)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
NC
A7
A6
A5
A4
A3
A2
A1
PIN DESCRIPTION
SYMBOL
A0-A16
Q0-Q14
Q15/A-1
CE
OE
RESET
WE
RY/BY
BYTE
VCC
GND
NC
PIN NAME
Address Input
Data Input/Output
Q15(Word mode)/LSB addr.(Byte mode)
Chip Enable Input
Output Enable Input
Hardware Reset Pin, Active low
Write Enable Input
Read/Busy Output
Word/Byte Selection Input
Power Supply Pin (+5V)
Ground Pin
Pin Not Connected Internally
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
2
MX29F200T/B
SECTOR STRUCTURE
MX29F200T Top Boot Sector Addresses Tables
Sector Size Address Range (in hexadecimal)
(Kbytes/
SA0
SA1
SA2
SA3
SA4
SA5
SA6
A16
A15
A14
A13
A12
Kwords)
(x8)Address Range
(x16) Address Range
0
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
0
1
1
1
X
X
X
X
0
0
1
X
X
X
X
0
1
X
64/32
64/32
64/32
32/16
8/4
8/4
16/8
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-37FFFh
38000h-39FFFh
3A000h-3BFFFh
3C000h-3FFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1BFFFh
1C000h-1CFFFh
1D000h-1DFFFh
1E000h-1FFFFh
MX29F200B Bottom Boot Sector Addresses Tables
Sector Size
Address Range (in hexadecimal)
(Kbytes/
A16
A15
A14
A13
A12
Kwords)
(x8)Address Range
(x16) Address Range
SA0
0
0
0
0
X
16/8
00000h-03FFFh
00000h-01FFFh
SA1
0
0
0
1
0
8/4
04000h-05FFFh
02000h-02FFFh
SA2
0
0
0
1
1
8/4
06000h-07FFFh
03000h-03FFFh
SA3
0
0
1
X
X
32/16
08000h-0FFFFh
04000h-07FFFh
SA4
0
1
X
X
X
64/32
10000h-1FFFFh
08000h-0FFFFh
SA5
1
0
X
X
X
64/32
20000h-2FFFFh
10000h-17FFFh
SA6
1
1
X
X
X
64/32
30000h-3FFFFh
18000h-1FFFFh
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
3
MX29F200T/B
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
PROGRAM/ERASE
STATE
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
A0-A16
BUFFER
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
STATE
MX29F200T/B
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
A-1/Q15
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q14
I/O BUFFER
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
4
MX29F200T/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F200T/B is byte programmable using the
Automatic Programming algorithm. The Automatic Programming algorithm does not require the system to time
out sequence or verify the data programmed. The
typical chip programming time of the MX29F200T/B at
room temperature is less than 2 seconds.
AUTOMATIC CHIP ERASE
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifies the erase and counts the number of sequences.
A status bit toggling between consecutive read cycles
provides feedback to the user as to the status of the
programming operation.
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than two second. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
internally controlled by the device.
Register contents serve as inputs to an internal statemachine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches addresses and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F200T/B
electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
AUTOMATIC SECTOR ERASE
The MX29F200T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are internally controlled by the device.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is complete,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, verifies the program, and counts the number of sequences. A status bit
similar to DATA polling and a status bit toggling between
consecutive read cycles, provides feedback to the user
as to the status of the programming operation.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
5
MX29F200T/B
TABLE1. SOFTWARE COMMAND DEFINITIONS
Command
Reset
Read
Read Silicon ID
Sector Protect
First Bus
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Addr
1
XXXH F0H
Data
Addr
Data
Addr
Data
Addr
Data
2AAH 55H
555H
90H
ADI
DDI
AAAH 90H
ADI
DDI
(SA)
XX00H
X02H
XX01H
(SA)
00
X04H
01
PD
1
RA
RD
Word
4
555H
AAH
Byte
4
AAAH AAH
555H
Word
4
555H
2AAH 55H
555H
Byte
4
AAAH AAH
555H
AAAH 90H
AAH
55H
90H
Verify
Porgram
Chip Erase
Sector Erase
Word
4
555H
AAH
55H
2AAH 55H
555H
A0H
PA
Data
Addr
Data
Byte
4
AAAH AAH
555H
AAAH A0H
PA
PD
Word
6
555H
2AAH 55H
555H
80H
555H
AAH
2AAH 55H
555H 10H
Byte
6
AAAH AAH
555H
AAAH 80H
AAAH
AAH
555H
AAAH 10H
Word
6
555H
2AAH 55H
555H
555H
AAH
2AAH 55H
SA
30H
555H
AAAH 80H
AAAH
AAH
555H
SA
30H
555H
555H
AAH
2AAH 55H
Byte
AAH
AAH
6
AAAH AAH
Sector Erase Suspend
1
XXXH B0H
Sector Erase Resume
1
XXXH 30H
Unlock for sector
6
555H
AAH
55H
Addr
55H
55H
2AAH 55H
80H
80H
55H
55H
555H 20H
protect/unprotect
NOTE:
1. ADI = Address of Device identifier; A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to Table 3)
DDI = Data of Device identifier : C2H for manufacture code,51H/57H(x8) and 2251H/2257H(x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A16 in either state.
4. For Sector Protection Verify Operation : If read out data is 01H, it means the sector has been protected. If read out data is
00H, it means the sector is still not being protected.
COMMAND DEFINITIONS
command sequences. Note that the Erase Suspend
(B0H) and Erase Resume (30H) commands are valid
only while the Sector Erase operation is in progress.
Either of the two reset command sequences will reset
the device(when applicable).
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
6
MX29F200T/B
TABLE 2. MX29F200T/B BUS OPERATION
Pins
Mode
Read Silicon ID
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
Read
Standby
Output Disable
Write
Sector Protect with 12V
system(6)
Chip Unprotect with 12V
system(6)
Verify Sector Protect
with 12V system
Sector Protect without 12V
system (6)
Chip Unprotect without 12V
system (6)
Verify Sector Protect/
Unprotect without 12V
system (7)
Reset
CE
OE
WE
A0
A1
A6
A9
Q0 ~ Q15
L
L
H
L
L
X
VID(2)
L
L
H
H
L
X
VID(2)
L
H
L
L
X
H
H
X
H
A0
X
X
A1
X
X
A6
X
X
A9
X
X
C2H(Byte mode)
00C2H(Word mode)
51H/57H(Byte mode)
2251H/2257H(Word mode)
DOUT
HIGH Z
HIGH Z
L
L
H
L
VID(2) L
A0
X
A1
X
A6
L
A9
VID(2)
DIN(3)
X
L
VID(2) L
X
X
H
VID(2)
X
L
L
H
X
H
X
VID(2)
Code(5)
L
H
L
X
X
L
H
X
L
H
L
X
X
H
H
X
L
L
H
X
H
X
H
Code(5)
X
X
X
X
X
X
X
HIGH Z
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H/0000H means unprotected.
Code=01H/0001H means protected.
A16~A12=Sector address for sector protect.
6. Refer to sector protect/unprotect algorithm and waveform.
Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system"
command.
7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V
system" command.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
7
MX29F200T/B
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command
must then be written to place the device in the desired
state.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify begin.
The erase and verify operations are completed when the
data on Q7 is "1" at which time the device returns to the
Read mode. The system does not require to provide
any control or timing during these operations.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto address lines is not generally desired
system design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase-verified command is required).
The MX29F200T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read
silicon ID command sequence into the command register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of 51H/2251H for MX29F200T, 57H/2257H
for MX29F200B.
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating an erase operation exceed
internal timing limit.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
Manufacture code
A0
A1
Q15~Q8 Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Code(Hex) Code
Word
VIL
VIL
00H
1
1
0
0
0
0
1
0
00C2H
Byte
VIL
VIL
X
1
1
0
0
0
0
1
0
C2H
Device code
Word
VIH
VIL
22H
0
1
0
1
0
0
0
1
2251H
for MX29F200T
Byte
VIH
VIL
X
0
1
0
1
0
0
0
1
51H
Device code
Word
VIH
VIL
22H
0
1
0
1
0
1
1
1
2257H
for MX29F200B
Byte
VIH
VIL
X
0
1
0
1
0
1
1
1
57H
Sector Portection
X
VIH
X
0
0
0
0
0
0
0
1
01H(Protected)
Verification
X
VIH
X
0
0
0
0
0
0
0
0
00H(Unprotected)
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REV. 1.3 , DEC. 24, 2001
8
MX29F200T/B
SECTOR ERASE COMMANDS
ERASE SUSPEND
The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.
This command is only valid while the state machine is
executing Automatic Sector Erase operation, and
therefore will only be responded to period during Automatic
Sector Erase operation. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. After this command has been executed, the
command register will initiate erase suspend mode. The
state machine will return to read mode automatically after
suspend is ready. At this time, state machine only allows
the command register to respond to the Read Memory
Array, Erase Resume and Program commands.
When the sector(s) is automatically verified to contain an
all-zero pattern, a self-timed sector erase and verification
begin. The erase and verification operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system does
not require to provide any control or timing during these
operations.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended sectors.
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase-verified command is required). Sector erase
is a six-bus cycle operation. There are two "unlock" write
cycles. These are followed by writing the set-up command
80H. Two more "unlock" write cycles are then followed
by the sector erase command 30H. The sector address
is latched on the falling edge of WE, while the
command(data) is latched on the rising edge of WE.
Sector addresses selected are loaded into internal register
on the sixth falling edge of WE. Each successive sector
load cycle started by the falling edge of WE must begin
within 30us from the rising edge of the preceding WE.
Otherwise, the loading period ends and internal auto
sector erase cycle starts. (Monitor Q3 to determine if the
sector erase timer window is still open, see section Q3,
Sector Erase Timer.) Any command other than Sector
Erase (30H) or Erase Suspend (B0H) during the timeout period resets the derice to read mode.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
9
MX29F200T/B
Table 4. Write Operation Status
Status
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
Q7
Note1
Q6
Q5
Note2
Q3
Q2
RY/BY
Q7
Toggle
0
N/A
No
Toggle
0
0
Toggle
0
1
Toggle
0
1
No
Toggle
0
N/A Toggle
1
In Progress
Erase Suspended Mode
Erase Suspend Read
Data
(Non-Erase Suspended Sector)
Erase Suspend Program
Byte Program in Auto Program Algorithm
Exceeded
Time Limits
Auto Erase Algorithm
Erase Suspend Program
Data
Data Data Data
1
Q7
Toggle
0
N/A
N/A
0
Q7
Toggle
1
N/A
No
Toggle
0
0
Toggle
1
1
Toggle
0
Q7
Toggle
1
N/A
N/A
0
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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10
MX29F200T/B
WRITE OPERATION STATUS DATA
POLLING-Q7
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
The MX29F200T/B also features Data Polling as a
method to indicate to the host system that the Automatic
Program or Erase algorithms are either in progress or
completed.
While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WE pulse of the four write pulse
sequences for automatic program.
SET-UP AUTOMATIC PROGRAM
COMMANDS
To initiate Automatic Program mode, A three-cycle
command sequence is required. There are two "unlock"
write cycles. These are followed by writing the Automatic
Program command A0H.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE pulse of six write pulse sequences
for automatic chip/sector erase.
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the rising
edge of the WE pulse. The rising edge of WE also begins
the programming operation. The system does not
require to provide further controls or timings. The device
will automatically provide an adequate internally
generated program pulse and verify margin.
The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).
RY/BY:Ready/Busy
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE pulse in the command
sequence. Since RY/BY is an open-drain output, several
RY/BY pins can be tied together in parallel with a pull-up
resistor to Vcc.
If the outputs is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the
device is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
11
MX29F200T/B
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sectors and mode information.
Refer to Table 4 to compare outputs for Q2 and Q6.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE pulse in the
command sequence(prior to the program or erase
operation), and during the sector time-out.
During an Automatic Program or Erase algorithm
operation, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles. When the operation is complete,
Q6 stops toggling.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read
cycle.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Q6 toggles
and returns to reading array data. If not all selected
sectors are protected, the Automatic Erase algorithm
erases the unprotected sectors, and ignores the selected
sectors that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic
Erase algorithm is in progress), Q6 toggling. When the
device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If
the toggle bit is no longer toggling, the device has
successfuly completed the program or erase operation.
If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status
of the operation.
Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is, the
Automatic Erase alorithm is in process), or whether that
sector is erase-suspended. Toggle Bit I is valid after the
rising edge of the final WE pulse in the command
sequence.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
12
MX29F200T/B
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
which indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use the
other active sectors in the device.
DATA PROTECTION
The MX29F200T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific command sequences. The device also
incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and powerdown transition or system noise.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector maynot
be reused, (other sectors are still functional and can be
reused).
TEMPORARY SECTOR UNPROTECT
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incorrectly
used.
This feature allows temporary unprotection of previously
protected sector to change data in-system. The Temporary Sector Unprotect mode is activated by setting the
RESET pin to VID(11.5V-12.5V). During this mode,
formerly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin,all the previously protected sectors are
protected again.
WRITE PULSE "GLITCH" PROTECTION
Q3
Sector Erase Timer
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
13
MX29F200T/B
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.
SECTOR PROTECTION WITH 12V SYSTEM
SECTOR PROTECTION WITHOUT 12V
SYSTEM
The MX29F200T/B features hardware sector protection.
This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and control pin OE, (suggest VID = 12V)
A6 = VIL and CE = VIL.(see Table 2) Programming of
the protection circuitry begins on the falling edge of the
WE pulse and is terminated on the rising edge. Please
refer to sector protect algorithm and waveform.
The MX29F200T/B also feature a hardware sector
protection method in a system without 12V power suppply.
The programming equipment do not need to supply 12
volts to protect sectors. The details are shown in sector
protect algorithm and waveform.
CHIP UNPROTECT WITHOUT 12V SYSTEM
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
a protected sector. Otherwise the device will produce
00H for the unprotected sector. In this mode, the
addresses,except for A1, are in "don't care" state.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes.(Read Silicon ID)
The MX29F200T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.
POWER-UP SEQUENCE
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
The MX29F200T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command
sequences.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F200T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.
To activate this mode, the programming equipment
must force VID on control pin OE and address pin A9.
The CE pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the WE pulse and is terminated on the rising edge .
It is also possible to determine if the chip is unprotected
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
14
MX29F200T/B
Temporary Sector Unprotect Operation
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
15
MX29F200T/B
TEMPORARY SECTOR UNPROTECT
Parameter Std. Description
Test Setup
AllSpeed Options Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET Setup Time for Temporary Sector Unprotect
Min
4
us
Note:
Not 100% tested
Temporary Sector Unprotect Timing Diagram
12V
RESET
0 or 5V
0 or 5V
Program or Erase Command Sequence
tVIDR
tVIDR
CE
WE
tRSP
RY/BY
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
16
MX29F200T/B
Parameter Std
Description
Test Setup All Speed Options Unit
tREADY1
RESET PIN Low (During Automatic Algorithms)
MAX
20
us
MAX
500
ns
to Read or Write (See Note)
tREADY2
RESET PIN Low (NOT During Automatic
Algorithms) to Read or Write (See Note)
tRP1
RESET Pulse Width (During Automatic Algorithms)
MIN
10
us
tRP2
RESET Pulse Width (NOT During Automatic Algorithms) MIN
500
ns
tRH
RESET High Time Before Read(See Note)
MIN
0
ns
tRB1
RY/BY Recovery Time(to CE, OE go low)
MIN
0
ns
tRB2
RY/BY Recovery Time(to WE go low)
MIN
50
ns
Note:Not 100% tested
RESET TIMING WAVFORM
RY/BY
CE, OE
tRH
RESET
tRP2
tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY
tRB1
CE, OE
WE
tRB2
RESET
tRP1
Reset Timing during Automatic Algorithms
P/N:PM0549
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17
MX29F200T/B
NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period may affect reliability.
ABSOLUTE MAXIMUM RATINGS
RATING
Ambient Operating Temperature
Ambient Temperature with Power
Applied
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9&OE
VALUE
-40oC to 85oC
-55oC to 125oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are
subject to change.
DC/AC Operating Conditions for Read Operation
Operating Temperature
Commercial
Industrial
Automotive
Vcc Power Supply
-55
0oCto 70oC
5V±5%
MX29F200T/B
-70
-90
-12
o
o
o
o
0 Cto 70 C
0 Cto 70 C
0oCto 70oC
-40oCto 85oC -40oCto 85oC -40oCto 85oC
-40oC to 125oC -40oC to 125oC
5V±10%
5V±10%
5V±10%
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN1
CIN2
COUT
PARAMETER
Input Capacitance
Control Pin Capacitance
Output Capacitance
MIN.
TYP
P/N:PM0549
MAX.
8
12
12
UNIT
pF
pF
pF
CONDITIONS
VIN = 0V
VIN = 0V
VOUT = 0V
REV. 1.3 , DEC. 24, 2001
18
MX29F200T/B
READ OPERATION
DC CHARACTERISTICS
Symbol
ILI
ILO
ISB1
ISB2
ICC1
ICC2
VIL
VIH
VOL
VOH1
VOH2
PARAMETER
Input Leakage Current
Output Leakage Current
Standby VCC current
MIN.
TYP
1(Note5)
Operating VCC current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage(TTL)
Output High Voltage(CMOS)
-0.3(Note1)
2.0
MAX.
1(Note3)
10
1
5(Note5)
40(Note4)
50
VCC+0.3
0.45
2.4
VCC-0.4
UNIT
uA
uA
mA
uA
mA
mA
0.8
V
V
V
V
CONDITIONS
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
CE = VCC + 0.3V
IOUT = 0mA, f=5MHz
IOUT = 0mA, f=10MHz
V
IOL = 2.1mA
IOH = -2mA
IOH = -100uA,VCC=VCC MIN
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to ot less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. ILI=10uA for Industrial Grade.
4. ICC1=45mA for Industrial Grade.
5. ISB2 maximum 20uA for automative grade.
P/N:PM0549
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19
MX29F200T/B
AC CHARACTERISTICS
29F200T/B-55
SYMBOL PARAMETER
MIN.
29F200T/B-70
MAX.
MIN.
MAX.
UNIT
CONDITIONS
tACC
Address to Output Delay
55
70
ns
CE=OE=VIL
tCE
CE to Output Delay
55
70
ns
OE=VIL
40
ns
CE=VIL
20
ns
CE=VIL
ns
CE=OE=VIL
tOE
OE to Output Delay
tDF
OE High to Output Float (Note1)
0
20
tOH
Address to Output hold
0
20
0
0
29F200T/B-90
SYMBOL PARAMETER
MIN.
29F200T/B-12
MAX.
UNIT
CONDITIONS
tACC
Address to Output Delay
90
120
ns
CE=OE=VIL
tCE
CE to Output Delay
90
120
ns
OE=VIL
tOE
OE to Output Delay
40
50
ns
CE=VIL
tDF
OE High to Output Float (Note1)
0
tOH
Address to Output hold
0
MAX.
MIN.
30
0
30
0
TEST CONDITIONS:
• Input pulse levels: 0.45V/2.4V for 70ns max, 0V/3V for
55ns
• Input rise and fall times: is equal to or less than 10ns
for 70ns max,5ns for 55ns
• Output load: 1 TTL gate + 100pF (Including scope and
jig) for 70ns max.
:1TTLgate+30pF for 55ns max.
• Reference levels for measuring timing: 0.8V, 2.0V for
70ns max.;1.5V for 55ns
ns
CE=VIL
ns
CE=OE=VIL
NOTE:
1.tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
READ TIMING WAVEFORMS
VIH
ADD Valid
A0~16
VIL
tCE
VIH
CE
VIL
WE
VIH
OE
VIH
tACC
VIL
DATA
Q0~7
tDF
tOE
VIL
VOH
HIGH Z
tOH
DATA Valid
HIGH Z
VOL
P/N:PM0549
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20
MX29F200T/B
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC/AC Operating Conditions for Programming/Erase Operation
Operating Temperature
Commercial
Industrial
Automotive
Vcc Power Supply
-55
0oC to 70oC
5V±5%
MX29F200T/B
-70
-90
-12
o
o
o
o
0 C to 70 C
0 C to 70 C
0oC to 70oC
-40oC to 85oC -40oC to 85oC -40oC to 85oC
-40oC to 125oC -40oC to 125oC
5V±10%
5V±10%
5V±10%
DC CHARACTERISTICS
SYMBOL
PARAMETER
ICC1 (Read)
Operating VCC Current
MIN.
TYP
MAX.
UNIT
CONDITIONS
40(Note5)
mA
IOUT=0mA, f=5MHz
ICC2
50
mA
IOUT=0mA, F=10MHz
ICC3 (Program)
50
mA
In Programming
50
mA
In Erase
mA
CE=VIH, Erase Suspended
ICC4 (Erase)
ICCES
VCC Erase Suspend Current
2
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is
the sum of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
5. ICC1 (Read)=45mA for Industrial Grade.
P/N:PM0549
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21
MX29F200T/B
AC CHARACTERISTICS
29F200T/B-55(Note2)
29F200T/B-70
SYMBOL PARAMETER
MIN.
MIN.
tOES
OE setup time
0
0
ns
tCWC
Command programming cycle
70
70
ns
tCEP
WE programming pulse width
45
45
ns
tCEPH1
WE programming pluse width High
20
20
ns
tCEPH2
WE programming pluse width High
20
20
ns
tAS
Address setup time
0
0
ns
tAH
Address hold time
45
45
ns
tDS
Data setup time
20
30
ns
tDH
Data hold time
0
0
ns
tCESC
CE setup time before command write
0
0
ns
tDF
Output disable time (Note 1)
30
ns
tAETC
Total erase time in auto chip erase
3(TYP.)
24
3(TYP.)
24
s
tAETB
Total erase time in auto sector erase
1(TYP.)
8
1(TYP.)
8
s
tAVT
Total programming time in auto verify
7/12(TYP.)
210/360
7/12(TYP.)
210/360
us
MAX.
20
MAX.
UNIT
tBAL
Sector address load time
100
100
us
tCH
CE Hold Time
0
0
ns
tCS
CE setup to WE going low
0
0
ns
tVLHT
Voltge Transition Time
4
4
us
tOESP
OE Setup Time to WE Active
4
4
us
tWPP
Write pulse width for sector protect
10
10
us
tWPP2
Write pulse width for sector unprotect
12
12
ms
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2.Under condition of VCC=5V±5%,CL=30pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
22
MX29F200T/B
AC CHARACTERISTICS
29F200T/B-90
29F200T/B-120
SYMBOL PARAMETER
MIN.
MIN.
tOES
OE setup time
0
0
ns
tCWC
Command programming cycle
90
120
ns
tCEP
WE programming pulse width
45
50
ns
tCEPH1
WE programming pluse width High
20
20
ns
tCEPH2
WE programming pluse width High
20
20
ns
tAS
Address setup time
0
0
ns
tAH
Address hold time
45
50
ns
tDS
Data setup time
45
50
ns
tDH
Data hold time
0
0
ns
tCESC
CE setup time before command write
0
0
ns
tDF
Output disable time (Note 1)
40
ns
tAETC
Total erase time in auto chip erase
3(TYP.)
24
3(TYP.)
24
s
tAETB
Total erase time in auto sector erase
1(TYP.)
8
1(TYP.)
8
s
tAVT
Total programming time in auto verify
7/12(TYP.)
210/360
7/12(TYP.)
210/360
us
MAX.
40
MAX.
UNIT
tBAL
Sector address load time
100
100
us
tCH
CE Hold Time
0
0
ns
tCS
CE setup to WE going low
0
0
ns
tVLHT
Voltge Transition Time
4
4
us
tOESP
OE Setup Time to WE Active
4
4
us
tWPP
Write pulse width for sector protect
10
10
us
tWPP2
Write pulse width for sector unprotect
12
12
ms
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2.Under condition of VCC=5V±5%,CL=30pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
23
MX29F200T/B
SWITCHING TEST CIRCUITS
1.6K ohm
DEVICE UNDER
TEST
+5V
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance for 70ns max.
CL= 30pF Including jig capacitance for 55ns max.
SWITCHING TEST WAVEFORMS(I) for 29F200T/B-70, 29F200T/B-90, 29F200T/B-12
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 10ns.
SWITCHING TEST WAVEFORMS(II) for 29F200T/B-55
3.0V
TEST POINTS
1.5V
1.5V
0V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
24
MX29F200T/B
COMMAND WRITE TIMING WAVEFORM
VCC
5V
ADDRESS
A0~16
VIH
WE
VIH
ADD Valid
VIL
tAH
tAS
VIL
tOES
tCEPH1
tCEP
tCWC
CE
VIH
VIL
tCS
OE
VIL
DATA
Q0-7
tCH
VIH
tDS
tDH
VIH
DIN
VIL
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
25
MX29F200T/B
AUTOMATIC PROGRAMMING TIMING
WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle
bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after
programming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform).
AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A16
A0~A10
ADD Valid
2AAH
555H
tAS
WE
ADD Valid
555H
tCWC
tAH
tCEPH1
tCESC
tAVT
CE
tCEP
OE
tDS
Q0~Q2
tDH
Command In
tDF
Command In
Command In
DATA
Data In
DATA polling
,Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command #55H
Command #A0H
(Q0~Q7)
DATA
Data In
DATA
tOE
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
26
MX29F200T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
Verify Byte Ok
YES
NO
.
Q5 = 1
Auto Program Completed
YES
Reset
Auto Program Exceed
Timing Limit
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
27
MX29F200T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs 0 during erasure
and 1 after erasure 0n Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A16
A0~A10
2AAH
555H
555H
555H
tAS
WE
2AAH
555H
tCWC
tAH
tCEPH1
tAETC
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
Q7
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Command #AAH
Command #55H
Command #80H
Command #AAH
Command #55H
Command #10H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
28
MX29F200T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
DATA Polling
Q7 = 1
YES
NO
.
Q5 = 1
Auto Chip Erase Completed
YES
Reset
Auto Chip Erase Exceed
Timing Limit
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
29
MX29F200T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A12 to A16 are erased. External
erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completion can be verified by DATA polling and toggle
bit checking after automatic erase starts. Device outputs
0 during erasure and 1 after erasure on Q7.(Q6 is for
toggle bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
Sector
Address0
A12~A16
A0~A10
555H
2AAH
555H
555H
Sector
Address1
Sector
Addressn
2AAH
tAS
tCWC
tAH
WE
tCEPH1
tBAL
tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q4(Note 1)
Q7
DATA polling
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H
(Q0~Q7)
Command
In
Command #30H
Command
In
Command #30H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
30
MX29F200T/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking
Q6 Toggled ?
NO
Invalid Command
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
Time-out Bit
Checking Q3=1 ?
NO
YES
Toggle Bit Checking
NO
Q6 not Toggled
YES
NO
Q5 = 1
DATA Polling
Q7 = 1
.
YES
Reset
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
31
MX29F200T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
Continue Erase
Another
Erase Suspend ?
NO
.
YES
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
32
MX29F200T/B
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 1
WE
tOESP
CE
Data
01H
tOE
A16-A12
Sector Address
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
tVLHT
A6
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
tOESP
CE
Data
00H
tOE
A16-A12
Sector Address
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
33
MX29F200T/B
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Set Up Sector Addr
(A16,A15,A14,A13,A12)
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Device Failed
Yes
Protect Another
.
Yes
Sector?
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
34
MX29F200T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Protect All Sectors
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device
No
Data=00H?
Increment
Sector Addr
Yes
No
No
PLSCNT=1000?
Yes
Device Failed
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect the whole chip, all sectors should be protected in advance.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
35
MX29F200T/B
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
Don't care
(Note 2)
01H
F0H
tOE
A16-A12
Sector Address
Note1: Must issue "unlock for sector protect/unprotect" command before sector protection
for a system without 12V provided.
Note2: Except F0H
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
36
MX29F200T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
Don't care
(Note 2)
00H
F0H
tOE
Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection
for a system without 12V provided.
Note2: Except F0H
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
37
MX29F200T/B
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for sector protect/unprotect"
Command(Table1)
Set Up Sector Addr
(A16,A15,A14,A13,A12)
OE=VIH,A9=VIH
CE=VIL,A6=VIL
Activate WE Pulse to start
Data don't care
Toggle bit checking
DQ6 not Toggled
No
Yes
Increment PLSCNT
Set CE=OE=VIL
A9=VIH
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Device Failed
Yes
Protect Another
Sector?
Yes
.
No
Write Reset Command
Sector Protection
Complete
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
38
MX29F200T/B
SECTOR UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
Protect All Sectors
PLSCNT=1
Write "unlock for sector protect/unprotect"
Command (Table 1)
Set OE=A9=VIH
CE=VIL,A6=1
Activate WE Pulse to start
Data don't care
No
Toggle bit checking
DQ6 not Toggled
Increment
PLSCNT
Yes
Set OE=CE=VIL
A9=VIH,A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Increment
Sector Addr
PLSCNT=1000?
Yes
Yes
No
All sectors have
been verified?
Device Failed
Yes
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect the whole chip, all sectors should be protected in advance.
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
39
MX29F200T/B
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
ADD
VIH
VIL
A9
tACC
tACC
A1
VIH
VIL
ADD
A2-A8
A10-A17
CE
VIH
VIL
VIH
VIL
WE
VIH
tCE
VIL
OE
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q15
DATA OUT
DATA OUT
VIL
C2H/00C2H
51H/57H (Byte mode)
2251H/2257H (Word mode)
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
40
MX29F200T/B
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
TYP.(2)
MAX.(3)
UNITS
Sector Erase Time
1
8
s
Chip Erase Time
3
24
s
Byte Programming Time
7
210
us
Word Programming Time
12
360
us
Chip Programming Time
3.5
10.5
sec
PARAMETER
Erase/Program Cycles
Note:
MIN.
100,000
Cycles
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,5V.
3.Maximum values measured at 25°C,4.5V.
LATCHUP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
13.5V
Input Voltage with respect to GND on all I/O pins
-1.0V
Vcc + 1.0V
-100mA
+100mA
MIN.
UNIT
20
Years
Current
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
PARAMETER
Data Retention Time
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
41
MX29F200T/B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
MX29F200TMC-55
MX29F200TMC-70
MX29F200TMC-90
MX29F200TMC-12
MX29F200TTC-55
Access Time Operating Current Standby Current
(ns)
(mA)
MAX.(uA)
55
40
5
70
40
5
90
40
5
120
40
5
55
40
5
Temperature
Range
0oC~70oC
0oC~70oC
0oC~70oC
0oC~70oC
0oC~70oC
MX29F200TTC-70
70
40
5
0oC~70oC
MX29F200TTC-90
90
40
5
0oC~70oC
MX29F200TTC-12
120
40
5
0oC~70oC
MX29F200BMC-55
MX29F200BMC-70
MX29F200BMC-90
MX29F200BMC-12
MX29F200BTC-55
55
70
90
120
55
40
40
40
40
40
5
5
5
5
5
0oC~70oC
0oC~70oC
0oC~70oC
0oC~70oC
0oC~70oC
MX29F200BTC-70
70
40
5
0oC~70oC
MX29F200BTC-90
90
40
5
0oC~70oC
MX29F200BTC-12
120
40
5
0oC~70oC
MX29F200TMI-70
MX29F200TMI-90
MX29F200TMI-12
MX29F200TTI-70
70
90
120
70
45
45
45
45
5
5
5
5
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40 oC~85oC
MX29F200TTI-90
90
45
5
-40 oC~85oC
MX29F200TTI-12
120
45
5
-40 oC~85oC
MX29F200BMI-70
MX29F200BMI-90
MX29F200BMI-12
MX29F200BTI-70
70
90
120
70
45
45
45
45
5
5
5
5
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40 oC~85oC
MX29F200BTI-90
90
45
5
-40 oC~85oC
MX29F200BTI-12
120
45
5
-40 oC~85oC
MX29F200TTA-90
90
45
20
-40oC~125oC
MX29F200TTA-12
120
45
20
-40oC~125oC
P/N:PM0549
PACKAGE
44 Pin SOP
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
44 Pin SOP
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
REV. 1.3 , DEC. 24, 2001
42
MX29F200T/B
PACKAGE INFORMATION
48-PIN PLASTIC TSOP
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
43
MX29F200T/B
44-PIN PLASTIC SOP
P/N:PM0549
REV. 1.3 , DEC. 24, 2001
44
MX29F200T/B
REVISION HISTORY
Revision
Description
Page
Date
1.0
1.To remove "Advanced Information" datasheet marking and
contain information on products in full production
2.The modification summary of Revision 0.9.9 to Revision 1.0:
2-1.Program/erase cycle times:10K cycles-->100K cycles
2-2.To add data retention 20 years
2-3.Industrial grade range from "Read Mode" to "Full Range"
2-4.To remove A9 from "timing waveform for sector protection for
system without 12V"
To remove A9 from "timing waveform for chip unprotection for
system without 12V"
To modify "Package Information"
Add automotive Grade
Correct sector address SA2 from 11XXX to 10XXX
P1
DEC/20/1999
1.1
1.2
1.3
P/N:PM0549
P1,42
P1,42
P20,21,22,40
P35
P36
P42,43
JUN/15/2001
P18,19,21,41 NOV/12/2001
P3
DEC/24/2001
REV. 1.3 , DEC. 24, 2001
45
MX29F200T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.