ON MC100LVEL91DWR2G 3.3 v triple lvpecl input to -3.3 v to -5.0 v ecl output translator Datasheet

MC100LVEL91
3.3 V Triple LVPECL Input to
-3.3 V to -5.0 V ECL Output
Translator
Description
The MC100LVEL91 is a triple LVPECL input to ECL output
translator. The device receives low voltage differential PECL signals,
determined by the VCC supply level, and translates them to differential
−3.3 V to −5.0 V ECL output signals.
To accomplish the level translation the LVEL91 requires three
power rails. The VCC supply should be connected to the positive
supply, and the VEE pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
VEE and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. This condition will force the
Q output to a low, ensuring stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
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SOIC−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
MC100LVEL91
AWLYYWWG
1
A
WL
YY
WW
G
Features
• 620 ps Typical Propagation Delay
• The 100 Series Contains Temperature Compensation
• Operating Range: VCC = 3.8 V to 3.0 V;
VEE = −3.0 V to −5.5 V; GND = 0 V
• Q Output will Default LOW with Inputs Open or at GND
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
MC100LVEL91DWG
Package
Shipping†
SOIC−20 WB
(Pb-Free)
38 Units/Tube
MC100LVEL91DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 12
1
Publication Order Number:
MC100LVEL91/D
VCC
Q0
Q0
GND
Q1
Q1
GND
Q2
Q2
VCC
MC100LVEL91
20
19
18
17
16
15
14
13
12
11
ECL
6
D1
7
8
9
10
VEE
5
D2
4
D2
3
D1
PECL/
LVPECL
PECL VBB
2
D0
VCC
1
PECL/
LVPECL
D0
PECL/
LVPECL
Pin
Function
Dn, Dn
Qn, Qn
PECL VBB
VCC
VEE
GND
PECL/LVPECL Inputs
ECL Outputs
PECL Reference Voltage Output
Positive Supply
Negative Supply
Ground
ECL
PECL VBB
ECL
Table 1. PIN DESCRIPTION
Figure 1. SO−20 Pinout (Top View) and Logic Diagram
* All VCC pins are tied together on the die.
Warning: All VCC, VEE, and GND pins must be externally
connected to Power Supply to guarantee proper operation.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
75 kW
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, (Note 1):
Pb-Free
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
282 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100LVEL91
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Power Supply
Parameter
GND = 0 V
Condition 1
Condition 2
3.8
V
VEE
NECL Power Supply
GND = 0 V
−6.0
V
VI
PECL Input Voltage
GND = 0 V
3.8
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
PECL VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
SOIC−20 WB
90
60
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−20 WB
30 to 35
°C/W
Tsol
Wave Solder (Pb-Free)
265
°C
VI ≤ VCC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. LVPECL INPUT DC CHARACTERISTICS (VCC = 3.3 V; VEE = −3.3 V to −5.0 V; GND = 0 V (Note 1))
−40°C
Symbol
Min
Characteristic
25°C
Typ
Max
Min
85°C
Typ
Max
6
11
Typ
Max
Unit
11
mA
ICC
VCC Power Supply Current
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1490
1825
1490
1825
1490
1825
mV
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
LVPECL VBB
VIHCMR
11
Min
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 2)
VPP < 500 mV
VPP ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
D
D
V
1.0
1.2
2.9
2.9
0.9
1.1
2.9
2.9
150
0.5
−600
0.9
1.1
2.9
2.9
150
0.5
−600
150
mA
mA
0.5
−600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input parameters vary 1:1 with VCC. VCC can vary +0.5 / −0.3 V.
2. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
Table 5. NECL OUTPUT DC CHARACTERISTICS (VCC = 3.3 V; VEE = −3.3 V to −5.0 V; GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
25°C
Min
Typ
Max
Min
Typ
27
85°C
Max
Min
Typ
Max
Unit
IEE
VEE Power Supply Current
21
27
29
mA
VOH
Output HIGH Voltage (Note 2)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 2)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Output parameters vary 1:1 with GND. VCC can vary +0.3 V / −0.5 V.
2. All loading with 50 W resistor to GND − 2.0 V.
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MC100LVEL91
Table 6. AC CHARACTERISTICS (VCC = 3.3 V; VEE = −3.0 V to −5.5 V; GND = 0 V (Note 1))
−40°C
Symbol
Characteristic
fmax
Maximum Toggle Frequency
TPLH
Propagation Delay
Differential Configuration
D to Q
Select−Ended
tPHL
tSKEW
VPP
tr
tf
Min
Typ
25°C
Max
Min
600
490
440
Skew
Output−to−Output (Note 2)
Part−to−Part (Differential Configuration) (Note 2)
Duty Cycle (Differential Configuration) (Note 3)
Input Swing (Note 4)
200
Output Rise/Fall Times Q
(20% − 80%)
320
690
740
40
100
200
400
85°C
Max
Min
600
590
590
25
Typ
520
470
1000
200
580
320
720
770
40
100
200
400
Max
600
620
620
25
Typ
560
510
660
660
760
810
40
100
200
25
1000
200
580
320
400
Unit
MHz
ps
ps
1000
mV
580
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. VCC can vary +0.5 V / −0.3 V.
2. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
3. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
4. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈ 40.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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4
MC100LVEL91
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1642/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVEL91
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
c
T
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
DIM
A
A1
b
c
D
E
e
H
h
L
q
RECOMMENDED
SOLDERING FOOTPRINT*
20X
20X
1.30
0.52
20
11
11.00
1
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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