OKI ML63295A-XXXGA 4-bit microcontroller with built-in 3072-dot matrix lcd driver and melody circuit Datasheet

FEDL63295A-02
1Semiconductor
ML63295A
This version:
Jul. 2001
Previous version: Nov. 2000
4-Bit Microcontroller with Built-in 3072-Dot Matrix LCD Driver and Melody Circuit
GENERAL DESCRIPTION
The ML63295A is a CMOS 4-bit microcontroller that employs Oki’s original CPU core nX-4/250.
The ML63295A operates on a power supply voltage of 6 V.
With built-in 3072-dot matrix LCD drivers (96 SEG. × 32 COM.), the ML63295A is suited for applications such as
electronic dictionaries with an LCD.
FEATURES
• Extensive instruction set
439 instructions:
Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations,
bit operations, ROM table reference, external memory transfer, stack operations, flag operations, jump,
conditional branch, call/return, control
• Wide variety of addressing modes
Indirect addressing mode for 4 types of data memory with current bank register, extra bank register,
HL register and XY register
Data memory bank internal direct addressing mode
• Processing speed
2 clocks per machine cycle, with most instructions executed in 1 machine cycle
Minimum instruction execution time : 61 µs (@ 32.768 kHz system clock)
: 1 µs (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock : Crystal oscillation or RC oscillation selected with mask option
(30 kHz to 80 kHz)
High-speed clock: Ceramic oscillation or RC oscillation selected with software
(2 MHz max)
• Program memory space
32 K words
Basic instruction length is 16 bits/1word.
• Data memory space
2048 nibbles
• External data memory space
64 Kbytes (expandable furthermore by using the I/O ports)
• Stack level
Call stack level
Register stack level
: 16 levels
: 16 levels
1/38
FEDL63295A-02
1Semiconductor
ML63295A
• Ports
Input ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Output ports:
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/CMOS
output.
I/O ports:
Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/
CMOS output.
Can be interfaced with external peripherals that use a different power supply than this device uses.
Number of ports:
Input port
: 2 ports × 4 bits
Output port
: 6 ports × 4 bits
Input-output port
: 6 ports × 4 bits
• Melody output
Melody frequency
Tone length
Tempo
Melody data
Buzzer driver signal output
• LCD driver
Number of segments
Duty
Bias
Frame frequency
Contrast
Display modes
• Multiplier/divider circuit
Multiplier
Divider
: 529 Hz to 2979 Hz
: 63 varieties
: 15 varieties
: Stored in program memory
: 4 kHz
: 3072 Max. (96 SEG. × 32 COM.)
: Selectable as 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14, 1/16, 1/18, 1/20,
1/22, 1/24, 1/26, 1/28, 1/30, or 1/32 duty
: Selectable as 1/5 or 1/6 bias (regulator built-in)
: ex. 64 Hz (at 1/32 duty), 128 Hz (at 1/16 duty), 256 Hz (at 1/8
duty), 512 Hz (at 1/4 duty), 1024 Hz (at 1/2 duty)
: 16 levels adjustable
: Selectable as all-ON mode/all-OFF mode/power down
mode/normal display mode
: (8 bits) × (8 bits) → Product (16 bits)
: (16 bits)/(8 bits) → Quotient (16 bits), Remainder (8 bits)
• System reset function
System reset through RESET pin
System reset by power-on detection
System reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of
BLDCON).
LD1
LD0
Judgment voltage (V)
Remarks
1
0
4.5 ±0.1
Ta = 25°C
1
1
5.1 ±0.1
Ta = 25°C
2/38
FEDL63295A-02
1Semiconductor
• Timers and Counter
8-bit timer
Watchdog timer
100 Hz timer
15-bit time-base counter
ML63295A
:2
Selectable as auto-reload mode/clock frequency measurement
mode
:1
:1
Measurable in steps of 1/100 sec.
:1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Serial port
Mode
UART communication speed
Clock frequency in synchronous mode
Data length
: Selectable as UART mode, synchronous mode
: 1200 bps, 2400 bps, 4800 bps, 9600 bps
: Internal clock mode (32.768 kHz), External clock frequency
: 5 to 8 bits
• Shift register
Shift clock
Data length
: 1 × or 1/2 × system clock, external clock
: 8 bits
• Interrupt factors
External interrupt
Internal interrupt
:5
: 12
• Operating temperature
: –20 to +70°C
• Power supply voltage
: 3.5 to 7.2 V
• Package:
Chip (212 pads)
: (Product name: ML63295A-xxxWA)
240-pin plastic QFP (QFP240-P-3232-0.50-BK4) : (Product name: ML63295A-xxxGA)
….under consideration
xxx indicates a code number.
3/38
FEDL63295A-02
1Semiconductor
ML63295A
BLOCK DIAGRAM
Asterisks (*) indicate the port secondary functions. Signal names enclosed by chain lines (
) indicate interface
signals of the VDDI power supply system. Signal names enclosed by
indicates signals of the VDDE power
supply system.
CPU core
TIMING
CONT.
nX-4/250
CBR
H
L
RA
EBR
X
Y
A
SP
C
Z
ALU
RSP
STACK
CAL.S:16-level
REG.S:16-level
G
PC
MIE
INSTRUCTION
DECODER
ROM
32 KW
BUS
CONT.
EXTMEM
64 KB
IR
D0-7*
A0-15*
RD*
W R*
INT
2
RAM
2048N
T2CK*
TIMER
8 bit (2ch)
T3CK*
INT
2
INT
SIO
RXC*
TXC*
RXD*
TXD*
SFT
SCLK*
SIN*
SOUT*
INT
MULDIV
INT
TST1
TST2
1
RST
TST
4
TBC
BLD
XT0
DATA BUS
RESET
INT
1
OSC0
INT
1
OSC1
1
BIAS
V DD
V DDL
V DDE
VR
1
INPUT
PORT
P0.0-P0.3
P1.0-P1.3
P2.0-P2.3
100HzTC
P3.0-P3.3
INT
V DDX1
V DDX2
V DDX3
V DDX4
C1
C2
V DD1
V DD2
V DD3
V DD4
V DD5
V DD6
MDB
INT
XT1
OSC
MD
MELODY
OUTPUT
W DT
P4.0-P4.3
P5.0-P5.3
P6.0-P6.3
P7.0-P7.3
INT
P8.0-P8.3
4
P9.0-P9.3
I/O
PORT
PA.0-PA.3
PB.0-PB.3
PC.0-PC.3
PE.0-PE.3
LCD
&
DSPR
COM1-COM32
SEG0-SEG95
V DDI
V SS
4/38
FEDL63295A-02
1Semiconductor
ML63295A
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
(NC)
VDDI
MDB
MD
(NC)
RESET
XT0
XT1
TST2
TST1
(NC)
OSC0
OSC1
VDDE
VDD
VDDL
VDD
(NC)
(NC)
(NC)
(NC)
C2
C1
VDDX4
(NC)
VDDX3
VDDX2
VDDX1
(NC)
VDD6
VDD5
VDD4
(NC)
VDD3
VDD2
VDD1
VSS
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
(NC)
PIN CONFIGURATION (TOP VIEW)
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
(NC)
(NC)
(NC)
SEG89
SEG88
SEG87
SEG86
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
(NC)
(NC)
(NC)
(NC)
(NC)
P0.2
P0.1
P0.0
VSS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
(NC)
(NC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
(NC)
(NC)
(NC)
(NC)
PE.3
PE.2
PE.1
PE.0
PC.3
PC.2
PC.1
PC.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P8.3
P8.2
P8.1
P8.0
P7.3
P7.2
P7.1
P7.0
P6.3
P6.2
P6.1
P6.0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P1.3
P1.2
P1.1
P1.0
P0.3
(NC)
(NC)
(NC)
240-Pin Plastic QFP
(GA:QFP240-P-3232-0.50-BK4)
Note: Pins marked as (NC) are no-connection pins which are left open.
5/38
FEDL63295A-02
1Semiconductor
ML63295A
PAD CONFIGURATION
163 SEG89
162 SEG88
161 SEG87
160 SEG86
159 SEG85
158 SEG84
157 SEG83
156 SEG82
155 SEG81
154 SEG80
153 SEG79
152 SEG78
151 SEG77
150 SEG76
149 SEG75
148 SEG74
147 SEG73
146 SEG72
145 SEG71
144 SEG70
143 SEG69
142 SEG68
141 SEG67
140 SEG66
139 SEG65
138 SEG64
137 SEG63
136 SEG62
135 SEG61
134 SEG60
133 SEG59
132 SEG58
131 SEG57
130 SEG56
129 SEG55
128 SEG54
127 SEG53
126 SEG52
125 SEG51
124 SEG50
123 SEG49
122 SEG48
121 SEG47
120 SEG46
119 SEG45
118 SEG44
117 SEG43
116 SEG42
115 SEG41
114 SEG40
113 SEG39
112 SEG38
111 SEG37
110 SEG36
Pad Layout
SEG90 164
SEG91 165
SEG92 166
SEG93 167
SEG94 168
SEG95 169
COM17 170
COM18 171
COM19 172
COM20173
COM21 174
COM22 175
COM23 176
COM24 177
COM25 178
COM26 179
COM27 180
COM28 181
COM29 182
COM30 183
COM31 184
COM32 185
VSS 186
VDD1 187
VDD2 188
VDD3 189
VDD4 190
VDD5 191
VDD6 192
VDDX1 193
VDDX2 194
VDDX3 195
VDDX4 196
C1 197
C2 198
VDD 199
VDDL 200
VDD 201
VDDE 202
OSC1 203
OSC0 204
TST1 205
TST2 206
XT1 207
XT0 208
RESET 209
MD 210
MDB 211
VDDI 212
Y
X
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
VSS
P0.0
P0.1
P0.2
PE.3
PE.2
PE.1
PE.0
PC.3
PC.2
PC.1
PC.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P8.3
P8.2
P8.1
P8.0
P7.3
P7.2
P7.1
P7.0
P6.3
P6.2
P6.1
P6.0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.3
P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
P2.0
P1.3
P1.2
P1.1
P1.0
P0.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
ML63295A
( 0,0 )
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
Chip size
Chip thickness
Coordinate origin
Pad hole size
Pad size
Minimum pad pitch
: 8.25 mm × 8.20 mm
: 350 µm (280 µm: available as required)
: center of chip
: 100 µm × 100 µm
: 110 µm × 110 µm
: 120 µm
Note: The chip substrate voltage is VSS.
6/38
FEDL63295A-02
1Semiconductor
ML63295A
Pad Coordinates
Center of chip: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
1
PE.3
–3138
–3905
40
P4.0
1542
–3905
2
PE.2
–3018
–3905
41
P3.3
1662
–3905
3
PE.1
–2898
–3905
42
P3.2
1782
–3905
4
PE.0
–2778
–3905
43
P3.1
1902
–3905
5
PC.3
–2658
–3905
44
P3.0
2022
–3905
6
PC.2
–2538
–3905
45
P2.3
2142
–3905
7
PC.1
–2418
–3905
46
P2.2
2262
–3905
8
PC.0
–2298
–3905
47
P2.1
2382
–3905
9
PB.3
–2178
–3905
48
P2.0
2502
–3905
10
PB.2
–2058
–3905
49
P1.3
2622
–3905
11
PB.1
–1938
–3905
50
P1.2
2742
–3905
12
PB.0
–1818
–3905
51
P1.1
2862
–3905
13
PA.3
–1698
–3905
52
P1.0
2982
–3905
14
PA.2
–1578
–3905
53
P0.3
3102
–3905
15
PA.1
–1458
–3905
54
P0.2
3965
–3281
16
PA.0
–1338
–3905
55
P0.1
3965
–3161
17
P9.3
–1218
–3905
56
P0.0
3965
–3041
18
P9.2
–1098
–3905
57
VSS
3965
–2907
19
P9.1
–978
–3905
58
COM1
3965
–2766
20
P9.0
–858
–3905
59
COM2
3965
–2646
21
P8.3
–738
–3905
60
COM3
3965
–2526
22
P8.2
–618
–3905
61
COM4
3965
–2406
23
P8.1
–498
–3905
62
COM5
3965
–2286
24
P8.0
–378
–3905
63
COM6
3965
–2166
25
P7.3
–258
–3905
64
COM7
3965
–2046
26
P7.2
–138
–3905
65
COM8
3965
–1926
27
P7.1
–18
–3905
66
COM9
3965
–1806
28
P7.0
102
–3905
67
COM10
3965
–1686
29
P6.3
222
–3905
68
COM11
3965
–1566
30
P6.2
342
–3905
69
COM12
3965
–1446
31
P6.1
462
–3905
70
COM13
3965
–1326
32
P6.0
582
–3905
71
COM14
3965
–1206
33
P5.3
702
–3905
72
COM15
3965
–1086
34
P5.2
822
–3905
73
COM16
3965
–966
35
P5.1
942
–3905
74
SEG0
3965
–846
36
P5.0
1062
–3905
75
SEG1
3965
–726
37
P4.3
1182
–3905
76
SEG2
3965
–606
38
P4.2
1302
–3905
77
SEG3
3965
–486
39
P4.1
1422
–3905
78
SEG4
3965
–366
7/38
FEDL63295A-02
1Semiconductor
ML63295A
Center of chip: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
79
SEG5
3965
–246
118
SEG44
2225
3905
80
SEG6
3965
–126
119
SEG45
2105
3905
81
SEG7
3965
–6
120
SEG46
1985
3905
82
SEG8
3965
114
121
SEG47
1865
3905
83
SEG9
3965
234
122
SEG48
1745
3905
84
SEG10
3965
354
123
SEG49
1625
3905
85
SEG11
3965
474
124
SEG50
1505
3905
86
SEG12
3965
594
125
SEG51
1385
3905
87
SEG13
3965
714
126
SEG52
1265
3905
88
SEG14
3965
834
127
SEG53
1145
3905
89
SEG15
3965
954
128
SEG54
1025
3905
90
SEG16
3965
1074
129
SEG55
905
3905
91
SEG17
3965
1194
130
SEG56
785
3905
92
SEG18
3965
1314
131
SEG57
665
3905
93
SEG19
3965
1434
132
SEG58
545
3905
94
SEG20
3965
1554
133
SEG59
425
3905
95
SEG21
3965
1674
134
SEG60
305
3905
96
SEG22
3965
1794
135
SEG61
185
3905
97
SEG23
3965
1914
136
SEG62
65
3905
98
SEG24
3965
2034
137
SEG63
–55
3905
99
SEG25
3965
2154
138
SEG64
–175
3905
100
SEG26
3965
2274
139
SEG65
–295
3905
101
SEG27
3965
2394
140
SEG66
–415
3905
102
SEG28
3965
2514
141
SEG67
–535
3905
103
SEG29
3965
2634
142
SEG68
–655
3905
104
SEG30
3965
2754
143
SEG69
–775
3905
105
SEG31
3965
2874
144
SEG70
–895
3905
106
SEG32
3965
2994
145
SEG71
–1015
3905
107
SEG33
3965
3114
146
SEG72
–1135
3905
108
SEG34
3965
3234
147
SEG73
–1255
3905
109
SEG35
3965
3354
148
SEG74
–1375
3905
110
SEG36
3185
3905
149
SEG75
–1495
3905
111
SEG37
3065
3905
150
SEG76
–1615
3905
112
SEG38
2945
3905
151
SEG77
–1735
3905
113
SEG39
2825
3905
152
SEG78
–1855
3905
114
SEG40
2705
3905
153
SEG79
–1975
3905
115
SEG41
2585
3905
154
SEG80
–2095
3905
116
SEG42
2465
3905
155
SEG81
–2215
3905
117
SEG43
2345
3905
156
SEG82
–2335
3905
8/38
FEDL63295A-02
1Semiconductor
ML63295A
Center of chip: X = 0, Y = 0
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
157
SEG83
–2455
3905
185
COM32
–3965
912
158
SEG84
–2575
3905
186
VSS
–3965
730
159
SEG85
–2695
3905
187
VDD1
–3965
580
160
SEG86
–2815
3905
188
VDD2
–3965
430
161
SEG87
–2935
3905
189
VDD3
–3965
280
162
SEG88
–3055
3905
190
VDD4
–3965
130
163
SEG89
–3175
3905
191
VDD5
–3965
–20
164
SEG90
–3965
3432
192
VDD6
–3965
–170
165
SEG91
–3965
3312
193
VDDX1
–3965
–320
166
SEG92
–3965
3192
194
VDDX2
–3965
–470
167
SEG93
–3965
3072
195
VDDX3
–3965
–620
168
SEG94
–3965
2952
196
VDDX4
–3965
–770
169
SEG95
–3965
2832
197
C1
–3965
–920
170
COM17
–3965
2712
198
C2
–3965
–1070
171
COM18
–3965
2592
199
VDD
–3965
–1220
172
COM19
–3965
2472
200
VDDL
–3965
–1370
173
COM20
–3965
2352
201
VDD
–3965
–1520
174
COM21
–3965
2232
202
VDDE
–3965
–1670
175
COM22
–3965
2112
203
OSC1
–3965
–1924
176
COM23
–3965
1992
204
OSC0
–3965
–2074
177
COM24
–3965
1872
205
TST1
–3965
–2268
178
COM25
–3965
1752
206
TST2
–3965
–2388
179
COM26
–3965
1632
207
XT1
–3965
–2593
180
COM27
–3965
1512
208
XT0
–3965
–2743
181
COM28
–3965
1392
209
RESET
–3965
–2912
182
COM29
–3965
1272
210
MD
–3965
–3120
183
COM30
–3965
1152
211
MDB
–3965
–3240
184
COM31
–3965
1032
212
VDDI
–3965
–3392
9/38
FEDL63295A-02
1Semiconductor
ML63295A
PIN DESCRIPTIONS
The basic functions of each pin of the ML63295A are described in Table 1.
A symbol with a slash “/” denotes a pin that has a secondary function. Refer to Table 2 for secondary functions.
For type, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input-output pin.
Table 1 Pin Descriptions (Basic Functions)
Function
Power
Supply
Symbol
Pin No.
Pad No.
Type
VDD
164, 166
199, 201
—
Positive power supply pin
VSS
6, 144
57, 186
—
Negative power supply pin
VDD1
145
187
VDD2
146
188
VDD4
149
190
VDD5
150
191
VDD6
151
192
VDDX1
153
193
VDD3
147
189
VDDX4
157
196
C1
158
197
C2
159
198
VDDX2
154
194
VDDX3
155
195
VDDI
179
212
Description
Power supply pins for LCD bias voltage (internally
generated):
—
Capacitors (1.0 µF) should be connected between
these pins and VSS.
—
Positive power supply for low-speed oscillation.
—
Power supply pins for LCD bias voltage generation:
Capacitors (1.0 µF) should be connected between
these pins and VSS.
—
Capacitor connection pins for LCD bias voltage
generation:
A capacitor (1.0 µF) should be connected between
C1 and C2, and between VDDX2 and VDDX3.
—
Positive power supply pin for external interface
(Power supply for input, output, and input-output
—
ports)
VDDL
165
200
—
Positive power supply pin for internal logic
(internally generated):
A capacitor (0.1 µF) should be connected between
this pin and VSS.
VDDE
167
202
—
Constant voltage output pin:
A capacitor (1.0 µF) should be connected between
this pin and VSS.
XT0
174
208
I
XT1
173
207
O
Oscillation
Low-speed clock oscillation pins:
An option for using crystal oscillation or RC
oscillation is chosen by the mask option.
If the crystal oscillation is chosen, a crystal should
be connected between XT0 and XT1, and capacitor
(CG) should be connected between XT0 and VSS.
If the RC oscillation is chosen, external oscillation
resistor (ROSL) should be connected between XT0
and XT1.
10/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
Type
OSC0
169
204
I
OSC1
168
203
O
TST1
171
205
I
TST2
172
206
I
Oscillation
Test
Reset
Melody
Description
High-speed clock oscillation pins:
A ceramic resonator and capacitors (CL0, CL1) or
external oscillation resistor (ROSH) should be
connected to these pins.
Input pins for testing.
A pull-down resistor is internally connected to these
pins.
RESET
175
209
I
System reset input pin.
Setting this pin to “H” level puts this device into a
reset state. Then, setting this pin to “L” level starts
executing an instruction from address 0000H.
A pull-down resistor is internally connected to this
pin.
MD
177
210
O
Melody output pin (non-inverted output)
MDB
178
211
O
Melody output pin (inverted output)
11/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Port
Symbol
Pin No.
Pad No.
P0.0/INT5
5
56
P0.1/INT5
4
55
P0.2/INT5
3
54
P0.3/INT5
237
53
P1.0/INT5
236
52
P1.1/INT5
235
51
P1.2/INT5
234
50
P1.3/INT5
233
49
P2.0
232
48
P2.1
231
47
P2.2
230
46
P2.3
229
45
P3.0
228
44
P3.1
227
43
P3.2
226
42
P3.3
225
41
P4.0/A0
224
40
P4.1/A1
223
39
P4.2/A2
222
38
P4.3/A3
221
37
P5.0/A4
220
36
P5.1/A5
219
35
P5.2/A6
218
34
P5.3/A7
217
33
P6.0/A8
216
32
P6.1/A9
215
31
P6.2/A10
214
30
P6.3/A11
213
29
P7.0/A12
212
28
P7.1/A13
211
27
P7.2/A14
210
26
P7.3/A15
209
25
P8.0/RD
208
24
P8.1/WR
207
23
P8.2
206
22
P8.3/INT4
205
21
P9.0/D0
204
20
P9.1/D1
203
19
P9.2/D2
202
18
P9.3/D3
201
17
Type
Description
4-bit input ports:
I
Pull-up resistor input, pull-down resistor input,
or high-impedance input is selectable for each
bit.
I
4-bit output ports:
O
P-channel open drain output, N-channel open
drain output, CMOS output, or high-impedance
output is selectable for each bit.
O
O
O
O
O
4-bit input-output ports:
I/O
I/O
In input mode, pull-up resistor input, pull-down
resistor input, or high-impedance input is
selectable for each bit.
In output mode, P-channel open drain output,
N-channel open drain output, CMOS output, or
high-impedance output is selectable for each
bit.
12/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin No.
Pad No.
PA.0/D4
200
16
PA.1/D5
199
15
PA.2/D6
198
14
PA.3/D7
197
13
PB.0/INT0
196
12
PB.1/INT0
195
11
194
10
193
9
PC.0/INT1/
RXD
192
8
PC.1/INT1/
TXC
191
7
PC.2/INT1/
RXC
190
6
PC.3/INT1/
TXD
189
5
PE.0/SIN
188
4
PE.1/SOUT
187
3
PE.2/SCLK
186
2
PE.3/INT2
185
1
PB.2/INT0/
T2CK
PB.3/INT0/
T3CK
Port
Type
Description
4-bit input-output ports:
I/O
I/O
In input mode, pull-up resistor input, pulldown resistor input, or high-impedance
input is selectable for each bit.
In output mode, P-channel open drain
output, N-channel open drain output, CMOS
output, or high-impedance output is
selectable for each bit.
I/O
I/O
13/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
Pin No.
Pad No.
COM1
7
58
COM2
8
59
COM3
9
60
COM4
10
61
COM5
11
62
COM6
12
63
COM7
13
64
COM8
14
65
COM9
15
66
COM10
16
67
COM11
17
68
COM12
18
69
COM13
19
70
COM14
20
71
COM15
21
72
COM16
22
73
COM17
128
170
COM18
129
171
COM19
130
172
COM20
131
173
COM21
132
174
COM22
133
175
COM23
134
176
COM24
135
177
COM25
136
178
COM26
137
179
COM27
138
180
COM28
139
181
COM29
140
182
COM30
141
183
COM31
142
184
COM32
143
185
Type
Description
LCD common signal output pins
O
14/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
64
65
66
67
68
69
70
71
72
73
74
Pad No.
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Type
Description
LCD segment signal output pins
O
15/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
LCD
Symbol
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
Pin No.
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
122
123
124
125
126
127
Pad No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
Type
Description
LCD segment signal output pins
O
16/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 2 shows the secondary functions of each pin of the ML63295A.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin No.
Pad No.
PB.0/INT0
196
12
PB.1/INT0
195
11
Type
Description
External 0 interrupt input pins
I
The change of input signal level causes an
interrupt to occur.
PB.2/INT0
194
10
PB.3/INT0
193
9
The Port B Interrupt Enable register (PBIE)
enables or disables an interrupt for each bit.
PC.0/INT1
192
8
External 1 interrupt input pins
PC.1/INT1
191
7
I
The change of input signal level causes an
interrupt to occur.
PC.2/INT1
190
6
PC.3/INT1
189
5
PE.3/INT2
185
1
I
P8.3/INT4
205
21
I
P0.0/INT5
5
56
External 5 interrupt input pins
P0.1/INT5
4
55
P0.2/INT5
3
54
The change of input signal level causes an
interrupt to occur.
P0.3/INT5
237
53
P1.0/INT5
236
52
P1.1/INT5
235
51
P1.2/INT5
234
50
P1.3/INT5
233
49
PB.2/T2CK
194
PB.3/T3CK
193
The Port C Interrupt Enable register (PCIE)
enables or disables an interrupt for each bit.
External 2 interrupt input pin
External
Interrupt
The change of input signal level causes an
interrupt to occur.
External 4 interrupt input pin
Timer
The change of input signal level causes an
interrupt to occur.
I
The Port 0 Interrupt Enable register (P0IE)
and Port 1 Interrupt Enable register (P1IE)
enable or disable an interrupt for each bit.
10
I
External clock input pin for timer 2
9
I
External clock input pin for timer 3
17/38
FEDL63295A-02
1Semiconductor
ML63295A
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Symbol
PC.0/RXD
Pin No.
192
Pad No.
8
Type
I
PC.1/TXC
191
7
I/O
PC.2/RXC
190
6
I/O
PC.3/TXD
PE.0/SIN
PE.1/SOUT
189
188
187
5
4
3
O
I
O
PE.2/SCLK
186
2
I/O
P4.0/A0
P4.1/A1
P4.2/A2
P4.3/A3
P5.0/A4
P5.1/A5
P5.2/A6
P5.3/A7
P6.0/A8
P6.1/A9
P6.2/A10
P6.3/A11
P7.0/A12
P7.1/A13
P7.2/A14
P7.3/A15
P9.0/D0
P9.1/D1
P9.2/D2
P9.3/D3
PA.0/D4
PA.1/D5
PA.2/D6
PA.3/D7
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
204
203
202
201
200
199
198
197
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
20
19
18
17
16
15
14
13
P8.0/RD
208
24
O
P8.1/WR
207
23
O
Serial
Port
Shift
Register
External
Memory
Description
Serial port receive data input pin
Sync serial port clock input-output pin
Transmit clock output when this device is used as a
master processor.
Transmit clock input when this device is used as a
slave processor.
Sync serial port clock input-output pin
Receive clock output when this device is used as a
master processor.
Receive clock input when this device is used as a
slave processor.
Serial port transmit data output pin
Shift register receive data input pin
Shift register transmit data output pin
Shift register clock input-output pin.
Clock output when this device is used as a master
processor.
Clock input when this device is used as a slave
processor.
Address output bus for external memory
O
Data bus for external memory
I/O
Read signal output pin for external memory
(negative logic)
Write signal output pin for external memory
(negative logic)
18/38
FEDL63295A-02
1Semiconductor
ML63295A
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage 1
VDD1
Ta = 25°C
–0.3 to +1.5
V
Power Supply Voltage 2
VDD2
Ta = 25°C
–0.3 to +2.5
V
Power Supply Voltage 3
VDD3
Ta = 25°C
–0.3 to +6.5
V
Power Supply Voltage 4
VDD4
Ta = 25°C
–0.3 to +4.5
V
Power Supply Voltage 5
VDD5
Ta = 25°C
–0.3 to +5.5
V
Power Supply Voltage 6
VDD6
Ta = 25°C
–0.3 to +6.5
V
Power Supply Voltage 7
VDDX1
Ta = 25°C
–0.3 to +2.0
V
Power Supply Voltage 8
VDDX4
Ta = 25°C
–0.3 to +6.5
V
Power Supply Voltage 9
VDD
Ta = 25°C
–0.3 to +7.5
V
Power Supply Voltage 10
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 11
VDDL
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 12
VDDE
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI input, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 1
VOUT1
VDD1 output, Ta = 25°C
–0.3 to VDD1 + 0.3
V
Output Voltage 2
VOUT2
VDD2 output, Ta = 25°C
–0.3 to VDD2 + 0.3
V
Output Voltage 3
VOUT3
VDD3 output, Ta = 25°C
–0.3 to VDD3 + 0.3
V
Output Voltage 4
VOUT4
VDD4 output, Ta = 25°C
–0.3 to VDD4 + 0.3
V
Output Voltage 5
VOUT5
VDD5 output, Ta = 25°C
–0.3 to VDD5 + 0.3
V
Output Voltage 6
VOUT6
VDD6 output, Ta = 25°C
–0.3 to VDD6 + 0.3
V
Output Voltage 7
VOUT7
VDDX1 output, Ta = 25°C
–0.3 to VDDX1 + 0.3
V
Output Voltage 8
VOUT8
VDDX4 output, Ta = 25°C
–0.3 to VDDX4 + 0.3
V
Output Voltage 9
VOUT11
VDD output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 10
VOUT12
VDDI output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 11
VOUT13
VDDE output, Ta = 25°C
–0.3 to VDDE + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
19/38
FEDL63295A-02
1Semiconductor
ML63295A
RECOMMENDED OPERATING CONDITIONS
(VSS = 0 V)
Parameter
Symbol
Condition
Range
Unit
Operating Temperature
TOP
—
–20 to +70
°C
VDD
—
3.5 to 7.2
V
Operating Voltage
VDDI
—
1.8 to 5.5
V
Crystal Oscillation Frequency
fXT
CG = 5 to 25 pF
32.768 to 76.8
kHz
Low-speed RC Oscillation
Frequency
ROSL = 1.5 MΩ
32 k ±30%
fROSL
ROSL = 700 kΩ
60 k ±30%
ROSL = 500 kΩ
80 k ±30%
VDD = 3.5 to 7.2 V
200 k to 2 M
Ceramic Oscillation
Frequency
High-speed RC Oscillation
Frequency
fCM
fROSH
VDD = 3.5 to 7.2 V
ROSH = 100 kΩ
700 k ±30%
ROSH = 75 kΩ
1 M ±30%
ROSH = 51 kΩ
1.35 M ±30%
ROSH = 30 kΩ
2 M ±30%
Hz
Hz
Hz
20/38
FEDL63295A-02
1Semiconductor
ML63295A
Typical characteristics of low-speed RC oscillation
(VDD = 6.0 V, VDDI = 3.0 V)
Reference data
fROSL [kHz]
1000
100
10
100
1000
10000
ROSL [kΩ]
Typical characteristics of high-speed RC oscillation
(VDD = 6.0 V, VDDI = 3.0 V)
Reference data
fROSH[kHz]
10000
1000
100
10
100
1000
ROSH [kΩ]
21/38
FEDL63295A-02
1Semiconductor
ML63295A
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD = 3.5 to 7.2 V, VDDI = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
VDDE Voltage
VDDE
IOUT = 0 to 15 mA, Ta = 25°C
2.7
3.0
3.3
V
VDDE Voltage
Temperature
Deviation
∆VDDE
—
—
–4.0
—
mV/°C
High-speed clock oscillation
stopped
1.0
1.5
2.0
1.2
—
3.3
VDDL Voltage
VDDL
During operation at high-speed
clock oscillation
(VDD = 3.5 to 7.2 V)
Crystal Oscillation
Start Voltage
V
VSTA
Oscillation start time:
within 5 seconds
3.5
—
—
Crystal Oscillation
Hold Voltage
VHOLD
—
3.5
—
—
Crystal Oscillation
Stop Detect Time
TSTOP
—
0.1
—
5.0
External RC
Oscillator
Capacitance
CG
—
5
—
25
Internal RC
Oscillator
Capacitance
CD
—
20
25
30
External Ceramic
Oscillator
Capacitance
CL0, CL1
CSA2.00MG
(Murata MFG.-make) used
VDDE = 3.0 V
—
30
—
Internal RC
Oscillator
Capacitance
COS
—
8
12
16
POR Voltage
VPOR1
VDD = 6.0 V
0
—
0.7
VPOR2
VDD = 6.0 V
2.0
—
6.0
BLD Judgment
Voltage
VBLDC
LD1 = 1, LD0 = 1, Ta = 25°C
5.00
5.10
5.20
LD1 = 1, LD0 = 0, Ta = 25°C
4.40
4.50
4.60
—
–3.5
—
Notes:
VBLDC = 5.10 V
∆VBLDC
(LD1 = 1, LD0 = 1)
VBLDC = 4.50 V
(LD1 = 1, LD0 = 0)
ms
1
pF
Non-POR Voltage
BLD Judgment
Voltage
Temperature
Deviation
Measuring
Circuit
V
V
—
mV/°C
—
–2.3
—
1. “TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset
occurs.
2. “POR” denotes Power On Reset.
3. “VPOR1” indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises up to VDD
4. “VPOR2” indicates that POR does not occur when VDD falls from VDD to VPOR2 and again rises
up to VDD.
22/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (2)
(VDD = 6.0 V, VDDI = 3.0 V, VSS = 0 V, 1/6 bias, DSPCNT = 0H, Ta = –20 to +70°C unless otherwise specified)
Parameter
Supply
Current 1
Supply
Current 2
Supply
Current 3
Symbol
IDD1
IDD2
IDD3
Supply
Current 4
IDD4
Supply
Current 5
IDD5
Condition
CPU in HALT state,
LCD is being driven,
no panel load
(Crystal oscillation: 32.768 kHz)
(High-speed clock oscillation
stopped)
CPU in HALT state,
LCD is being driven,
no panel load
(RC oscillation: ROSL = 1.5 MΩ)
(High-speed clock oscillation
stopped)
CPU in HALT state,
LCD in Power Down mode
(Crystal oscillation: 32.768 kHz)
(High-speed clock oscillation
stopped)
CPU in HALT state,
LCD in Power Down mode
(RC oscillation: ROSL = 1.5 MΩ)
(High-speed clock oscillation
stopped)
CPU operating at low speed,
LCD is being driven,
no panel load
(Crystal oscillation: 32.768 kHz)
(High-speed clock oscillation
stopped)
CPU operating at low speed,
LCD is being driven,
no panel load
(RC oscillation: ROSL = 1.5 MΩ)
(High-speed clock oscillation
stopped)
Min.
Max.
Ta = –20 to +50°C
—
11.0 14.5
Ta = –20 to +70°C
—
11.0 19.5
Ta = –20 to +50°C
—
14.5 18.0
Ta = –20 to +70°C
—
14.5 23.0
Ta = –20 to +50°C
—
4.0
5.0
Ta = –20 to +70°C
—
4.0
6.5
Ta = –20 to +50°C
—
7.0
8.0
Ta = –20 to +70°C
—
7.0
Ta = –20 to +50°C
—
20.5 29.0
Ta = –20 to +70°C
—
20.5 34.0
Ta = –20 to +50°C
—
24.5 33.0
Ta = –20 to +70°C
—
24.5 38.0
—
1100 1700
—
1500 2000
CPU operating at high-speed oscillation
(1 MHz RC oscillation, ROSH = 75 kΩ)
CPU operating at high-speed oscillation
(2 MHz ceramic oscillation)
Typ.
Unit
Measuring
Circuit
µA
1
9.5
23/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (3)
(VDD = 3.5 to 7.2 V, VDDI = 1.8 to 5.5 V, VSS = 0 V, Ta = 25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
VDD6 Voltage
VDD6
1/6 bias, 1/5 bias
4.0
4.1
4.2
VDD5 Voltage
VDD5
1/6 bias
Typ.–0.1
5/6 × VDD6
Typ.+0.1
1/5 bias
Typ.–0.1
4/5 × VDD6
Typ.+0.1
VDD4 Voltage
VDD4
1/6 bias
Typ.–0.1
4/6 × VDD6
Typ.+0.1
1/5 bias
Typ.–0.1
3/5 × VDD6
Typ.+0.1
1/6 bias
Typ.–0.1
2/6 × VDD6
Typ.+0.1
1/5 bias
Typ.–0.1
2/5 × VDD6
Typ.+0.1
1/6 bias
Typ.–0.1
1/6 × VDD6
Typ.+0.1
1/5 bias
Typ.–0.1
1/5 × VDD6
Typ.+0.1
VDD2 Voltage
VDD2
VDD1 Voltage
VDD1
Unit
Measuring
Circuit
V
1
Note: “VDD6” changes in the range from 4.10 to 6.14 V (Typ. value) according to the value of Display
Contrast register (DSPCNT).
(VDD = 3.5 to 7.2 V, VDDI = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
VDDE Voltage
∆VDDE
—
—
–4.0
—
mV/°C
VDD6 Voltage
VDD6
1/6 bias, 1/5 bias
3.6
4.1
4.6
VDD5 Voltage
VDD5
1/6 bias
Typ.–0.5
5/6 × VDD6
Typ.+0.5
1/5 bias
Typ.–0.5
4/5 × VDD6
Typ.+0.5
1/6 bias
Typ.–0.5
4/6 × VDD6
Typ.+0.5
1/5 bias
Typ.–0.5
3/5 × VDD6
Typ.+0.5
1/6 bias
Typ.–0.5
2/6 × VDD6
Typ.+0.5
1/5 bias
Typ.–0.5
2/5 × VDD6
Typ.+0.5
1/6 bias
Typ.–0.5
1/6 × VDD6
Typ.+0.5
1/5 bias
Typ.–0.5
1/5 × VDD6
Typ.+0.5
Temperature Deviation
VDD4 Voltage
VDD4
VDD2 Voltage
VDD2
VDD1 Voltage
VDD1
Measuring
Circuit
1
V
Note: “VDD6” changes in the range from 4.10 to 6.14 V (Typ. value) according to the value of Display
Contrast register (DSPCNT).
24/38
FEDL63295A-02
1Semiconductor
ML63295A
• Contrast voltage (VDD6 voltage)
Ta = 25°C, VDD6 = 4.1 V (Typ.)
VDD6 Voltage (V)
DSPCNT
CN0 to CN3
CN3
CN2
CN1
CN0
Min.
Typ.
Max.
0H
0
0
0
0
—
4.1
—
1H
0
0
0
1
Typ.–0.1
4.2
Typ.+0.1
2H
0
0
1
0
Typ.–0.1
4.3
Typ.+0.1
3H
0
0
1
1
Typ.–0.1
4.4
Typ.+0.1
4H
0
1
0
0
Typ.–0.1
4.5
Typ.+0.1
5H
0
1
0
1
Typ.–0.1
4.62
Typ.+0.1
6H
0
1
1
0
Typ.–0.1
4.74
Typ.+0.1
7H
0
1
1
1
Typ.–0.1
4.86
Typ.+0.1
8H
1
0
0
0
Typ.–0.1
5.00
Typ.+0.1
9H
1
0
0
1
Typ.–0.1
5.14
Typ.+0.1
0AH
1
0
1
0
Typ.–0.1
5.29
Typ.+0.1
0BH
1
0
1
1
Typ.–0.1
5.44
Typ.+0.1
0CH
1
1
0
0
Typ.–0.1
5.60
Typ.+0.1
0DH
1
1
0
1
Typ.–0.1
5.77
Typ.+0.1
0EH
1
1
1
0
Typ.–0.1
5.95
Typ.+0.1
0FH
1
1
1
1
Typ.–0.1
6.14
Typ.+0.1
Display Contrast
Light
Dark
Ta = 25°C, VDD6 = 4.0 V (Min.)
VDD6 Voltage (V)
DSPCNT
CN0 to CN3
CN3
CN2
CN1
CN0
Min.
Typ.
Max.
0H
0
0
0
0
—
4.0
—
1H
0
0
0
1
Typ.–0.1
4.1
Typ.+0.1
2H
0
0
1
0
Typ.–0.1
4.2
Typ.+0.1
3H
0
0
1
1
Typ.–0.1
4.3
Typ.+0.1
4H
0
1
0
0
Typ.–0.1
4.4
Typ.+0.1
5H
0
1
0
1
Typ.–0.1
4.52
Typ.+0.1
6H
0
1
1
0
Typ.–0.1
4.64
Typ.+0.1
7H
0
1
1
1
Typ.–0.1
4.76
Typ.+0.1
8H
1
0
0
0
Typ.–0.1
4.90
Typ.+0.1
9H
1
0
0
1
Typ.–0.1
5.04
Typ.+0.1
0AH
1
0
1
0
Typ.–0.1
5.19
Typ.+0.1
0BH
1
0
1
1
Typ.–0.1
5.34
Typ.+0.1
0CH
1
1
0
0
Typ.–0.1
5.50
Typ.+0.1
0DH
1
1
0
1
Typ.–0.1
5.67
Typ.+0.1
0EH
1
1
1
0
Typ.–0.1
5.85
Typ.+0.1
0FH
1
1
1
1
Typ.–0.1
6.04
Typ.+0.1
Display Contrast
Light
Dark
25/38
FEDL63295A-02
1Semiconductor
ML63295A
• Contrast voltage (VDD6 voltage)
Ta = 25°C, VDD6 = 4.2 V (Max.)
VDD6 Voltage (V)
DSPCNT
CN0 to CN3
CN3
CN2
CN1
CN0
Min.
Typ.
Max.
0H
0
0
0
0
—
4.2
—
1H
0
0
0
1
Typ.–0.1
4.3
Typ.+0.1
2H
0
0
1
0
Typ.–0.1
4.4
Typ.+0.1
3H
0
0
1
1
Typ.–0.1
4.5
Typ.+0.1
4H
0
1
0
0
Typ.–0.1
4.6
Typ.+0.1
5H
0
1
0
1
Typ.–0.1
4.72
Typ.+0.1
6H
0
1
1
0
Typ.–0.1
4.84
Typ.+0.1
7H
0
1
1
1
Typ.–0.1
4.96
Typ.+0.1
8H
1
0
0
0
Typ.–0.1
5.10
Typ.+0.1
9H
1
0
0
1
Typ.–0.1
5.24
Typ.+0.1
0AH
1
0
1
0
Typ.–0.1
5.39
Typ.+0.1
0BH
1
0
1
1
Typ.–0.1
5.54
Typ.+0.1
0CH
1
1
0
0
Typ.–0.1
5.70
Typ.+0.1
0DH
1
1
0
1
Typ.–0.1
5.87
Typ.+0.1
0EH
1
1
1
0
Typ.–0.1
6.05
Typ.+0.1
0FH
1
1
1
1
Typ.–0.1
6.24
Typ.+0.1
Display Contrast
Light
Dark
26/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (4)
(VDD = 6.0 V, VDDI = VDDE = 3.0 V, VDD1 = 1.0 V, VDD2 = 2.0 V, VDD3 = 3.0 V, VDD4 = 4.0 V,
VDD5 = 5.0 V, VDD6 = 6.0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Output Current 1
(P2.0 to P2.3)
Symbol
Condition
Min.
Typ.
Max.
VDDI = 3.0 V
–6.0
–3.5
–1.0
VDDI = 5.0 V
–8.5
–5.0
–1.5
VDDI = 3.0 V
1.0
3.0
6.0
VDDI = 5.0 V
1.5
3.7
8.5
VOH1 = VDDI – 0.5 V
(PC.0 to PC.3)
(PE.0 to PE.3)
IOL1
VOL1 = 0.5 V
Output Current 2
(MD, MDB)
IOH2
VOH2 = VDDE – 0.7 V
VDDE = 3.0 V
–11.0
–6.0
–2.0
IOL2
VOL2 = 0.7 V
VDDE = 3.0 V
2.0
5.5
11.0
—
—
–4
…
IOH1
IOH3
Output Current 3
(SEG0 to SEG95)
(COM1 to COM32)
IOHM3
VOHM3 = VDD5 + 0.2 V (VDD5 level)
4
—
—
VOHM3S = VDD5 – 0.2 V (VDD5 level)
—
—
–4
IOMH3
VOMH3 = VDD4 + 0.2 V (VDD4 level)
4
—
—
IOMH3S
VOMH3S = VDD4 – 0.2 V (VDD4 level)
—
—
–4
IOML3
VOML3 = VDD2 + 0.2 V (VDD2 level)
4
—
—
IOML3S
VOML3S = VDD2 – 0.2 V (VDD2 level)
—
—
–4
IOLM3
VOLM3 = VDD1 + 0.2 V (VDD1 level)
4
—
—
IOLM3S
VOLM3S = VDD1 – 0.2 V (VDD1 level)
—
—
–4
VOL3 = VSS + 0.2 V (VSS level)
4
—
—
IOH4R
VOH4R = VDDE – 0.5 V
(RC oscillation)
VDDE = 3.0 V
–2.50
–1.30
–0.25
IOL4R
VOL4R = 0.5 V
(RC oscillation)
VDDE = 3.0 V
0.25
1.50
2.50
IOH4C
VOH4C = VDDE – 0.5 V
(ceramic oscillation)
VDDE = 3.0 V
–300
–120
–60
IOL4C
VOL4C = 0.5 V
(ceramic oscillation)
VDDE = 3.0 V
60
120
300
µA
2
mA
IOOH
VOH = VDDI
—
—
0.3
IOOL
VOL = VSS
–0.3
—
—
µA
…
Output Leakage
Current
(P2.0 to P2.3)
Measuring
Circuit
mA
IOHM3S
IOL3
Output Current 4
(OSC1)
VOH3 = VDD6 – 0.2 V (VDD6 level)
Unit
(PC.0 to PC.3)
(PE.0 to PE.3)
27/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (5)
(VDD = 6.0 V, VDDI = VDDE = 3.0 V, VDD1 = 1.0 V, VDD2 = 2.0 V, VDD3 = 3.0 V, VDD4 = 4.0 V,
VDD5 = 5.0 V, VDD6 = 6.0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
…
Input Current 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
Symbol
IIH1
IIL1
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
VDDI = 3.0 V
Min.
Typ.
Max.
10
20
40
VDDI = 5.0 V
20
60
120
VDDI = 3.0 V
–40
–20
–10
VDDI = 5.0 V
–120
–60
–20
IIH1Z
VIH1 = VDDI (in a high impedance state)
0
—
1.0
IIL1Z
VIL1 = VSS (in a high impedance state)
–1.0
—
0
–350
–170
–30
IIL2
Input Current 2
(OSC0)
Condition
VIL2 = VSS
(when pulled up)
VDDE = 3.0 V
Unit
µA
3
IIH2R
VIH2R = VDDE (RC oscillation)
0
—
1.0
IIL2R
VIL2R = VSS (RC oscillation)
–1.0
—
0
IIH2C
VIH2R = VDDE (ceramic oscillation)
0.1
0.5
1.0
IIL2C
VIL2R = VSS (ceramic oscillation)
–1.0
–0.5
–0.1
40
60
150
–1.0
—
0
4.0
12.0
16.0
mA
–1.0
—
0
µA
Input Current 3
(RESET)
IIH3
Input Current 4
(TST1, TST2)
IIH4
IIL3
IIL4
VIH3 = VDD
VDD = 6.0 V
VIL3 = VSS
VIH4 = VDD
VIL4 = VSS
VDD = 6.0 V
Measuring
Circuit
28/38
FEDL63295A-02
1Semiconductor
ML63295A
DC Characteristics (6)
(VDD = 6.0 V, VDDI = VDDE = 3.0 V, VDD1 = 1.0 V, VDD2 = 2.0 V, VDD3 = 3.0 V, VDD4 = 4.0 V,
VDD5 = 5.0 V, VDD6 = 6.0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
(PC.0 to PC.3)
(PE.0 to PE.3)
VIL1
Input Voltage 2
(OSC0)
VIH2
Input Voltage 3
(RESET, TST1, TST2)
VIH3
Min.
Typ.
Max.
VDDI = 3.0 V
2.3
—
3.0
VDDI = 5.0 V
3.8
—
5.0
VDDI = 3.0 V
0
—
0.7
VDDI = 5.0 V
0
—
1.2
2.4
—
3.0
Unit
Measuring
Circuit
VDDE = 3.0 V
0
—
0.6
4.8
—
6.0
0
—
1.2
VDDI = 3.0 V
0.2
0.5
1.0
VDDI = 5.0 V
0.25
1.00
1.50
∆VT2
VDD = 5.0 V
0.25
1.00
1.50
CIN
—
—
—
5
VIL2
VIL3
VDD = 6.0 V
V
4
pF
—
∆VT1
…
Hysteresis Width 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
Condition
VIH1
…
Input Voltage 1
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
Symbol
(PC.0 to PC.3)
(PE.0 to PE.3)
Hysteresis Width 2
(RESET, TST1, TST2)
…
Input Pin Capacitance
(P0.0 to P0.3)
(P1.0 to P1.3)
(P8.0 to P8.3)
(PC.0 to PC.3)
(PE.0 to PE.3)
29/38
FEDL63295A-02
1Semiconductor
ML63295A
Measuring circuit 1
XT0
3
XT1
4
(*2)
C1
C12
1
C2
OSC0
2
OSC1
VDDX1
VDDX2
VDDX3
VDDX4
(*1)
VSS
VDD
VDDE
A CXE
VDD1
Ca
V
CX1, CX23, CX4, CXE
Ca, Cb, Cc, Cd, Ce, Cf, C12
Cl
CG
CL0
CL1
Ceramic resonator
VDDI
VDD2
Cb
V
: 1.0 µF
: 1.0 µF
: 0.1 µF
: 15 pF
: 30 pF
: 30 pF
: CSA2.00MG (2 MHz)
: CSB1000J (1 MHz)
(Murata MFG-.make)
VDD3
Cc
VDD4
VDD5
Cd
V
Ce
V
VDD6
Cf
V
CI
V
V
*2 RC Oscillator
1
3
2
4
ROSL
ROSH
Ceramic Oscillator
Crystal Oscillator
CG
3
1
Ceramic resonator
2
CL1
CX4
VDDL
*1 RC Oscillator
CL0
CX1
CX23
4
32.768 kHz
crystal
30/38
FEDL63295A-02
1Semiconductor
ML63295A
Measuring circuit 2
*4
VIH
INPUT
*3
VIL
OUTPUT
VSS
VDD
VDDE
VDDI
VDD1
VDD2
VDD4
VDD5
VDD6
A
VDDL
*3 Input logic circuit to determine the specified measuring conditions.
*4 Measured at the specified output pins.
Measuring circuit 3
*5
INPUT
A
OUTPUT
VSS
VDD
VDDE VDDI
VDD1
VDD2
VDD4
VDD5
VDD6
VDDL
Measuring circuit 4
VIH
*5
VIL
INPUT
VSS
OUTPUT
VDD
VDDE VDDI
VDD1
VDD2
VDD4
VDD5
VDD6
Waveform
Monitoring
VDDL
*5 Measured at the specified input pins.
31/38
FEDL63295A-02
1Semiconductor
ML63295A
AC Characteristics (Serial Interface, Serial Port)
(1) Synchronous Communication
(VDD = 3.5 to 7.2 V,VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
TXC/RXC Input Fall Time
tf
—
—
—
1.0
TXC/RXC Input Rise Time
tr
—
—
—
1.0
TXC/RXC Input “L” Level Pulse Width
tCWL
—
0.8
—
—
TXC/RXC Input “H” Level Pulse Width
tCWH
—
0.8
—
—
TXC/RXC Input Cycle Time
tCYC
—
2.0
—
—
tCYC1 (O)
CPU operating at 32.768 kHz
—
30.5
—
tCYC2 (O)
CPU operating at 2 MHz
—
0.5
—
tDDR
Output load capacitance
10 pF
—
—
0.4
RXD Input Setup Time
tDS
—
0.5
—
—
RXD Input Hold Time
tDH
—
0.8
—
—
TXC/RXC Output Cycle Time
TXD Output Delay Time
Unit
µs
Synchronous communication timing
(“H” level = 4.0 V, “L” level = 1.0 V)
tCYC
VDDI
TXC (PC.1)/
RXC (PC.2)
VSS
tr
tf
tCWH
tCWL
tDDR
tDDR
VDDI
TXD (PC.3)
VSS
tDS
tDH
tDS
VDDI
RXD (PC.0)
VSS
32/38
FEDL63295A-02
1Semiconductor
ML63295A
(2) UART Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Transmit Baud Rate
TBRT
TBRT = 1/fBRT
TCR = 1/fOSC
TBRT – TCR
TBRT
TBRT + TCR
Receive Baud Rate
RBRT
RBRT = 1/fBRT
RBRT × 0.97
RBRT
RBRT × 1.03
Unit
s
fBRT: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing
(“H” level = 4.0 V, “L” level = 1.0 V)
TBRT
VDDI
TXD (PC.3)
VSS
RBRT
VDDI
RXD (PC.0)
VSS
33/38
FEDL63295A-02
1Semiconductor
ML63295A
AC Characteristics (Serial Interface, Shift Register)
(VDD = 3.5 to 7.2 V, VDDI = 5.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Parameter
SCLK Input Fall Time
SCLK Input Rise Time
Symbol
Condition
Min.
Typ.
Max.
tf
—
—
—
1.0
tr
—
—
—
1.0
SCLK Input “L” Level Pulse Width
tCWL
—
0.8
—
—
SCLK Input “H” Level Pulse Width
tCWH
—
0.8
—
—
tCYC
VDDI = VDDE to 5.5 V
1.8
—
—
tCYC1(O)
CPU operating at 32.768 kHz
—
30.5
—
SCLK Input Cycle Time
SCLK Output Cycle Time
tCYC2(O)
CPU operating at 2 MHz
—
0.5
—
SOUT Output Delay Time
tDDR
Output load capacitance 10 pF
—
—
0.4
SIN Input Setup Time
tDS
—
0.5
—
—
SIN Input Hold Time
tDH
—
0.8
—
—
Unit
µs
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
tCYC
VDDI
SCLK (PE.2)
VSS
tr
tf
tCWH
tCWL
tDDR
tDDR
VDDI
SOUT (PE.1)
VSS
tDS
tDH
tDS
VDDI
SIN (PE.0)
VSS
34/38
FEDL63295A-02
1Semiconductor
ML63295A
AC Characteristics (External Memory Interface)
(VDD = 3.5 to 7.2 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless otherwise specified)
(1)
For Reading from External Memory
(a) When the CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Read Cycle Time
tRC
—
—
61.0
—
RD Output Delay Time
tOE
—
—
—
5.0
Output Enable Time
tOHA
—
—
—
5.0
External Memory Output Delay Time
tDO
—
—
—
5.0
Unit
µs
(b) When the CPU operates at 2 MHz (VDD = 3.5 to 7.2 V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Read Cycle Time
tRC
—
1.0
—
—
µs
RD Output Delay Time
tOE
—
—
—
100
Output Enable Time
tOHA
—
—
—
100
External Memory Output Delay Time
tDO
—
—
—
150
ns
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
P7 to P4
(A15 to A0)
Port set value
Address output
Port set value
P8.0
(RD)
VSS
VDDI
VSS
tOHA
tOE
PA, P9
(D7 to D0)
VDDI
VDDI
Port set value
Input data
Port set value
VSS
tDO
35/38
FEDL63295A-02
1Semiconductor
(2)
ML63295A
For Writing to External Memory
(a) When the CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Write Cycle Time
tWC
—
—
61.0
—
Address Setup Time
tAS
—
—
30.5
—
Write Time
tW
—
—
15.3
—
Write Recovery Time
tWR
—
—
15.3
—
Data Setup Time
tDS
—
—
45.8
—
Data Hold Time
tDH
—
—
15.3
—
Unit
µs
(b) When the CPU operates at 2 MHz (VDD = 3.5 to 7.2 V)
Symbol
Condition
Min.
Typ.
Max.
Write Cycle Time
Parameter
tWC
—
1.0
—
—
Address Setup Time
tAS
—
0.4
—
—
Write Time
tW
—
0.2
—
—
Write Recovery Time
tWR
—
0.2
—
—
Data Setup Time
tDS
—
0.7
—
—
Data Hold Time
tDH
—
0.2
—
—
Unit
µs
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
MOVXB [RA], obj
MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
VDDI
P7 to P4
(A15 to A0)
Port set value
Address output
Port set value
PA, P9
(D7 to D0)
Port set value
Output data
Port set value
VSS
VDDI
tDH
tDS
VSS
VDDI
P8.1
(WR)
tWR
tAS
VSS
tW
36/38
FEDL63295A-02
1Semiconductor
ML63295A
PACKAGE DIMENSIONS
(Unit: mm)
QFP240-P-3232-0.50-BK4
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
Cu alloy
Solder plating (≥5µm)
7.82 TYP.
2/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
37/38
FEDL63295A-02
1Semiconductor
ML63295A
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
38/38
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