ON MC74VHCT50ADTG Noninverting buffer / cmos logic level shifter Datasheet

MC74VHCT50A
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT50A is a hex noninverting buffer fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high−voltage power
supply.
The MC74VHCT50A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when
VCC = 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
•
•
•
•
•
•
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
These Devices are Pb−Free and are RoHS Compliant
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14−LEAD SOIC
D SUFFIX
CASE 751A
14−LEAD TSSOP
DT SUFFIX
CASE 948G
14−LEAD SOEIAJ
M SUFFIX
CASE 965
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
LOGIC DIAGRAM
A1
A2
A3
1
3
5
2
4
6
LOGIC SYMBOL
Y1
A1
1
A2
1
A3
1
A4
1
A5
1
A6
1
Y2
Y3
Y=A
A4
A5
A6
9
8
11
10
13
12
Y4
Y1
Y2
A Input
Y Output
L
H
L
H
Y3
ORDERING INFORMATION
Y4
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Y5
Y5
Y6
Y6
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 7
FUNCTION TABLE
1
Publication Order Number:
MC74VHCT50A/D
MC74VHCT50A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
*0.5 to )7.0
V
*0.5 v VI v )7.0
V
*0.5 v VO v )7.0
V
VCC
DC Supply Voltage
VIN
DC Input Voltage
VOUT
DC Output Voltage
IIK
DC Input Diode Current
*20
mA
IOK
DC Output Diode Current
$20
mA
IO
DC Output Source/Sink Current
$25
mA
ICC
DC Supply Current per Supply Pin
$50
mA
IGND
DC Ground Current per Ground Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
_C
TJ
Junction Temperature under Bias
)150
_C
qJA
Thermal Resistance
PD
Power Dissipation in Still Air
VESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
2000
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85_C (Note 5)
$300
mA
Output in HIGH or LOW State (Note 1)
SOIC
TSSOP
125
170
SOIC
TSSOP
500
450
_C/W
mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Max
Unit
DC Supply Voltage
Characteristics
VCC
2.0
5.5
V
DC Input Voltage
VIN
0.0
5.5
V
VOUT
0.0
0.0
5.5
VCC
V
TA
−55
+125
°C
tr , tf
0
0
100
20
ns/V
DC Output Voltage
VCC = 0
High or Low State
Operating Temperature Range
Input Rise and Fall Time
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
TEST POINT
3.0V
A
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL*
VOH
Y
50% VCC
VOL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
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2
MC74VHCT50A
DC ELECTRICAL CHARACTERISTICS
VCC
Symbol
Parameter
Test Conditions
Min
1.2
2.0
2.0
VIH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
VIL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
VOH
Minimum High−Level
Output Voltage
VIN = VIH or VIL
VOL
Maximum Low−Level
Output Voltage
VIN = VIH or VIL
TA = 25°C
(V)
Typ
TA ≤ 85°C
Max
Min
1.2
2.0
2.0
0.53
0.8
0.8
VIN = VIH or VIL
IOH = −50 mA
3.0
4.5
2.9
4.4
VIN = VIH or VIL
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
VIN = VIH or VIL
IOL = 50 mA
3.0
4.5
VIN = VIH or VIL
IOH = −4 mA
IOL = 8 mA
Max
Max
1.2
2.0
2.0
Unit
V
0.53
0.8
0.8
3.0
4.5
0.0
0.0
TA ≤ 125°C
Min
0.53
0.8
0.8
2.9
4.4
2.9
4.4
2.48
3.80
2.34
3.66
V
V
V
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
μA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
2.0
20
40
μA
ICCT
Quiescent Supply
Current
Input: VIN = 3.4 V
5.5
1.35
1.50
1.65
mA
IOFF
Output Leakage
Current
VOUT = 5.5 V
0.0
0.5
5.0
10
μA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
CIN
Parameter
Maximum
Propogation Delay,
Input A to Y
Min
TA ≤ 85°C
TA ≤ 125°C
Typ
Max
Min
Max
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
5.5
8.0
7.9
11.4
1.0
1.0
9.5
13.0
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
6.2
7.0
7.5
8.5
8.5
9.5
9.5
10.5
5
10
10
10
Test Conditions
Maximum Input
Capacitance
Min
Max
Unit
ns
pF
Typical @ 25°C, VCC = 5.0 V
15
CPD
Power Dissipation Capacitance (Note 6)
pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.8
1.0
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.8
−1.0
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
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3
MC74VHCT50A
ORDERING INFORMATION
Package
Shipping†
MC74VHCT50ADG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74VHCT50ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT50ADTG
TSSOP−14
(Pb−Free)
96 Units / Rail
MC74VHCT50ADTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT50AMG
SOEIAJ
(Pb−Free)
50 Units / Rail
MC74VHCT50AMELG
SOEIAJ
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
(Top View)
14
13
12
11
10
9
14 13 12 11 10
8
2
3
4
8
6
7
VHCT
50A
ALYWG
G
VHCT50AG
AWLYWW*
1
9
5
6
7
1
2
14−LEAD SOIC
D SUFFIX
CASE 751A
3
4
5
14−LEAD TSSOP
DT SUFFIX
CASE 948G
14
13
12
11
10
9
8
6
7
74VHCT50A
ALYWG*
1
2
3
4
5
14−LEAD SOEIAJ
M SUFFIX
CASE 965
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*See Applications Note #AND8004/D for date code and traceability information.
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4
MC74VHCT50A
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
B
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
M
S
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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5
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC74VHCT50A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
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6
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74VHCT50A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHCT50A/D
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