Very Low Power CMOS SRAM 512K X 16 bit BS616LV8017 Pb-Free and Green package materials are compliant to RoHS FEATURES DESCRIPTION y Wide VCC operation voltage : 2.4V ~ 5.5V y Very low power consumption : Operation current : 31mA (Max.) at 55ns VCC = 3.0V 2mA (Max.) at 1MHz O Standby current : 4/8uA (Max.) at 70/85 C Operation current : 76mA (Max.) at 55ns VCC = 5.0V 10mA (Max.) at 1MHz O Standby current : 25/50uA (Max.) at 70/85 C y High speed access time : -55 55ns(Max.) at VCC=3.0~5.5V -70 70ns(Max.) at VCC=2.7~5.5V y Automatic power down when chip is deselected y Easy expansion with CE and OE options y I/O Configuration x8/x16 selectable by LB and UB pin. y Three state outputs and TTL compatible y Fully static operation y Data retention supply voltage as low as 1.5V The BS616LV8017 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 by 16 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum CMOS standby O current of 8/50uA at Vcc=3/5V at 85 C and maximum access time of 55/70ns. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state output drivers. The BS616LV8017 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8017 is available in DICE form, JEDEC standard 44-pin TSOP II and 48-ball BGA package. POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE BS616LV8017DC Operating (ICCSB1, Max) VCC=5.0V VCC=3.0V 25uA 4.0uA PKG TYPE (ICC, Max) 1MHz VCC=5.0V 10MHz fMax. 9mA 39mA 75mA 1MHz VCC=3.0V 10MHz fMax. 1.5mA 19mA 30mA DICE Commercial O O +0 C to +70 C BS616LV8017EC STANDBY BS616LV8017EI Industrial O O -40 C to +85 C BS616LV8017FI 50uA 8.0uA 10mA 40mA PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A18 A17 A16 A15 A14 TSOP II-44 BGA-48-0912 BS616LV8017FI 76mA 2mA 20mA 31mA TSOP II-44 BGA-48-0912 BLOCK DIAGRAM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 BS616LV8017EC BS616LV8017EI 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B D8 UB A3 A4 CE D0 C D9 D10 A5 A6 D1 D2 D VSS D11 A17 A7 D3 VCC E VCC D12 NC A16 D4 VSS F D14 D13 A14 A15 D5 D6 G D15 NC A12 A13 WE D7 H A18 A8 A9 A10 A11 NC A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A12 A13 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 Address 1024 10 Input Row Buffer Decoder Memory Array 1024 x 8192 8192 DQ0 . 16 . . . . . . . . . . . 16 VCC VSS Data Output Buffer 16 Column I/O Write Driver Sense Amp 16 512 Column Decoder DQ15 CE WE OE UB LB Data Input Buffer 9 Control Address Input Buffer A14 A15 A16 A17 A18 A0 A1 A2 A3 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS616LV8017 1 Revision 2.4 Oct. 2008 BS616LV8017 PIN DESCRIPTIONS Name Function A0-A18 Address Input These 19 address inputs select one of the 524,288 x 16-bit in the RAM CE Chip Enable Input CE is active LOW. Chip enable must be active when data read form or write to the device. If chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the WE Write Enable Input chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is OE Output Enable Input selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. DQ0-DQ15 Data Input/Output Ports There 16 bi-directional ports are used to read data from or write data into the RAM. VCC Power Supply VSS Ground TRUTH TABLE MODE CE WE OE LB UB IO0~IO7 IO8~IO15 VCC CURRENT Chip De-selected (Power Down) H X X X X High Z High Z ICCSB, ICCSB1 X X X H H High Z High Z ICCSB, ICCSB1 L H H L X High Z High Z ICC L H H X L High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC Output Disabled Read Write L L H L L X NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state) R0201-BS616LV8017 2 Revision 2.4 Oct. 2008 BS616LV8017 ABSOLUTE MAXIMUM RATINGS (1) SYMBOL VTERM TBIAS TSTG PARAMETER OPERATING RANGE RATING Terminal Voltage with Respect to GND Temperature Under Bias (2) -0.5 Storage Temperature UNITS RANG AMBIENT TEMPERATURE V Commercial 0 C to + 70 C Industrial -40 C to + 85 C to 7.0 -40 to +125 O C -60 to +150 O C PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA O VCC O O 2.4V ~ 5.5V O 2.4V ~ 5.5V CAPACITANCE (1) (TA = 25OC, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V 6 pF VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS 2.4 -- 5.5 V 0.8 V VCC Power Supply VIL Input Low Voltage -0.5 -- VIH Input High Voltage 2.2 -- IIL Input Leakage Current -- -- 1 uA ILO Output Leakage Current -- -- 1 uA VOL Output Low Voltage VCC = Max, IOL = 2.0mA -- -- 0.4 V VOH Output High Voltage VCC = Min, IOH = -1.0mA 2.4 -- -- V ICC(5) Operating Power Supply Current CE = VIL, -- -- ICC1 Operating Power Supply Current -- -- -- -- ICCSB ICCSB1(6) (2) Standby Current – TTL Standby Current – CMOS VIN = 0V to VCC CE= VIH VI/O = 0V to VCC, CE= VIH or OE = VIH IIO = 0mA, f = FMAX VCC=3.0V (4) VCC=5.0V CE = VIL, VCC=3.0V IIO = 0mA, f = 1MHz VCC=5.0V CE = VIH, VCC=3.0V IIO = 0mA VCC=5.0V CE≧VCC-0.2V VCC=3.0V VIN ≧VCC-0.2V or V IN ≦0.2V VCC=5.0V -- VCC+0.3 31 (3) V mA 76 2 mA 10 1.0 2.0 0.8 8.0 3.5 50 mA uA O 1. Typical characteristics are at TA=25 C and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. O 5. ICC (MAX.) is 30mA/75mA at VCC=3.0V/5.0V and TA=70 C. O 6. ICCSB1(MAX.) is 4.0uA/25uA at VCC=3.0V/5.0V and TA=70 C. R0201-BS616LV8017 3 Revision 2.4 Oct. 2008 BS616LV8017 DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC) SYMBOL PARAMETER TEST CONDITIONS VDR VCC for Data Retention ICCDR(3) Data Retention Current tCDR Chip Deselect to Data Retention Time CE≧VCC-0.2V VIN≧VCC-0.2V or VIN≦0.2V CE≧VCC-0.2V VIN≧VCC-0.2V or VIN≦0.2V MIN. TYP. (1) MAX. UNITS 1.5 -- -- V -- 0.4 4.0 uA 0 -- -- ns -- -- ns See Retention Waveform tR Operation Recovery Time tRC (2) O 1. VCC=1.5V, TA=25 C and not 100% tested. 2. tRC = Read Cycle Time. O 3. ICCDR(Max.) is 2.0uA at TA=70 C. LOW VCC DATA RETENTION WAVEFORM (CE Controlled) Data Retention Mode VCC VDR≧1.5V VCC tCDR tR CE≧VCC - 0.2V VIH CE VCC AC TEST CONDITIONS VIH KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load WAVEFORM tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Others CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output (1) VCC GND CL 90% 10% → ← Rise Time: 1V/ns 90% 10% → ← Fall Time: 1V/ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE 1. Including jig and scope capacitance. R0201-BS616LV8017 4 Revision 2.4 Oct. 2008 BS616LV8017 AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION CYCLE TIME : 55ns (VCC=3.0~5.5V) CYCLE TIME : 70ns (VCC=2.7~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNITS tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tELQV tACS Chip Select Access Time (CE) -- -- 55 -- -- 70 ns tBLQV tBA Data Byte Control Access Time (LB, UB) -- -- 55 -- -- 70 ns tGLQV tOE Output Enable to Output Valid tELQX tCLZ Chip Select to Output Low Z tBLQX tBE Data Byte Control to Output Low Z tGLQX tOLZ Output Enable to Output Low Z tEHQZ -- -- 30 -- -- 35 ns (CE) 10 -- -- 10 -- -- ns (LB, UB) 10 -- -- 10 -- -- ns 5 -- -- 5 -- -- ns tCHZ Chip Select to Output High Z (CE) -- -- 30 -- -- 35 ns tBHQZ tBDO Data Byte Control to Output High Z (LB, UB) -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH tAA tOH DOUT R0201-BS616LV8017 5 Revision 2.4 Oct. 2008 BS616LV8017 READ CYCLE 2 (1,3,4) CE tACS tBA LB, UB tCHZ(5) tBE DOUT tBDO tCLZ(5) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE tOH tOLZ CE tCLZ tOHZ(5) (5) tCHZ(1,5) tBA LB, UB tBE tBDO DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS616LV8017 6 Revision 2.4 Oct. 2008 BS616LV8017 AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION CYCLE TIME : 55ns (VCC=3.0~5.5V) CYCLE TIME : 70ns (VCC=2.7~5.5V) MIN. TYP. MAX. MIN. TYP. MAX. UNITS tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 55 -- -- 70 -- -- ns tELWH tCW Chip Select to End of Write (CE) 55 -- -- 70 -- -- ns tBLWH tBW Data Byte Control to End of Write (LB, UB) 25 -- -- 30 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX tWR Write Recovery Time 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns (CE, WE) SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1(3) OE tCW(11) CE (5) tBW LB, UB tWR2(3) tAW WE tWP(2) tAS tOHZ(4,10) DOUT tDH tDW DIN R0201-BS616LV8017 7 Revision 2.4 Oct. 2008 BS616LV8017 WRITE CYCLE 2 (1,6) tWC ADDRESS tCW(11) CE (5) LB, UB (12) tBW tAW WE tAS tWR2(3) tWP(2) tWHZ(4,10) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10.Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11.tCW is measured from the later of CE going low to the end of write. 12.The change of Read/Write cycle must accompany with CE or address toggled. R0201-BS616LV8017 8 Revision 2.4 Oct. 2008 BS616LV8017 ORDERING INFORMATION BS616LV8017 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE o o C: +0 C ~ +70 C o o I: -40 C ~ +85 C PACKAGE D: DICE E: TSOP II-44 F: BGA-48-0912 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP II-44 R0201-BS616LV8017 9 Revision 2.4 Oct. 2008 BS616LV8017 0.25±0.05 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.2 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 3.375 0.1 D1 N D E D1 E1 e 48 12.0 9.0 5.25 3.75 0.75 E±0.1 2.625 E1 e SOLDER BALL 0.35 ±0.05 VIEW A 48 mini-BGA (9mm x 12mm) R0201-BS616LV8017 10 Revision 2.4 Oct. 2008 BS616LV8017 Revision History Revision No. History Draft Date 2.2 Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 110uA to 50uA at 5.0V 10uA to 8.0uA at 3.0V C-grade from 55uA to 25uA at 5.0V 5.0uA to 4.0uA at 3.0V Jan. 13, 2006 2.3 Change I-grade operation temperature range - from –25OC to –40OC May. 25, 2006 2.4 Typical value of standby current is replaced by maximum value in Featues and Description section Oct. 31, 2008 Remark Remove “-: Normal” (Leaded) PKG Material in ordering information R0201-BS616LV8017 11 Revision 2.4 Oct. 2008