CXP881P60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP881P60 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface,
timer/counter, time base timer, high precision timing
pattern generation circuits, PWM output, PWM for
tuner, VISS/VASS circuit, 32kHz timer counter,
remote control reception circuit, fluorescent display
panel (FDP) controller/driver, VSYNC separator and
the measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, PROM, RAM and I/O port. They are integrated
into a single chip.
Also, CXP881P60 provides sleep/stop function
which enables to lower power consumption and
ultra-low speed instruction mode in 32kHz operation.
The CXP881P60 is the PROM-incorporated
version of the CXP88160 with built-in mask ROM.
This provides the additional feature of being able to
write directly into the program. Thus, it is most suitable for evaluation use during system development
and for small-quantity production.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated PROM capacity 60K bytes
• Incorporated RAM capacity
1296 bytes (including fluorescent display area)
• Peripheral function
— A/D converter
8 bits, 8 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
— Timer
8-bit timer/counter, 2 channel
19-bit time base timer
32kHz timer/counter
— High precision timing pattern generator
PPG 8 pins, 21-stage programmable circuit
RTG 5 pins, 2 channels
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 4 channels
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14 bits, 1 channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Fluorescent display panel controller/driver Maximum 144-segment display possible
Hardware key scan function (Maximum 16 x 3 key matrix available)
Dimmer function
High voltage drive output (40V)
Incorporated pull-down resistor (mask option)
— Tri-state output
PPG 1 pin, RTG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
• Interruption
22 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95325-ST
ADJ
HGO
PWM0
DAA0
DAB0
PWM1
DAA1
DAB1
PWM
RMC
CFG
DFG
DPG
PBCTL
SYNC0
SYNC1
EXI0
EXI1
EC0
EC1
EC2
TO/DDO
AVDD
FIFO
AVss
8 BIT TIMER/COUNTER1
8 BIT TIMER/COUNTER 0
PSEUDO HSYNC GENERATOR
12 BIT PWM GENERATOR CH1
12 BIT PWM GENERATOR CH0
14 BIT PWM GENERATOR
VISS/VASS
FIFO
SERVO INPUT
CONTROL
REMOCON INPUT
CTL
DRUM
CAPSTAN
V SYNC SEPARATOR
EC
SELECT
SERIAL INTERFACE UNIT
(CH1)
SERIAL
INTERFACE UNIT
(CH0)
3
2
4
2
2
2
2
INT1/NMI
INT2
8
PROGRAMABLE
PATTERN
GENERATOR
FRC
CAPTURE UNIT
INTERRUPT CONTROLLER
AVREF
A/D CONVERTER
RAM
FIFO
CH0
5
CH1
REALTIME
PULSE
GENERATOR
2
PROM
60K BYTES
SPC700
CPU CORE
8
8
8
FDP
CONTROLLER
/DRIVER
32kHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
RAM
1296 BYTES
RAM
CLOCK
GENERATOR/
SYSTEM CONTROL
AA
A
RTO3 to RTO7
CS0
SI0
SO0
SCK0
SI1
SO1
SCK1
8
VFDP
AN0 to AN7
T0 to T7
2
PPO0 to PPO7
EXTAL
XTAL
TEX
TX
RST
MP
VDD
Vss
Vpp
T8/S15
to
T15/S8
S0 to S7
PORT A
PG0 to PG7
PH0 to PH2
8
3
PI1 to PI7
PF4 to PF7
4
7
PF0 to PF3
PE2 to PE7
PE0 to PE1
PD0 to PD7
PC0 to PC7
PB0 to PB7
PA0 to PA7
4
6
2
8
8
4
4
8
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
–2–
PORT I
Block Diagram
CXP881P60
INT0
CXP881P60
PI5/SCK0
PI4/INT1/NMI/CS0
PI3/TO/DDO/ADJ
PI2/PWM
PI1/RMC
TEX
TX
VDD
VSS
Vpp
PH2/KR2
PH1/KR1
PH0/KR0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Pin Configuration (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PB0
1
80
PI6/SO0
PC7/RTO7
2
79
PI7/SI0
PC6/RTO6
3
78
VFDP
PC5/RTO5
4
77
PD0/S0
PC4/RTO4
5
76
PD1/S1
PC3/RTO3
6
75
PD2/S2
PC2
7
74
PD3/S3
PC1
8
73
PD4/S4
PC0
9
72
PD5/S5
PA7/PPO7
10
71
PD6/S6
(HAMP) PA6/PPO6
11
70
PD7/S7
(ROTA) PA5/PPO5
12
69
S8/T15
(RF-PLS) PA4/PPO4
13
68
S9/T14
PA3/PPO3
14
67
S10/T13
PA2/PPO2
15
66
S11/T12
PA1/PPO1
16
65
S12/T11
HGO/PA0/PPO0
17
64
S13/T10
PF7
18
63
S14/T9
SI1/PF6
19
62
S15/T8
SO1/PF5
20
61
T7
SCK1/PF4
21
60
T6
PF3/AN7
22
59
T5
PF2/AN6
23
58
T4
PF1/AN5
24
57
T3
PF0/AN4
25
56
T2
AN3
26
55
T1
AN2
27
54
T0
AVREF
28
53
PE0/INT0 (ENV-DET)
AVSS
29
52
PE1/EC0/INT2
AVDD
30
51
PWM0/PE2
Note) 1. Vpp (Pin 90) is always connected to VDD.
2. VSS (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) must be connected to GND.
–3–
PE3/PWM1
PE4/DAA0
PE5/DAA1
DAB0/PE6
DAB1/PE7
PG0/CFG
PG1/DFG
EXTAL
XTAL
VSS
RST
MP
PG2/DPG
PG3/PBCTL/EC1
PG4/SYNC0/EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP881P60
Pin Description
Symbol
PA0/PPO0/
HGO
I/O
Output/Real time
output/Output
PA1/PPO1
PA2/PPO2
PA3/PPO3
I/O/
Real time output
PA4/PPO4
PA5/PPO5
PA6/PPO6
Description
Output/
Real time output
Pseudo HSYNC
output pin.
(Port A)
PA0 and PA5 to PA7 are
for outputs; PA1 to PA4
are for I/O. I/O can be
set in a unit of single bits.
Data is gated with PPO
content by OR-gate and
they are output.
(8 pins)
Programmable pattern generator (PPG)
output. Functions as high precision realtime pulse output port.
(8 pins)
Head switching
output pins. (2 pins)
PA7/PPO7
8-bit output port. Tri-state can be controlled.
(8 pins)
PB0 to PB7
Output
PC0 to PC2
I/O
PC3/RTO3
to
PC7/RTO7
I/O/
Real time output
T0 to T7
Output
FDP timing signal output pin. (8 pins)
T8/S15
to
T15/S8
Output/Output
Output pins for FDP timing signal and segment signal.
(8 pins)
PD0/S0
to
PD7/S7
Output/Output
(Port D)
8-bit output port.
(8 pins)
PE0/INT0
Input/Input
Trigger pulse
Input pin to request
input pin for head external interruption.
switching output. Active when falling edge.
PE1/EC0/
INT2
Input/Input/Input
External event
input pin for
timer/counter.
PE2/PWM0
Output/Output
PE3/PWM1
Output/Output
PE4/DAA0
Output/Output
PE5/DAA1
Output/Output
PE6/DAB0
Output/Output
PE7/DAB1
Output/Output
AN0 to AN3
Input
PF0/AN4
to
PF3/AN7
Input/Input
PF4/SCK1
I/O/I/O
PF5/SO1
I/O/Output
PF6/SI1
I/O/Input
PF7
I/O
(Port C)
8-bit I/O port. I/O can be
set in a unit of single bits.
Data is gated with RTO
content by OR-gate and
they are output. (8 pins)
Real-time pulse generator (RTG) output.
Functions as high precision real-time pulse
output port.
(5 pins)
FDP segment signal output pin. (8 pins)
(Port E)
8-bit port.
Lower 2 bits are for
inputs; upper 6 bits are for
outputs.
(8 pins)
Input pin to request
external interruption.
Active when falling edge.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
Analog input pins to A/D converter. (8 pins)
(Port F)
Lower 4 bits are for
inputs; upper 4 bits are
for I/O. I/O can be set
in a unit of single bits.
(8 pins)
–4–
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
CXP881P60
Symbol
I/O
Description
PG0/CFG
Input/Input
Capstan FG input pin.
PG1/DFG
Input/Input
Drum FG input pin.
PG2/DPG
Input/Input
Drum PG input pin.
PG3/
PBCTL/EC1
Input/Input/Input
Playback CTL input pin.
PG4/
SYNC0/EC2
Input/Input/Input
PG5/SYNC1
Input/Input
PG6/EXI0
Input/Input
PG7/EXI1
Input/Input
PH0/KR0
to
PH2/KR2
I/O/Input
PI1/RMC
I/O/Input
Remote control reception circuit input pin.
PI2/PWM
I/O/Input
14-bit PWM output pin.
PI3/TO/
DDO/ADJ
I/O/Output/
Output/Output
PI4/INT1/
NMI/CS0
I/O/Input/
Input/Input
PI5/SCK0
I/O/I/O
PI6/SO0
I/O/Output
Serial data (CH0) output pin.
PI7/SI0
I/O/Input
Serial data (CH0) input pin.
EXTAL
Input
XTAL
Output
TEX
Input
TX
Output
Connecting pin of crystal oscillator for 32kHz timer clock.
When used as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)
RST
Input
System reset pin of active "L" level.
MP
Input
Test mode pin. Always connect to GND.
(Port G)
8-bit input port.
(8 pins)
Composite sync signal input pins.
External event
input pin for
timer/counter.
External event
input pin for
timer/counter.
External input pins for FRC capture unit.
(Port H)
3-bit I/O port.
(3 pins)
(Port I)
7-bit I/O port.
I/O can be
set in a unit of
single bits.
(7 pins)
Key return input signal for key scanning at FDP
segment signal. (3 pins)
Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.
Input pin to request external interruption,
non-maskable interruption and for serial chip select
(CH0). Active when falling edge.
Serial clock (CH0) I/O pin.
Connecting pin of crystal oscillator for system clock.
When supplying the external clock, input the external clock to EXTAL
pin and input opposite phase clock to XTAL pin.
VFDP
FDP voltage supply pin when specifying internal resistor by mask
option.
AVDD
Positive power supply pin of A/D converter.
AVREF
Input
Reference voltage input pin of A/D converter.
AVss
GND pin of A/D converter.
VDD
Positive power supply pin.
Vpp
Positive power supply pin for incorporated PROM writing connect to
VDD during normal operation.
Vss
GND pin. Connect both Vss pins to GND.
–5–
CXP881P60
Input/Output Circuit Formats for Pins
Pin
When reset
Circuit format
AA
AA
AA
AAAA
AA
AAAA AA
AAAA
AAAA
AA
AA
AAAA
AA
AAAA
AAAA
AA
Port A
HSEL
HOUT
PPO0
PA0/PPO0/
HGO
MPX
PA0
Hi-Z
Data bus
RD
(Port A)
1 pin
HSEL
MPX
HOUTE
Output becomes active from high impedance
by data writing to port register.
PPO1
PPG control status
register bit 0
Tri-state control selection
PPO1
PA1/PPO1
PA1
Hi-Z
PA1 direction
IP
Data bus
1 pin
RD (Port A)
AA
AA
A
A
Port A
AAAA
AAAA
AAAA
PPO data
PA2/PPO2
to
PA4/PPO4
Port A data
Port A direction
IP
Data bus
3 pins
RD (Port A)
AA
AA
Port A
PPO data
PA5/PPO5
to
PA7/PPO7
AAAA
Port A data
Hi-Z
Data bus
RD (Port A)
3 pins
Hi-Z
Output becomes active from high impedance
by data writing to port register.
–6–
CXP881P60
Pin
AAAA
AAAA
Port B
AA
AA
Port B data
PB0
to
PB7
Data bus
AAAA
RD (Port B)
Port C
AA
AA
A
AAAA
AAAA
AAAA
Port C data
Port C direction
3 pins
RD (Port C)
A
A
Port C
AAAA
AAAA
AAAA
RTO3
PC3
A
A
PC3 direction
RD (Port C)
1 pin
Hi-Z
IP
Data bus
A
A
RTO4
RTG interruption
control register bit 7
Tri-state control selection
AAAA
AAAA
AAAA
RTO4
PC4/RTO4
A
A
PC4
PC4 direction
IP
Data bus
1 pin
Hi-Z
IP
Data bus
PC3/RTO3
Hi-Z
Port B tri-state
control
8 pins
PC0
to
PC2
When reset
Circuit format
RD (Port C)
–7–
Hi-Z
CXP881P60
Pin
Circuit format
Port C
AAAA
AAAA
AAAA
RTO data
PC5/RTO5
to
PC7/RTO7
Port C data
Port C direction
Data bus
AA
AA
A
A
When reset
Hi-Z
IP
3 pins
RD (Port C)
Port D
High voltage drive
transistor
Segment output data
PD0/S0
to
PD7/S7
AA
AAAA
AAAA
Output selection control signal
("0" when reset)
Port D data
Hi-Z
Data bus
8 pins
RD (Port D)
AA
AA
AA
AA
High voltage drive
transistor
Timing output data
Output selection control signal
("0" when reset)
T0 to T7
Pull-down resistor
VFDP
8 pins
High voltage drive
transistor
Timing output data
T8/S15
to
T15/S8
Hi-Z
Output selection control signal
("0" when reset)
Segment output data
Pull-down resistor
AA
AA
AA
AA
VFDP
8 pins
–8–
Hi-Z
CXP881P60
Pin
Port E
Schmitt input
PE0/INT0
PE1/EC0/INT2
INT0
EC0/INT2
IP
2 pins
Port E
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
Port E function
select
DA gate output or
PWM output
Port E data
Data bus
4 pins
AAAA
AA
AAA
AAA
AAA
AAA
When reset
Circuit format
AAAA
AAAA
AAAA
AAAA
Hi-Z
Data bus
RD (Port E)
AAA
AAA
AAA
AAA
AA
AA
MPX
Hi-Z
Hi-Z control
RD (Port E)
Port E
Port E function
select
PE6/DAB0
PE7/DAB1
DA gate output
Port E data
Data bus
AAAA
AAAAA
AA
AA
AAAAA
Input multiplexer
To A/D converter
IP
Hi-Z
Data bus
Port F function select
Port F
RD (Port F)
AAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
SCK1 output enable
From serial interface
MPX
Port F data
PF4/SCK1
Port F direction
A
A
AA
AA
IP
Data bus
1 pin
High level
RD (Port E)
Port F
4 pins
AA
AA
MPX
Hi-Z control
2 pins
PF0/AN4
to
PF3/AN7
AA
AA
AA
AA
RD (Port F)
Schmitt input
To serial interface
–9–
Hi-Z
CXP881P60
Pin
When reset
Circuit format
Port F
AA
AA
AAAA
AA
AAAA AA
Port F output selection
AA
AA
AA
From serial interface
MPX
PF5/SO1
Port F data
Port F direction
IP
Data bus
RD (Port F)
1 pin
Port F
AAAA
AAAA
AAAA
AAAA
Port F data
PF6/SI1
Port F direction
RD (Port F)
Schmitt input
Hi-Z
To serial interface
Port F
AAAA
AAAA
AAAA
AAAA
AA
AA
A
A
Port F data
PF7
Port F direction
Hi-Z
IP
Data bus
RD (Port F)
1 pin
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL/
EC1
PG4/SYNC0/
EC2
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AA
AA
A
A
IP
Data bus
1 pin
Hi-Z
Port G
AAA
AAA
Schmitt input
IP
Hi-Z
Data bus
RD (Port G)
8 pins
– 10 –
CXP881P60
Pin
When reset
Circuit format
Port I
AAA
AAAAAA
AAA
AAAA
AAA
AAAA
AAA
AAAA
Port I function
select
PI2/PWM
PI3/TO/
DDO/ADJ
PI2 ... From 14-bit PWM,
timer/counter
PI3 ... From CTL duty detection
circuit, 32kHz timer
AA
AA
AA
MPX
Port I data
Port I direction
Data bus
2 pins
IP
RD (Port I)
AAAA
AAAA
AAAA
Port I
AA
AA
AA
AA
Port I data
PI1/RMC
PI4/INT1/
NMI/CS0
PI7/SI0
Port I direction
IP
Data bus
RD (Port I)
3 pins
Hi-Z
Hi-Z
Schmitt input
PI1 ... To remote control circuit
PI4 ... To interruption circuit
PI7 ... To serial CH0
AAAA
AAAAAAA
AAA
AAA
AAA
AA
AAA AAA
AA
AA
Port I
Port I function
select
PI5/SCK0
PI6/SO0
From
serial CH0
MPX
Port I data
MPX
Port I direction
Data bus
RD (Port I)
PI5...To serial CH0
2 pins
Port H
AAAA
AAAA
AAAA
Port H data
PH0/KR0
to
PH2/KR2
Port H direction
Data bus
RD (Port H)
3 pins
Key input signal
– 11 –
AA
AA
A
A
Hi-Z
IP
Note)
PI5 is schmitt input
Schmitt input
AA
AA
A
A
IP
Hi-Z
CXP881P60
Pin
EXTAL
XTAL
2 pins
TEX
TX
2 pins
RST
1 pin
When reset
Circuit format
AA AA
AA
AA
AA
AA
AA
AA
AA
EXTAL
• Shows the circuit
composition during
oscillation.
IP
• Feedback resistor is
removed during stop.
Hi-Z
XTAL
TEX
• Shows the circuit composition
during oscillation.
IP
• Feedback resistor is removed
during 32kHz oscillation circuit
stop by software. At this time
TEX pin outputs "L" level and
TX pin outputs "H" level.
Oscillation
TX
AA
AA
A
A
Pull-up resistor
Schmitt input
IP
– 12 –
Low level
CXP881P60
Absolute Maximum Ratings
Item
Supply voltage
Symbol
(Vss=0V)
Rating
Unit
VDD
–0.3 to +7.0
V
Vpp
–0.3 to +13
AVss to +7.0∗1
V
V
AVDD
Remarks
Incorporated PROM
V
Input voltage
VIN
–0.3 to +0.3
–0.3 to +7.0∗2
Output voltage
VOUT
–0.3 to +7.0∗2
V
Display output voltage
VOD
VDD–40 to VDD+0.3
V
IOH
–5
mA
All pins excluding display outputs
(value per pin)∗3
IODH1
–15
mA
Display outputs S0 to S7 (value per pin)
IODH2
–35
mA
Display outputs T0 to T7,
and T8/S15 to T15/S8 (value per pin)
∑IOH
–50
mA
Total for all pins excluding display outputs
∑IODH
–100
mA
Total for all display outputs
15
mA
130
mA
AVSS
High level output current
High level total
output current
Low level output current
IOL
Low level total output current ∑IOL
V
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
As P-channel transistor is open drain,
VDD is reference.
Total for all outputs
∗1) AVDD and VDD should be set to the same voltage.
∗2) VIN and VOUT should not exceed VDD+0.3V.
∗3) It specifies output current of general-purpose I/O port.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 13 –
CXP881P60
Recommended Operating Conditions
Item
Symbol
VDD
Supply voltage
Min.
Max.
4.5
5.5
3.5
5.5
2.7
5.5
2.5
5.5
Vpp = VDD
Vpp
Analog power supply
High level input voltage
Low level input voltage
Operating temperature
(Vss=0V)
Unit
Remarks
Guaranteed range during high speed mode
(1/2 dividing clock) operation
V
Guaranteed range during low speed mode
(1/16 dividing clock) operation
Guaranteed operation range by TEX clock
V
Guaranteed data hold operation range
during STOP
∗7
4.5
5.5
V
∗1
VIH
0.7VDD
VDD
V
∗2
VIHS
0.8VDD
VDD
V
VIHTS
2.2
VDD
V
CMOS schmitt input∗3
TTL schmitt input∗4
VIHEX
VDD–0.4
VDD+0.3
V
EXTAL pin∗5 TEX pin∗6
VIL
0
0.3VDD
V
∗2
VILS
0
0.2VDD
V
VILTS
0
0.8
V
CMOS schmitt input∗3
TTL schmitt input∗4
VILEX
–0.3
0.4
V
EXTAL pin∗5 TEX pin∗6
Topr
–10
+75
°C
AVDD
∗1) AVDD and VDD should be set to the same voltage.
∗2) Normal input port (each pin of PA1 to PA4, PC, PF0 to PF3, PF5, PF7, PH, PI2, PI3 and PI6), MP pin
∗3) Each pin of RST, PE0/INT0, PE1/EC0/INT2, PF4/SCK1, PF6/SI1, PI1/RMC, PI4/CS0/NMI/INT1, PI5/SCK0,
PI7/SI1, PG0/CFG, PG1/DFG, PG2/DPG, PG3/PBCTL/EC, PG6/EXI0, PG7/EXI1.
∗4) Each pin of PG4/SYNC0/EC2, PG5/SYNC1.
∗5) It specifies only when the external clock is input.
∗6) It specifies only when the external event is input.
∗7) Vpp and VDD should be set to the same voltage.
– 14 –
CXP881P60
DC Characteristics
Item
Symbol
High level
VOH
output voltage
Low level
VOL
output voltage
Display
output current
IOH
(Ta=–10 to +75°C, Vss=0V)
Pin
Condition
Min.
VDD=4.5V, IOH=–0.5mA
PA to PC, PE
PF4 to PF7, VDD=4.5V, IOH=–1.2mA
PH,
VDD=4.5V, IOL=1.8mA
PI1 to PI7
VDD=4.5V, IOL=3.6mA
4.0
V
3.5
V
S0 to S7
–8
mA
–20
mA
S8/T15 to
S15/T8,
T0 to T7
VDD=4.5V,
VOH=VDD–2.5V
Open drain
output leakage
current (P-CH ILOL
Tr OFF in
state)
S0 to S7,
S8/T15 to
S15/T8,
T0 to T7
VDD=5.5V,
VOL=VDD–35V
VFDP=VDD–35V
Pull-down
resistor
RL
S8/T15 to
S15/T8,
T0 to T7
VDD=5V,
VOD–VFDP=30V
60
EXTAL
VDD=5.5V, VIH=5.5V
IIHE
IILE
TEX
Input
current
I/O leakage
current
Supply
current∗1
Input
capacity
Typ.
Max.
Unit
0.4
V
0.6
V
–20
µA
270
kΩ
0.5
40
µA
VDD=5.5V, VIL=0.4V
–0.5
–40
µA
VDD=5.5V, VIH=5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400
µA
±10
µA
VDD=5.5V,
VIL=0.4V
IILR
RST
IIZ
PA to PC,
PE to PI,
AN1 to AN3, VDD=5.5V, VI=0, 5.5V
MP
100
IDD1
16MHz crystal oscillation (C1=C2=15pF),
VDD=5V±0.5V∗2
28
50
mA
IDDS1
16MHz crystal oscillation (C1=C2=15pF),
VDD=5V±0.5V, SLEEP mode
1.7
8
mA
32kHz crystal oscillation (C1=C2=47pF),
VDD=3V±0.3V
0.8
2
mA
IDDS2
32kHz crystal oscillation (C1=C2=47pF),
VDD=3V±0.3V, SLEEP mode
3
35
µA
IDDS3
VDD=5.5V, STOP mode
(32kHz, 16MHz oscillation stop)
30
µA
20
pF
IDD2
CIN
VDD, Vss
PA1 to PA4
PC0 to PC7
PE0, PE1
AN0 to AN3
Clock 1MHz
PF0 to PF7
0V other than the measured pins
PG0 to PG7
PH0 to PH2
PI1 to PI7
– 15 –
10
CXP881P60
∗1) When entire output pins are open.
∗2) When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
AC Characteristics
(1) Clock timing
(Ta=–10 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Item
Symbol
Pin
Condition
Min.
System clock frequency
fC
XTAL
EXTAL
Fig. 1, Fig. 2
1
System clock input pulse width
tXL,
tXH
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
28
System clock input rise and
fall times
tCR,
tCF
XTAL
EXTAL
Fig. 1, Fig. 2
External clock drive
Event count clock input
pulse width
EC0, EC1,
Fig. 3
EC2
Event count clock input
rise and fall times
tEH,
tEL
tER,
tEF
System clock frequency
fC
Event count clock input
pulse width
tTL,
tTH
tTR,
tTF
Event count clock input
rise and fall times
Typ.
Max. Unit
16
ns
200
tsys+200∗1
20
VDD=2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
Fig. 3
TEX
Fig. 3
ns
ns
EC0, EC1,
Fig. 3
EC2
TEX
TX
MHz
ms
kHz
32.768
µs
10
20
ms
∗1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2
bits (CPU clock selection).
tsys [ns]=2000/fc (Upper 2 bits="00"), 4000/fc (Upper 2 bits="01"), 16000/fc (Upper 2 bits="11")
Fig. 1. Clock timing
1/fc
VDD – 0.4V
EXTAL
XTAL
0.4V
tCF
tXH
tXL
tCR
AAAA AAAAAAAAAA
AAAA
AAAAA
AAAAA
AAAA AAAAAAAAAA
Fig. 2. Clock applied condition
Crystal oscillation
Ceramic oscillation
EXTAL
C1
XTAL
C2
External clock
EXTAL
32kHz clock appied condition
Crystal oscillation
TEX
XTAL
74HC04
– 16 –
C1
TX
C2
CXP881P60
Fig. 3. Event count clock timing
TEX
EC0
EC1
EC2
0.8VDD
0.2VDD
tEH
tEF
tEL
tER
tTH
tTF
tTL
tTR
(2) Serial transfer (CH0)
Item
(Ta=–10 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Symbol
Condition
Pin
Min.
Max.
Unit
CS0 ↓ → SCK0
delay time
tDCSK
SCK0
Chip select transfer mode
(SCK0=output mode)
tsys+200
ns
CS0 ↑ → SCK0
floating delay time
tDCSKF SCK0
Chip select transfer mode
(SCK0=output mode)
tsys+200
ns
CS0 ↓ → SO0
delay time
tDCSO
SO0
Chip select transfer mode
tsys+200
ns
CS0 ↑ → SO0
floating delay time
tDCSOF SO0
Chip select transfer mode
tsys+200
ns
CS0
high level width
tWHCS CS0
Chip select transfer mode
tsys+200
ns
SCK0
cycle time
tKCY
Input mode
2tsys+200
ns
SCK0
Output mode
16000/fc
ns
SCK0
high and low level widths
tKH
tKL
Input mode
tsys+100
ns
SCK0
8000/fc–50
ns
SI0 input set-up time
(against SCK0 ↑)
tSIK
SCK0 input mode
100
ns
SI0
SCK0 output mode
200
ns
SI0 input hold time
(against SCK0 ↑)
tKSI
tsys+200
ns
SI0
100
ns
SCK0 ↓ → SO0 delay time
tKSO
SO0
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
tsys+200
ns
100
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns]=2000/fc (Upper 2 bits="00"), 4000/fc (Upper 2 bits="01"), 16000/fc (Upper 2 bits="11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF +1TTL.
– 17 –
CXP881P60
Fig. 4. Serial transfer timing (CH0)
tWHCS
0.8VDD
CS0
0.2VDD
tKCY
tDCSK
tKL
tDCSKF
tKH
0.8VDD
0.8VDD
SCK0
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI0
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
– 18 –
CXP881P60
Serial transfer (CH1)
Item
(Ta=–10 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Symbol
Pin
tKCY
SCK1
SCK1 high and low
level widths
tKH
tKL
SCK1
SI1 input set-up time
(against SCK1 ↑)
tSIK
SI1
SI1 input hold time
(against SCK1 ↑)
tKSI
SI1
SCK1 ↓ → SO1 delay time
tKSO
SO1
SCK1 cycle time
Condition
Min.
Input mode
Max.
1000
ns
16000/fc
ns
400
ns
8000/fc–50
ns
SCK1 input mode
100
ns
SCK1 output mode
200
ns
SCK1 input mode
200
ns
SCK1output mode
100
ns
Output mode
Input mode
Output mode
SCK1 input mode
200
ns
SCK1 output mode
100
ns
Note) The load of SCK1 output mode and SO1 output delay time is 50pF +1TTL.
Fig. 5. Serial transfer timing (CH1)
tKCY
tKL
tKH
0.8VDD
SCK1
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI1
Unit
0.2VDD
tKSO
0.8VDD
Output data
SO1
0.2VDD
– 19 –
CXP881P60
(3) A/D converter characteristics (Ta=–10 to +75°C, VDD=AVDD=4.5 to 5.5V, AVREF=4.0 to AVDD, Vss=AVss=0V)
Item
Symbol
Pin
Condition
Min.
Typ.
Resolution
Only for A/D converter
operation
Ta=25°C
VDD=AVDD=AVREF=5.0V
VSS=AVss=0V
Linearity error
Absolute error
Sampling time
tCONV
tSAMP
Reference input voltage
VREF
AVREF
Analog input voltage
VIAN
AN0 to AN7
Conversion time
Operation mode
AVREF=4.0 to 5.5V
AVREF current
IREF
AVREF
Max.
Unit
8
Bits
±1
LSB
±2
LSB
160/fADC
µs
12/fADC
µs
AVDD–0.5
AVDD
V
0
AVREF
V
1.0
mA
10
µA
0.6
SLEEP mode
STOP mode
32kHz operation mode
Fig. 6. Definitions of A/D converter terms
Digital conversion value
FFH
FEH
∗ The value of fADC is as follows by selecting ADC
operation clock (MSC: 01FFH bit 0).
When PS2 is selected, fADC=fc/2
When PS1 is selected, fADC=fc
Linearity error
01H
00H
VFT
VZT
Analog input
– 20 –
CXP881P60
(4) Interruption, reset input
(Ta=–10 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
External interruption high and
low level widths
tIH
tIL
INT0
INT1
INT2
NMI
1
µs
Reset input low level width
tRSL
RST
32/fc
µs
Fig. 7. Interruption input timing
tIH
tIL
INT0
INT1
INT2
NMI
(Falling edge)
0.8VDD
0.2VDD
Fig. 8. Reset input timing
tRSL
RST
0.2VDD
(5) Others
(Ta=–10 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Item
Symbol
DPG minimum pulse width
tCFH
tCFL
tDFH
tDFL
tDPW
DPG minimum removal time
trem
PBCTL input high and low
level widths
tCTH
tCTL
tEIH
tEIL
CFG input high and
low level widths
DFG input high and
low level widths
EXI input high and low level
widths
Pin
Condition
Min.
Max.
Unit
CFG
tFRC × 24+200
ns
DFG
tFRC × 16+200
ns
DPG
tFRC × 8+200
ns
DPG
tFRC × 16+200
ns
PBCTL
tsys=2000/fc
tFRC × 8+tsys+200
ns
EXI0
EXI1
tsys=2000/fc
tFRC × 8+tsys+200
ns
Note 1) tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns]=2000/fc (Upper 2 bits="00"), 4000/fc (Upper 2 bits="01"), 16000/fc (Upper 2 bits="11")
Note 2) tFRC=1000/fc (ns)
– 21 –
CXP881P60
Fig. 9. Other timings
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
tDFL
0.8VDD
DFG
0.2VDD
trem
tDPW
trem
0.8VDD
DPG
tCTH
tCTL
0.8VDD
PBCTL
0.2VDD
tEIH
EXI0
EXI1
tEIL
0.8VDD
0.2VDD
– 22 –
CXP881P60
Supplement
Fig. 10. Recommended oscillation circuit
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
(i)
EXTAL
(ii)
TEX
XTAL
Rd
C1
RIVER
ELETEC
CO., LTD.
Rd
C2
Manufacturer
Model
HC-49/U03
TX
C2
C1
Rd (Ω)
Circuit
example
0
(i)
fc (MHz)
C1 (pF)
C2 (pF)
8.00
10
10
5
5
8.00
16 (12)
16 (12)
10.00
16 (12)
16 (12)
12.00
12
12
0
16.00
12
12
0
32.768kHz
30
18
470k
10.00
12.00
16.00
KINSEKI LTD.
HC-49/U (-S)
P3
0
(i)
(ii)
Product list
Option item
Package
ROM capacitance
Reset pin pull-up resistor
Input circuit format∗1
High voltage drive output port
pull-down resistor
Mask product
CXP881P60Q-1-
100-pin plastic QFP
100-pin plastic QFP
16K/20K/24K
(CXP88216/88220/88224)
32K/40K
(CXP88132/88140)
52K/60K
(CXP88152/88160)
PROM 60K bytes
Existent/non-existent
Existent
CMOS schmitt
/TTL schmitt
TTL schmitt
Existent/non-existent
Existent∗3
∗1 In PG4/SYNC0/EC2 pin and PG5/SYNC1 pin only.
∗2 OEM No.
∗3 No pull-down resistor for PD0/S0 to PD7/S7 pins.
– 23 –
∗2
CXP881P60
Characteristics Curve
IDD vs. VDD
IDD vs. fc
(fc = 16MHz, Ta = 25°C, Typical)
(VDD = 5.0V, Ta = 25°C, Typical)
1/2 dividing mode
1/4 dividing mode
1/16 dividing mode
10
40
32kHz mode
(instruction)
1
0.1
32kHz
SLEEP mode
IDD – Supply current [mA]
IDD – Supply current [mA]
SLEEP mode
1/2 dividing mode
20
1/4 dividing mode
0.01
1/16 dividing mode
0.001
SLEEP mode
2.5
3
4
5
VDD – Supply voltage [V]
0
6
– 24 –
5
10
fc – System clock [MHz]
15
CXP881P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
+ 0.1
0.15 – 0.05
80
51
+ 0.4
14.0 – 0.1
17.9 ± 0.4
15.8 ± 0.4
50
81
A
31
100
1
0.65
30
+ 0.15
0.3 – 0.1
0.13
+ 0.2
0.1 – 0.05
+ 0.35
2.75 – 0.15
M
0° to 10°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
QFP100-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.7g
JEDEC CODE
– 25 –