AD ADP1148AN-5 High efficiency synchronous step-down switching regulator Datasheet

a
High Efficiency Synchronous
Step-Down Switching Regulators
ADP1148, ADP1148-3.3, ADP1148-5
FEATURES
Operation From 3.5 V to 18 V Input Voltage
Ultrahigh Efficiency > 95%
Low Shutdown Current
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Wide Current Range
Logic Controlled Micropower Shutdown
Short Circuit Protection
Very Low Dropout Operation
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
FUNCTIONAL BLOCK DIAGRAM
ADJUSTABLE
VERSION
PWR SIGNAL
VIN P-DRIVE N-DRIVE GND
GND SENSE(+) VFB SENSE(–)
3
8
9
7
V
R
Q S
SLEEP
B
1
VTH1
Q R
S
C
13kV
10mV to
150mV
T
OFF-TIME
CONTROL
The ADP1148 is part of a family of synchronous step-down
switching regulator controllers featuring automatic sleep mode
to maintain high efficiencies at low output currents. These
devices drive external complementary power MOSFETs at
switching frequencies up to 250 kHz using a constant off-time
current-mode architecture.
11
2
VTH2
GENERAL DESCRIPTION
12
14
NON-OVERLAP
DRIVE
S
APPLICATIONS
Notebook and Palmtop Computers
Portable Instruments
Battery Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies
GPS Systems
Cellular Telephones
1
ADP1148
G
VIN
SENSE(–)
VFB
100kV
1.25V
REFERENCE
4
6
10
5
CT
ITH
SHUTDOWN
INT VCC
The constant off-time architecture maintains constant ripple
current in the inductor, easing the design of wide input range
converters. Current-mode operation provides excellent line and
load transient response. The operating current level is user
programmable via an external current sense resistor.
The ADP1148 incorporates automatic Power Saving Sleep
Mode operation when load currents drop below the level required for continuous operation. In sleep mode, standby power
is reduced to only about 2 mW at VIN = 10 V. In shutdown,
both MOSFETs are turned off.
TYPICAL APPLICATIONS
VIN (5.2V TO 18V)
+
CIN
100mF
1mF
VIN
INT VCC
0V = NORMAL
>1.5V = SHUTDOWN
VIN = 6V
95
P-CH
IRF7204
P-DRIVE
ADP1148
VIN = 10V
L* RSENSE**
62mH 0.05V
SHUTDOWN
VOUT
5V/2A
ITH
SENSE(+)
CT
SENSE(–)
1000pF
RC
1kV
CC
3300pF
CT
470pF
N-DRIVE
S-GND
P-GND
+
N-CH
IRF7403
COUT
390mF
EFFICIENCY – %
10nF
100
+
90
85
80
75
FIGURE 1 CIRCUIT
C1
10BQ040
70
0.02
0.2
LOAD CURRENT – A
2
*COILTRONICS CTX-68-4
**KRL SL-1-C1-0R050L
Figure 1. High Efficiency Step-Down Converter
Figure 2. ADP1148-5 Typical Efficiency
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
ADP1148, ADP1148-3.3, ADP1148-5–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (08C ≤ T ≤ +708C,
A
1
VIN = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.)
Parameter
Symbol
Conditions2
Min
Typ
Max
Units
FEEDBACK VOLTAGE
ADP1148 Only
V10
VIN = 9 V
1.21
1.25
1.29
V
FEEDBACK CURRENT
ADP1148 Only
I10
0.2
1.0
µA
3.33
5.05
3.43
5.2
V
V
+40
mV
65
100
mV
mV
REGULATED OUTPUT VOLTAGE
ADP1148-3.3
ADP1148-5
OUTPUT VOLTAGE LINE
REGULATION
VOUT
dVOUT
OUTPUT VOLTAGE LOAD
REGULATION
ADP1148-3.3
ADP1148-5
VIN = 9 V
ILOAD = 700 mA
ILOAD = 700 mA
3.23
4.9
TA = +25°C, VIN = 7 V to 12 V,
ILOAD = 50 mA
–40
dVOUT
5 mA < ILOAD < 2 A
5 mA < ILOAD < 2 A
40
60
dVOUT
ILOAD = 0 A
50
INPUT DC SUPPLY CURRENT
Normal Mode
Sleep Mode (ADP1148-3.3)
Sleep Mode (ADP1148-5)
Shutdown
IQ
TA = +25°C
VIN = 4 V < V IN < 18 V
VIN = 4 V < V IN < 18 V
VIN = 4 V < V IN < 18 V
VSHUTDOWN = 2.1 V,
4 V < VIN < 15 V
1.6
160
160
10
CURRENT SENSE THRESHOLD
VOLTAGE4
ADP1148 Only
V8–V7
SLEEP MODE OUTPUT RIPPLE
3
ADP1148-3.3
ADP1148-5
V9 = VOUT/4 + 25 mV (Forced),
V7 = 5 V, TA = +25°C
V9 = VOUT/4 mV – 25 mV (Forced),
V7 = 5 V
V7 = VOUT + 100 mV (Forced)
V7 = VOUT – 100 mV (Forced)
V7 = VOUT + 100 mV (Forced
V7 = VOUT – 100 mV (Forced)
mV p-p
2.3
250
250
20
25
130
mA
µA
µA
µA
mV
170
130
150
25
150
25
150
170
mV
mV
mV
mV
mV
0.6
0.8
2.0
V
1.2
5
µA
130
170
SHUTDOWN PIN THRESHOLD
ADP1148-3.3, ADP1148-5
V10
TA = +25°C
SHUTDOWN PIN INPUT CURRENT
I10
0 V < VSHUTDOWN < 8 V, VIN = 18 V
CT PIN DISCHARGE CURRENT
I4
TA = +25°C, VOUT in Regulation,
V7 = VOUT,
VOUT = 0 V
50
65
2
90
10
µA
µA
4
5
6
µs
100
200
ns
OFF-TIME
tOFF
CT = 390 pF, ILOAD = 700 mA
DRIVER OUTPUT TRANSITION
TIMES
tR, tF
CL = 3000 pF (Pins 1, 14)
VIN = 6 V, TA = +25°C
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Quality Control methods. Specifications subject to change without notice.
2
TJ is calculated from the ambient temperature T A and power dissipation P D according to the following formulas:
ADP1148AR, ADP1148AR-3.3, ADP1148AR-5: T J = T A + (PD × 110°C/W)
ADP1148AN, ADP1148AN-3.3, ADP1148AN-5: T J = T A + (PD × 70°C/W)
3
Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.
4
The ADP1148 version is tested with external feedback resistors, setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
–2–
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
ELECTRICAL CHARACTERISTICS (–408C ≤ T
A
1
≤ +858C, VIN = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.)
Parameter
Symbol
Conditions2
Min
Typ
Max
Units
FEEDBACK VOLTAGE
ADP1148 Only
V10
VIN = 9 V
1.20
1.25
1.30
V
REGULATED OUTPUT VOLTAGE
ADP1148-3.3
ADP1148-5
VOUT
VIN = 9 V
ILOAD = 700 mA
ILOAD = 700 mA
3.17
4.85
3.33
5.05
3.4
5.2
V
V
INPUT DC SUPPLY CURRENT3
Normal Mode
Sleep Mode (ADP1148-3)
Sleep Mode (ADP1148-5)
Shutdown
IQ
VIN = 4 V < V IN < 18 V
VIN = 4 V < V IN < 18 V
VIN = 6 V < V IN < 18 V
VSHUTDOWN = 2.1 V,
4 V < VIN < 12 V
1.6
160
160
10
2.6
280
280
24
mA
µA
µA
µA
V9 = VOUT/4 + 25 mV (Forced),
V7 = 5 V
V9 = VOUT/4 – 25 mV (Forced),
V7 = 5 V
V7 = VOUT + 100 mV (Forced)
V7 = VOUT – 100 mV (Forced)
V7 = VOUT + 100 mV (Forced)
V7 = VOUT – 100 mV (Forced)
0
CURRENT SENSE THRESHOLD
VOLTAGE4
ADP1148 Only
V8–V7
ADP1148-3.3
ADP1148-5.0
SHUTDOWN PIN THRESHOLD
ADP1148-3.3, ADP1148-5
V10
OFF-TIME
tOFF
115
175
mV
115
0
150
0
150
175
mV
mV
mV
mV
0.55
0.8
2
V
4
5
6.2
µs
115
CT = 390 pF, ILOAD = 700 mA
150
mV
175
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Quality Control method.
2T is calculated from the ambient temperature T and power dissipation P according to the following formulas:
J
A
D
ADP1148AR, ADP1148AR-3, ADP1148AR-5: T J = TA + (PD × 110°C/W)
ADP1148AN, ADP1148AN-3, ADP1148AN-5: T J = TA + (PD × 70°C/W)
3Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.
4The ADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (Pin 3) . . . . . . . . . . . . . –0.3 V to +20 V
Continuous Output Currents (Pins 1, 14) . . . . . . . . . . 50 mA
Sense Voltages (Pins 7, 8) . . . . . . . . . . . . . . . . –0.3 V to VCC
Operating Temperature Range . . . . . . . . . . . . 0°C to +70°C
Extended Commercial Temperature Range . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
REV. A
ORDERING GUIDE
Model
Output
Voltage
Package
Description
Package
Option
ADP1148AN
ADP1148AR
ADP1148AN-3.3
ADP1148AR-3.3
ADP1148AN-5
ADP1148AR-5
ADJ
ADJ
3.3 V
3.3 V
5V
5V
Plastic DIP
Small Outline Package
Plastic DIP
Small Outline Package
Plastic DIP
Small Outline Package
N-14
SO-14
N-14
SO-14
N-14
SO-14
–3–
ADP1148, ADP1148-3.3, ADP1148-5
PIN FUNCTION DESCRIPTIONS
Pin #
Mnemonic
Function
1
P-Channel Drive
High Current Gate Drive for Top P-Channel MOSFET. The voltage swing at Pin 4 is from VIN to
ground.
2
NC
No Connection.
3
VIN
Input Voltage.
4
CT
External Capacitor CT from Pin 4 to Ground Sets the Operating Frequency. The frequency is also
dependent on the ratio VOUT/VIN.
5
Int VCC
Internal Supply Voltage, Nominally 3.3 V. Must be decoupled to signal ground. Do not externally load
this pin.
6
ITH
Error Amplifier Decoupling Point. The current comparator threshold increases with the Pin 7 voltage.
7
Sense–
Connects to internal resistive divider that sets the output voltage in ADP1148-3.3 and ADP1148-5
versions. Pin 7 is also the (–) input for the current comparator.
8
Sense+
The (+) Input for the Current Comparator. A built-in offset between Pins 7 and 8, in conjunction with
RSENSE, sets the current trip threshold.
9
VFB
For the ADP1148 adjustable version, Pin 9 serves as the feedback pin from an external resistive divider
used to set the output voltage. On ADP1148-3.3 and ADP1148-5 versions, this pin is not used.
10
Shutdown
Taking Pin 10 of the ADP1148, ADP1148-3.3 or ADP1148-5 high holds both MOSFETs off. Must be
at ground potential for normal operation.
11
Signal GND
Small Signal Ground. Must be routed separately from other grounds to the (–) terminal of COUT.
12
Power GND
Driver Power Ground. Connects to source of N-channel MOSFET and the (–) terminal of CIN.
13
NC
No Connection.
14
N-Channel Drive High Current Drive for bottom N-channel MOSFET. The voltage swing at Pin 13 is from ground to
VIN.
PIN CONFIGURATIONS
14-Lead Plastic DIP
14-Lead Plastic SO
P-DRIVE 1
14 N-DRIVE
13 NC
NC 2
VIN 3
CT 4
INT VCC
5
ADP1148
12 POWER GND
TOP VIEW 11 SIGNAL GND
(Not to Scale)
10 SHUTDOWN
ITH 6
9
VFB*
SENSE(–) 7
8
SENSE(+)
NC = NO CONNECT
*FIXED OUTPUT VERSIONS = SD1
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
Typical Performance Characteristics–ADP1148, ADP1148-3.3, ADP1148-5
200
1000
1000
VSENSE = VOUT = 5V
800
CAPACITANCE – pF
50
400
VIN = 12V
0
1
2
3
VIN = 10V
0
0
5
4
100
200
FREQUENCY – kHz
MAXIMUM OUTPUT CURRENT – A
Figure 3. Selecting RSENSE vs. Maximum Output Current
0
1
2
3
4
(VIN–VOUT) VOLTAGE – V
5
Figure 5. Selecting Minimum Output
Capacitor vs. (VIN–VOUT ) and Inductor
+40
+20
96
95
94
EFFICIENCY – %
IQ
90
85
ILOAD = 1A
92
90
ILOAD = 100mA
88
82
80
0.01
0.03
0.1
0.3
1.0
OUTPUT CURRENT – A
3.0
Figure 6. Typical Efficiency Losses
–60
4
8
12
16
INPUT VOLTAGE – V
20
SUPPLY CURRENT – mA
SUPPLY CURRENT – mA
0.8
0.6
0.4
SLEEP MODE
0.5
1.0
1.5
2.0
LOAD CURRENT – A
Figure 9. Load Regulation
REV. A
2.5
10
12
14
16
20
VSHUTDOWN = 2V
15
10
5
0.2
0
8
25
1.0
0.0
6
Figure 8. ADP1148-5 Output Voltage
Change vs. Input Voltage
ACTIVE MODE
1.2
VIN = 12V
–40
4
30
1.4
–20
0
VIN
Figure 7. Efficiency vs. Input Voltage
FIGURE 1 CIRCUIT
–60
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
40
0
–20
ILOAD = 1A
1.6
VIN = 6V
ILOAD = 0.1A
–40
80
0
60
20
0
86
84
DVOUT – mV
L = 50mH
RSENSE = 0.05V
98
GATE CHARGE
EFFICIENCY/LOSS – %
0
300
100
I 2R
400
200
Figure 4. Operating Frequency vs.
Timing Capacitor Value
100
L = 25mH
RSENSE = 0.02V
600
VIN = 7V
200
0
COUT – mF
600
DVOUT – mV
RSENSE – mV
100
L = 50mH
RSENSE = 0.02V
800
150
4
6
8
10 12
14
16
INPUT VOLTAGE – V
18
Figure 10. DC Supply Current
–5–
20
0
4
6
8
10 12 14
16
INPUT VOLTAGE – V
18
20
Figure 11. Supply Current in Shutdown
ADP1148, ADP1148-3.3, ADP1148-5–Typical Performance Characteristics
1.8
1.4
1.2
708C
258C
1.0
0.8
0.6
0.4
70
25
60
20
Qn+Qp = 100nC
15
10
Qn+Qp = 50nC
OFF TIME – msec
08C
GATE CHARGE CURRENT – mA
NORMALIZED FREQUENCY
80
30
1.6
50
40
30
5V
20
5
3.3V
10
0.2
0.0
1
2
4
6
8
(VIN–VOUT) – V
10
12
Figure 12. Operating Frequency vs.
(VIN–VOUT )
0
20
80 110 140 170 200 230 260
50
OPERATING FREQUENCY – kHz
Figure 13. Gate Charge Supply
Current
0
0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.3 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE – V
Figure 14. Off Time vs. VOUT
155
SENSE VOLTAGE – mV
150
145
MAXIMUM THRESHOLD
140
135
130
125
120
0
85
25
70
TEMPERATURE – 8C
100
Figure 15. Current Sense Threshold
Voltage
–6–
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
APPLICATIONS
The ADP1148 uses a current-mode, constant off-time structure
to switch a pair of external complementary N- and P-channel
MOSFETs. The operating frequency of the device is determined by the value of the external capacitor connected to the
CT pin.
The output voltage is sensed by an internal voltage divider which is
connected to the Sense(–) pin (ADP1148-3.3 and AD1148-5) or
an external voltage divider returned to VFB (ADP1148). A voltage
comparator V, and a gain block G compare the values of the
divided output voltage with a reference voltage of 1.25 V.
To maximize the efficiency, the ADP1148 automatically switches
between two operational modes, power-saving and continuous.
The Flip-Flop 1 is the main control element when the device is
in its power-saving mode while the gain block is the main control when the output voltage moves to continuous mode. During
the continuous mode of the PMOS switch on-cycle, the current
comparator C, monitors the voltage between Sense(–) and
Sense(+). When the voltage level reaches the threshold level, the
P drive output is switched to VIN which turns off the P-channel
MOSFET. The timing capacitor CT is now able to discharge at
a rate determined by the off-time controller. The discharge
current is made to be proportional to the value of the output
voltage (measured at the Sense(–) pin) to model the inductor
current which decays at a rate which is proportional to the output voltage. While the timing capacitor is discharging, the N
drive output goes to VIN , turning on the N-channel MOSFET.
When the voltage level on the timing capacitor has discharged to
the threshold voltage level VTH1, comparator T switches setting
Flip-Flop 1. This forces the N drive to go off and the P drive
output low and subsequently turns the P-channel MOSFET on.
The sequence is then repeated. As load current increases, the
output voltage starts to reduce. This results in the output of the
gain circuit increasing the level of the current comparator threshold, thus tracking the load current.
At very low load currents the power-saving sequence will be
interrupted by the Set of Flip-Flop 2, by voltage comparator B,
which also monitors the voltage across RSENSE. When the load
current decreases to half the designed inductor ripple current,
the voltage across RSENSE will reverse polarity. When this happens, comparator B will set the Q-bar output of Flip-Flop 2,
which will go to logic zero state and interrupt the cycle-by-cycle
operation and inhibit the output FET-driver. The output of the
power supply storage capacitor will slowly be drained by the
load and the output voltage starts decreasing. When this
decreased voltage exceeds the VOS of comparator V, this in turn
will reset Flip-Flop 2, and normal cycle-by-cycle operation will
resume. If the load is very small, it will take a long time for FlipFlop 2 to reset, and during that time the oscillator capacitor
may discharge below VTH2. At the point at which the timing
capacitor discharges below VTH2, comparator S trips causing the
internal sleep-bar to go low. The circuit is now in sleep mode
and the N-channel Power MOSFET remains turned off. While
the circuit remains in this mode, a significant amount of the
circuit of the IC is turned off dropping the ground current from
approximately 1.6 mA to a level of 160 µA. In this state the load
current is supplied by the output capacitor. The sleep mode is
also terminated by the reset of Flip-Flop 2.
To prevent both the external MOSFETs from ever being turned
on simultaneously, feedback is incorporated to sense the state of
the driver output pins.
Before the N drive output can go high, the P drive output must
also be high. Likewise, the P drive output is unable to go low
while the N drive output is high. By utilizing a constant off-time
structure, the device operation is a function of the input voltage.
To limit the effect of frequency variation as the device approaches
dropout, the controller begins to increase the discharge current
as V IN drops below VOUT +1.5 V. While the device is in dropout, the P-channel MOSFET is on constantly.
RSENSE Selection For Output Current
The choice of RSENSE is based on the required output current.
The ADP1148 current comparator has a threshold range which
extends from 0 mV to a maximum of 150 mV/RSENSE. The
current comparator threshold sets the peak of the inductor current, yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. The ADP1148
operates effectively with values of RSENSE from 20 mΩ to
200 mΩ. A graph for selecting RSENSE versus maximum output
current is given in Figure 3. Solving for RSENSE and allowing a
margin for variations in the ADP1148 and external component
values yields:
RSENSE = 100 mV/IMAX
The peak short circuit current, (ISC(PK) ) tracks IMAX. Once
RSENSE has been chosen, ISC(PK) can be predicted from the following equation:
ISC(PK) = 150 mV/RSENSE
The load current, below which power-saving mode commences
(IPOWER-SAVING) is determined by the offset in comparator B and
the value of the inductor chosen. Comparator B is designed to
have approximately 5 mV offset. This offset and the inductor
can now be used to predict the power saving mode current as
follows:
IPOWER-SAVING ~ 5 mV/RSENSE + VO × tOFF /2 L
The ADP1148 automatically extends tOFF during a short circuit
to provide adequate time for the inductor current to decay between switch cycles. The resulting ripple current causes the
average short circuit current, ISC(AVG), to be lowered to approximately IMAX.
L and C T Selection for Operating Frequency
The ADP1148 uses a constant off-time architecture with tOFF
determined by an external timing capacitor CT . Each time the
P-channel MOSFET switch turns on, the voltage on CT is reset
to approximately 3.3 V. During the off time, CT is discharged by
a current which is proportional to VOUT. The voltage on CT is
analogous to the current in inductor L, which likewise decays at
a rate proportional to VOUT. Therefore, the inductor value must
track the timing capacitor value.
The value of CT is calculated from the preferred continuous
mode operating frequency:
CT = 1/2.6 × 104 × f
Assumes VIN = 2 VOUT (Figure 1 circuit).
A graph for selecting CT versus frequency including the effects
of input voltage is given in Figure 5.
*Component, voltage, current, etc., values are in SI-units (international standard)
unless otherwise indicated.
REV. A
–7–
ADP1148, ADP1148-3.3, ADP1148-5
As the operating frequency is increased, the gate charge losses
will cause reduced efficiency (see Efficiency section). The full
formula for operating frequency is given by:
components are also available from Coiltronics which do not
increase the component height significantly.
Power MOSFET
f = ( 1 – VOUT/VIN )/tOFF
Two external power MOSFETs must be selected for use with
the ADP1148, a P-channel MOSFET for the main switch, and
an N-channel MOSFET for the synchronous switch. The main
selection parameters for the power MOSFETs are the threshold
voltage VGS(TH) and on resistance RDS(ON) .
where tOFF = 1.3 × 104 × CT × VREG /VOUT.
VREG is the desired output voltage (i.e., 5 V or 3.3 V), VOUT is
the measured output voltage. Thus, VREG/VOUT = 1 in regulation.
Note that as VIN reduces, the frequency also decreases. When
the input to output voltage differential drops below 1.5 V, the
ADP1148 reduces tOFF by increasing the discharge current in
CT. This prevents audible operation before the device goes into
dropout.
The minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFETs must be used. For VIN > 8 V,
standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If
VIN is expected to drop below 8 V, logic-level threshold MOSFETs
(VGS(TH) < 2.5 V) are strongly recommended. When logic-level
MOSFETs are used, the ADP1148 supply voltage must be less
than the absolute maximum VGS rating for the MOSFETs (e.g.,
>± 8 V of IRF7304.
Once the frequency has been set by CT , the inductor L must be
chosen to provide no more than 25 mV/RSENSE of peak-to-peak
inductor ripple current. This is set by the equation:
The maximum output current IMAX determines the RDS(ON)
requirement for the two power MOSFETs. When the ADP1148
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. The duty cycles for the MOSFET and
diode are given by:
25 mV
×t
V
= OUT OFF
LMIN
RSENSE
or
LMIN =
V OUT × tOFF × RSENSE
25 mV
P-Channel Duty Cycle = VOUT/VIN
Substituting for tOFF from above gives the minimum required
inductor value of:
N-Channel Duty Cycle = (VIN – VOUT)/VIN
From the duty cycle the required RDS(ON) for each MOSFET
can be derived:
LMIN = 5.1 × 105 × RSENSE × CT × VREG
As the inductor value increases above the minimum value, the
ESR requirements for the output capacitor are relaxed at the
expense of efficiency. If too small an inductor is used, the inductor current will decrease past zero and change polarity. A result
of this occurrence will be that the ADP1148 may not be in
power saving mode operation and efficiency will be significantly
reduced at low currents.
P-Ch RDS(ON) = (VIN × PP )/[VOUT × IMAX2 × (1 + dP )]
N-Ch
RDS(ON)
= (VIN × PN)/[(VIN – VOUT) × IMAX2 × (1+dN)]
where Pp and PN are the allowable power dissipations and dp and
dN are the temperature dependency of RDS(ON). PP and PN will
be determined by efficiency and/or thermal requirements (see
Efficiency). (1+d) is generally given for a MOSFET in the form
of a normalized RDS(ON) vs. temperature curve, but d = 0.007/°C
can be used as an approximation for low voltage MOSFETs.
Inductor Core
Once the minimum value for L is known, the selection of the
inductor must be made. High efficiency converters -π generally
cannot accommodate the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite, molypermalloy
(MPP), or Kool Mµ® cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
The Schottky diode D1 shown in Figure 1 conducts only during
the deadtime between the conduction of the two power
MOSFETs. D1’s purpose is to prevent the body-diode of the
N-channel MOSFET from turning on and storing charge during
the dead time, which could cost as much as 1% in efficiency. D1
should be selected for forward voltage of less than 0.5 V when
conducting IMAX.
C IN and COUT Selection
Ferrite designs have very low core loss, so design goals can focus
on copper loss and preventing saturation. Ferrite core material
saturates “hard,” which causes the inductance to collapse
abruptly when the peak design current is exceeded. This results
in a sharp increase in inductor ripple current and subsequently
output voltage ripple which can cause the power saving mode
operation to be falsely triggered in the ADP1148. To prevent
this action from occurring, do not allow the core to saturate!
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/VlN . To prevent
large voltage transients, a low ESR input capacitor sized for the
maximum rms current must be used. The maximum rms capacitor current is given by:
CIN required
IRMS ~ [VOUT(VIN – VOUT)]0.5 × IMAX/VIN
This formula has a maximum at VIN = 2 VOUT, where IRMS =
IOUT/2. This simple worst case condition is commonly used for
design because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor
rated at a higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any question.
Molypermalloy from Magnetics, Inc., is a very good, low loss
core material for toroids, but it is more expensive than ferrite. A
reasonable compromise from the same manufacturer is Kool
Mµ. Toroids are very space efficient, especially when you can
use several layers of wire. Because they generally lack a bobbin,
mounting is more difficult. Many new designs for surface mount
All trademarks are the property of their respective holders.
–8–
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
An additional 0.1 µF – 1 µF ceramic bypass capacitor is advised
on VIN Pin 3 parallel with CIN. The selection of COUT is driven
by the required effective series resistance (ESR). The ESR of
COUT must be less than twice the value of RSENSE for proper
operation of the ADP1148:
COUT required ESR < 2 RSENSE.
Optimum efficiency is obtained by making the ESR equal to
RSENSE. As the ESR is increased up to 2 RSENSE, the efficiency
degrades by less than 1%.
Manufacturers such as Sprague, and United Chemmicon should
be considered for high performance capacitors. The OS-CON
semiconductor dielectric capacitor has the lowest ESR for its
size, at a somewhat higher price. Once the ESR requirement for
COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement.
In surface-mount applications multiple capacitors may have to
be paralleled to meet the capacitance, ESR, or RMS current
handling requirements of the application. Aluminum electrolytic
and dry tantalum capacitors are both available in surface-mount
configurations. In the case of tantalum, it is critical that the
capacitors are surge tested for use in switching power supplies.
Consult the manufacturer for other specific recommendations.
The CO output filter capacitor has to be sized correctly to avoid
excessive ripple voltages at low frequencies. See Figure 5 for
output capacitor selection.
Transient Response
The regulator loop response can be checked by looking at the
load transient response. Switching regulators take several cycles
to respond to a step in dc (resistive) load current. When a load
step occurs, VOUT shifts by an amount equal to D1LOAD × ESR,
where ESR is the effective series resistance of COUT. D1LOAD
also begins to charge or discharge COUT until the regulator loop
adapts to the current change and returns VOUT to its steadystate value. During this recovery time VOUT can be monitored
for overshoot or ringing which would indicate a stability problem. The external components on the ITH pin shown in the
Figure 1 circuit will prove adequate compensation for most
applications.
A second, more severe transient is caused by switching in loads
with large (>1 mF) supply bypass capacitors. The discharged
bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low
and it is driven quickly. The only solution is to limit the inrush
current to these capacitors below the current limit of the circuit.
Efficiency
The percent efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is limiting
the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as:
% Efficiency = 100% - (L1 + L2 + L3 +. . . )
where L1, L2, etc. are the individual losses as a percentage of
input power. (For high efficiency circuits only small errors are
incurred by expressing losses as a percentage of output power.)
REV. A
Although all dissipative elements in the circuit produce losses,
three main sources usually account for most of the losses in
ADP1148 circuits:
1) ADP1148 dc bias current,
2) MOSFET gate charge currents,
3) I2 × R losses.
1) The dc supply current is the current which flows into VIN Pin
3 less the gate charge current. For VIN = 10 V the ADP1148
dc supply current is 160 µA for no load, and increases proportionally with load up to a constant 1.6 mA after the
ADP1148 has entered continuous mode. Because the dc bias
current is drawn from VIN, the resulting loss increases with
input voltage. For VIN = 10 V the dc bias losses are generally
less than 1% for load currents over 30 mA. However, at very
low load currents the dc bias current accounts for nearly all
of the loss.
2) MOSFET gate charge currents result from switching the gate
capacitance of the power MOSFETs. Each time a MOSFET
gate is switched from low to high to low again, a packet of
charge dQ moves from VIN to ground. The resulting dQ/dt is
a current out of VIN which is typically much larger than the
dc supply current. In continuous mode, IGATECHG = f (QP +
QN). The typical gate charge for a 100 mΩ N-channel power
MOSFET is 25 nC and for the P-channel about twice that
value. This results in IGATECHG = 7.5 mA in 100 kHz continuous operation for a 2% to 3% typical midcurrent loss with
VIN = 10 V.
Note that the gate charge loss increases directly with both
input voltage and operating frequency. This is the principal
reason why the highest efficiency circuits operate at moderate
frequencies. Furthermore, it argues against using a larger
MOSFET than necessary to control I2 × R losses.
3) I2 × R losses are easily predicted from the dc resistances of
the MOSFET, inductor, and current shunt. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the P-channel and Nchannel MOSFETs. If the two MOSFETs have about the
same RDS(ON), the resistance of one MOSFET can be simply
summed with the resistances of L and RSENSE to obtain I2 × R
losses. For example, if each RDS(ON) = 100 mΩ, RL = 150 mΩ,
and RSENSE = 50 mΩ, then the total resistance is 300 mΩ.
This results in losses ranging from 3% to 10% as the output
current increases from 0.5 A to 2 A. I2 × R losses cause the
efficiency to roll-off at high output currents.
Figure 6 shows how the efficiency losses in a typical ADP1148
regulator. The gate charge loss is responsible for the majority of
the efficiency lost in the midcurrent region. If power saving
mode operation was not employed at low currents, the gate
charge loss alone would cause the efficiency to drop to unacceptable levels. With power saving mode operation, the dc supply
current represents the lone (and unavoidable) loss component
which continues to become a higher percentage as output current is reduced. As expected, the I2 × R losses dominate at high
load currents. Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, generally
account for less than 2% total additional loss.
–9–
ADP1148, ADP1148-3.3, ADP1148-5
Design Example
Output Crowbar
As a design example, assume VIN = 12 V (nominal), VOUT = 5 V,
IMAX = 2 A, and f = 200 kHz, RSENSE. C T, and L can immediately be calculated:
An added feature to using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the
same MOSFET. Pulling the timing cap CT pin above 1.5 V
when the output voltage is greater than the desired regulated
value will turn “on” the N-channel MOSFET and turn “off” the
P-channel MOSFET.
RSENSE = 100 mV/2 = 50 mΩ
t OFF = (1/200 kHz) × [1 – (5/12)] = 2.92 µs
CT = 2.92 µs/(1.3 × 104) = 220 pF
A fault condition such as an external short between VIN and
VOUT, or an internal short of the P-channel device which causes
the output voltage to go above a maximum allowable value can
be detected by external circuity. Turning on the N-channel
MOSFET when this fault is detected will cause large currents to
flow and blow the system fuse.
L min = 5.1 × 105 × 50 E-3 Ω × 220 pF × 5 V = 28 µH
Assume that the MOSFET dissipations are to be limited to
PN = 2PP = 250 mW.
If TA = 50°C and the thermal resistance of each MOSFET is
50°C/W, then the junction temperatures will be 63°C and dP =
dP = 0.007 × (63–25) = 0.27.
The required RDS(ON) for each MOSFET can now be calculated:
P-Ch RDS(ON) = 12 × 0.25/5 × 2 × 1.27 = 120 mΩ
N-Ch RDS(ON) = 12 × 0.25/7 × 2 × 1.27 = 85 mΩ
The P-channel requirement can be met by a IRF7204. The
N-channel requirement can be met by a IRF7404. Note that
the most stringent requirement for the N-channel MOSFET is
with VOUT = 0 (i.e., short circuit). During a continuous short
circuit, the worst case N-channel MOSFET dissipation rises to:
The N-channel MOSFET needs to be sized so it will safely
handle this over current condition. The typical delay from pulling the CT pin high and the N drive, Pin 14 going high is 250 ns.
Note: under shutdown conditions, the N-channel MOSFET
is held OFF and pulling the CT pin high will not cause the
N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface between
the overvoltage detect circuitry and the ADP1148 as shown in
Figure 16.
5
PN ~ ISC(AVG)2 × RDS(ON) × (1 + dN)
*FROM CROWBAR
DETECT CIRCUIT
With the 50 mΩ sense resistor I SC(AVG) = 2 A will result, increasing the N-channel dissipation to 0.45 W at die temperature of
73°C.
INT VCC
ADP1148
4
CT
*ACTIVE WHEN VGATE = VIN
OFF WHEN VGATE = GROUND
CIN will require an rms current rating of at least 1 A at temperature, and COUT will require an ESR of 50 mΩ for optimum
efficiency.
Now allow VIN to drop to its minimum value. At lower input
voltages, the operating frequency will decrease and the Pchannel will be conducting most of the time causing the power
dissipation to increase. At VIN(MIN) = 7 V, the frequency shifts
to:
VN2222LL
Figure 16. Output Crowbar Interface
Troubleshooting
Since efficiency is critical to ADP1148 applications, it is very
important to verify that the circuit is functioning correctly in
both continuous and power saving mode operation. The waveform to monitor is the voltage on the timing capacitor
CT pin.
fMIN = (1 – VOUT/VIN)/t OFF = (1/2.92 µs) × (1 – 5/7) = 98 kHz
In continuous mode (ILOAD > IPOWER SAVING MODE ), the voltage
on the CT pin should be a sawtooth with a 0.9 V p-p swing. This
voltage should never dip below 2 V as shown in Figure 17a.
and the P-channel power dissipation increases to:
PP = (120 mΩ) (2 A)2 (1.27) 5 V/7 V = 435 mW
This last step is needed to ensure the maximum temperature of
the P-channel MOSFET is not exceeded.
When load currents are low (ILOAD < IPOWER SAVING MODE), power
saving mode operation occurs. The voltage on the CT pin now
falls to ground for periods of time as shown in Figure 17b. If the
CT pin is observed falling to ground at high output currents, it
indicates poor decoupling or improper grounding. Refer to the
Board Layout list.
ADP1148 Adjustable Applications
When an output voltage other than 3.3 V or 5 V is required, the
ADP1148 adjustable version is used with an external resistive
divider from VOUT to VFB Pin 9. The regulated voltage is determined by:
3.3V
VOUT = 1.25 (1 + R2/R1)
0V
To prevent a stray pickup, a 100 pF capacitor is suggested across
R1 located close to the ADP1148.
(A) CONTINOUS MODE OPERATION
Auxiliary Windings
3.3V
The ADP1148 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With
synchronous switching, auxiliary outputs may be loaded without
regard to the primary output load, providing that the loop remains in continuous mode operation.
–10–
0V
(B) POWER-SAVING MODE
Figure 17. CT Waveforms
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
4) Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? This capacitor
provides the ac current to the P-channel MOSFET.
Board Layout
When laying out the printed circuit board, the following check
list should be used to ensure proper operation of the ADP1148.
These items are also illustrated graphically in the layout diagram
of Figure 18. Check the following in your layout:
5) Is the input decoupling capacitor (1 µF) connected closely
between VIN (Pin 3) and POWER GND (Pin 12)? This
capacitor carries the MOSFET driver peak currents.
1) Are the signal and power grounds segregated? The ADP1148
SIGNAL GND (Pin 11) must return to the (–) plate of COUT.
The power ground returns to the source of the N-channel
MOSFET, anode of the Schottky diode, and (–) plate of CIN,
which should have as short lead lengths as possible.
6) Is INTVCC (Pin 5) decoupled with a 10 nF capacitor to
signal ground?
7) Is the SHUTDOWN (Pin 10) actively pulled to ground
during normal operation? The Shutdown pin is high impedance and must not be allowed to float.
2) Does the ADP1148 SENSE(–), (Pin 7), connect to a point
close to RSENSE and the (+) plate Of COUT? In adjustable
versions the resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground.
To prevent noise spikes from erroneously tripping the current
comparator, a 1000 pF capacitor is needed across Sense(–) and
Sense(+).
3) Are the SENSE(–) and SENSE(+) leads routed together with
minimum PC trace spacing? The 1000 pF capacitor between
Pins 7 and 8 should be as close as possible to the ADP1148.
P-CHANNEL
CIN
D1
VIN
–
1
N-DRIVE
P-DRIVE
NC 13
2 NC
1mF
3
4
CT
5
3300pF
10nF
1kV
6
7
14
ADP1148
VIN
CT
POWER GND
SIGNAL GND
12
SHUTDOWN
ITH
VFB
SENSE(–)
SENSE(+)
L
11
10
INT VCC
N-CHANNEL
–
R1
COUT
9
8
VOUT
R2
RSENSE
1000pF
R1, R2 OUTPUT DIVIDER REQUIRED
FOR ADJUSTABLE VERSION ONLY.
NC = NO CONNECT
Figure 18. ADP1148 Layout Diagram (See Board Layout)
REV. A
–11–
ADP1148, ADP1148-3.3, ADP1148-5
VIN
4V TO 18V
IRF7204
CIN
100mF
20V
D1
10BQ040
IRF7403
1
2
1mF
3
4
CT
300pF
5
10nF
6
CC
3300pF
7
N-DRIVE
P-DRIVE
NC
NC
ADP1148-3.3
VIN
POWER GND
CT
SIGNAL GND
INT VCC
SHUTDOWN
ITH
VFB
SENSE(–)
SENSE(+)
14
13
*L
50mH
12
11
10
9
8
1000pF
RC
1kV
**RSENSE
0.1V
COUT
220mF
10V 3 2
AVX
VOUT
3.3V/1A
NC = NO CONNECT
*COILTRONICS CTX50-2-MP
**KRL SP-1/2-A1-0R100J
Figure 19. ADP1148 Low Dropout, 3.3 V/1 A High Efficiency Regulator
VIN
4V TO 9V
IRF7204
D1
10BQ015
CIN
220mF
20V
IRF7403
1
2
1mF
3
4
CT
560pF
5
10nF
6
CC
6800pF
7
P-DRIVE
NC
N-DRIVE
ADP1148
NC
VIN
POWER GND
CT
SIGNAL GND
INT VCC
ITH
SHUTDOWN
VFB
SENSE(–)
SENSE(+)
14
13
*L
50mH
12
11
VOUT
–5V/1.4A
10
200pF
25kV
1%
9
COUT
220mF 3 2
10V
8
RC
1kV
1000pF
**RSENSE
0.05V
75kV
1%
NC = NO CONNECT
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R05J
Figure 20. 4 V to 9 V Input Voltage to –5 V/1.4 A Regulator
–12–
REV. A
ADP1148, ADP1148-3.3, ADP1148-5
VIN
5.2V TO 14V
IRF7204
D1
10BQ040
CIN
100mF
20V
IRF7403
1
2
1mF
3
4
CT
390pF
5
10nF
6
CC
3300pF
RC
1kV
7
P-DRIVE
NC
14
N-DRIVE
ADP1148
NC
13
VIN
POWER GND
CT
SIGNAL GND
INT VCC
VFB
SENSE(–)
SENSE(+)
VN2222LL
0V: VOUT = 3.3V
5V: VOUT = 5V
11
10
SHUTDOWN
ITH
*L
50mH
12
100pF
R1A
33kV
1%
R1B
43kV
1%
9
8
1000pF
NC = NO CONNECT
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050J
**RSENSE
0.05V
R2
56kV
1%
COUT
220mF
10V 3 2
OS-CON
VOUT
3.3V/2A
OR 5V/2A
Figure 21. Logic Selectable 5 V/1 A or 3.3 V/2 A High Efficiency Regulator
REV. A
–13–
ADP1148, ADP1148-3.3, ADP1148-5
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
0.795 (20.19)
0.725 (18.42)
14
8
1
7
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100 0.070 (1.77)
(2.54) 0.045 (1.15)
BSC
14-Lead Plastic SO
(SO-14)
0.3444 (8.75)
0.3367 (8.55)
0.1574 (4.00)
0.1497 (3.80)
14
8
1
7
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0500
(1.27)
BSC
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
–14–
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
REV. A
–15–
–16–
PRINTED IN U.S.A.
C2219a–2–12/97