AD AD802 Clock recovery and data retiming phase-locked loop Datasheet

a
Clock Recovery and Data Retiming
Phase-Locked Loop
AD800/AD802
FEATURES
Standard Products
44.736 Mbps—DS-3
51.84 Mbps—STS-1
155.52 Mbps—STS-3 or STM-1
Accepts NRZ Data, No Preamble Required
Recovered Clock and Retimed Data Outputs
Phase-Locked Loop Type Clock Recovery—No Crystal
Required
Random Jitter: 208 Peak-to-Peak
Pattern Jitter: Virtually Eliminated
10KH ECL Compatible
Single Supply Operation: –5.2 V or +5 V
Wide Operating Temperature Range: –408C to +858C
PRODUCT DESCRIPTION
The AD800 and AD802 employ a second order phase-locked
loop architecture to perform clock recovery and data retiming
on Non-Return to Zero, NRZ, data. This architecture is
capable of supporting data rates between 20 Mbps and 160
Mbps. The products described here have been defined to work
with standard telecommunications bit rates. 45 Mbps DS-3 and
52 Mbps STS-1 are supported by the AD800-45 and
AD800-52 respectively. 155 Mbps STS-3 or STM-1 are
supported by the AD802-155.
Unlike other PLL-based clock recovery circuits, these devices
do not require a preamble or an external VCXO to lock onto
input data. The circuit acquires frequency and phase lock using
two control loops. The frequency acquisition control loop
initially acquires the clock frequency of the input data. The
phase-lock loop then acquires the phase of the input data, and
ensures that the phase of the output signals track changes in the
phase of the input data. The loop damping of the circuit is
dependent on the value of a user selected capacitor; this defines
jitter peaking performance and impacts acquisition time. The
devices exhibit 0.08 dB jitter peaking, and acquire lock on
random or scrambled data within 4 × 105 bit periods when
using a damping factor of 5.
FUNCTIONAL BLOCK DIAGRAM
CD
DATA
INPUT
ØDET
COMPENSATING
ZERO
∑
LOOP
FILTER
VCO
RECOVERED
CLOCK
OUTPUT
fDET
RETIMED
DATA
OUTPUT
RETIMING
DEVICE
AD800/AD802
FRAC
OUTPUT
During the process of acquisition the frequency detector
provides a Frequency Acquisition (FRAC) signal which
indicates that the device has not yet locked onto the input data.
This signal is a series of pulses which occur at the points of cycle
slip between the input data and the synthesized clock signal.
Once the circuit has acquired frequency lock no pulses occur at
the FRAC output.
The inclusion of a precisely trimmed VCO in the device
eliminates the need for external components for setting center
frequency, and the need for trimming of those components. The
VCO provides a clock output within ± 20% of the device center
frequency in the absence of input data.
The AD800 and AD802 exhibit virtually no pattern jitter, due
to the performance of the patented phase detector. Total loop
jitter is 20° peak-to-peak. Jitter bandwidth is dictated by mask
programmable fractional loop bandwidth. The AD800, used for
data rates < 90 Mbps, has been designed with a nominal loop
bandwidth of 0.1% of the center frequency. The AD802, used
for data rates in excess of 90 Mbps, has a loop bandwidth of
0.08% of center frequency.
All of the devices operate with a single +5 V or –5.2 V supply.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(VEE = VMIN to VMAX, VCC = GND, TA = TMIN to TMAX, Loop Damping
Factor = 5, unless otherwise noted)
AD800/AD802–SPECIFICATIONS
Parameter1
Condition
AD800-45BQ
Min
Typ
Max
NOMINAL CENTER FREQUENCY
OPERATING TEMPERATURE
RANGE (TMIN to TMAX)
K Grade
B Grade
Min
AD800-52BR
Typ
Max
44.736
–40
AD802-155KR/BR
Min
Typ
Max
51.84
85
–40
155.52
85
0
–40
Units
MHz
70
85
°C
°C
TRACKING RANGE
43
45.5
49
53
155
156
Mbps
CAPTURE RANGE
43
45.5
49
53
155
156
Mbps
14
18
30
37
Degrees
Degrees
0.2
0.8
1
2.06
2.37
STATIC PHASE ERROR
ρ = 1, TA = +25°C,
VEE = –5.2 V
ρ=1
RECOVERED CLOCK SKEW
tRCS (Figure 1)
SETUP TIME
tSU (Figure 1)
0.2
2
3
10
11.5
0.6
1
TRANSITIONLESS DATA RUN
OUTPUT JITTER
JITTER TOLERANCE
JITTER TRANSFER
Damping Factor
Capacitor, CD
ζ = 1, Nominal
ζ = 5, Nominal
ζ = 10, Nominal
Peaking
ζ = 1, Nominal
ζ = 5, Nominal
ζ = 10, Nominal
Bandwidth
0.2
2
3
10
11.5
0.6
1
240
ρ=1
27–1 PRN Sequence
223–1 PRN Sequence
f = 10 Hz
f = 2.3 kHz
f = 30 kHz
f = 1 MHz
f = 30 Hz
f = 300 Hz
f = 2 kHz
f = 20 kHz
f = 6.5 kHz
f = 65 kHz
2
2.5
2.5
240
2
2.5
2.5
4.7
4.7
2,500
3.5
5.4
5.4
4.7
4.7
2,500
240
Bit Periods
9.7
9.7
Degrees rms
Degrees rms
Degrees rms
3,000
7.6
0.9
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
6.5
0.47
0.47
830
83
7.4
0.47
2.0
0.26
ns
ns
8.2
0.22
0.82
6.8
0.15
0.68
2.2
0.047
0.22
nF
µF
µF
TA = +25°C, VEE = –5.2 V
TA = +25°C, VEE = –5.2 V
TA = +25°C, VEE = –5.2 V
2
0.08
0.02
45
2
0.08
0.02
52
2
0.08
0.02
130
dB
dB
dB
kHz
ACQUISITION TIME
ρ = 1/2
TA = +25°C
VEE = –5.2 V
ζ=1
ζ=5
ζ = 10
1 × 104
3 × 105 8 × 105
8 × 105
1 × 104
3 × 105 8 × 105
8 × 105
1.5 × 104
Bit Periods
4 × 105 8 × 105 Bit Periods
1.4 × 106
Bit Periods
POWER SUPPLY
Voltage (VMIN to VMAX)
Current
TA = +25°C
–4.5
TA = +25°C, VEE = –5.2 V
–5.2
125
INPUT VOLTAGE LEVELS
Input Logic High, VIH
Input Logic Low, VIH
TA = +25°C
OUTPUT VOLTAGE LEVELS
Output Logic High, VOH
Output Logic Low, VOL
TA = +25°C
INPUT CURRENT LEVELS
Input Logic High, IIH
Input Logic Low, IIL
TA = +25°C
OUTPUT SLEW TIMES
Rise Time (tR)
Fall Time (tF)
TA = +25°C
20%–80%
80%–20%
SYMMETRY
Recovered Clock Output
ρ = 1/2, TA = +25°C
VEE = –5.2 V
–5.5
170
180
–4.5
–5.2
125
–5.5
170
180
–4.5
–5.2
140
–5.5
180
205
Volts
mA
mA
–1.084
–1.95
–0.72 –1.084
–1.594 –1.95
–0.72 –1.084
–1.594 –1.95
–0.72 Volts
–1.594 Volts
–1.084
–1.95
–0.72
–1.60
–0.72
–1.60
–0.72
–1.60
Volts
Volts
125
80
µA
µA
1.5
1.5
ns
ns
55
%
–1.084
–1.95
125
80
0.75
0.75
45
125
80
1.5
1.5
55
–1.084
–1.95
0.75
0.75
45
1.5
1.5
55
0.75
0.75
45
NOTES
1
Refer to Glossary for parameter definition.
Specifications subject to change without notice.
–2–
REV. B
AD800/AD802
ABSOLUTE MAXIMUM RATINGS*
THERMAL CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Input Voltage (Pin 16 or Pin 17 to VCC) . . . . VEE to +300 mV
Maximum Junction Temperature
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
ESD Rating
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
SOIC Package
Cerdip Package
θJC
θJA
22°C/W
25°C/W
75°C/W
90°C/W
Use of a heatsink may be required depending on operating
environment.
GLOSSARY
Maximum and Minimum Specifications
Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. Typical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
Nominal Center Frequency
DATAOUT 50%
(PIN 2)
This is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, CD, shorted.
CLKOUT 50%
(PIN 5)
Tracking Range
SETUP TIME
tSU
This is the range of input data rates over which the PLL will
remain in lock.
RECOVERED CLOCK
SKEW, tRCS
Capture Range
This is the range of input data rates over which the PLL can
acquire lock.
Figure 1. Recovered Clock Skew and Setup
(See Previous Page)
Static Phase Error
PIN DESCRIPTIONS
Number
Mnemonic
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DATAOUT
DATAOUT
VCC2
CLKOUT
CLKOUT
VEE
VEE
VCC1
AVEE
ASUBST
CF2
CF1
AVCC
VCC1
VEE
DATAIN
DATAIN
SUBST
FRAC
20
FRAC
Differential Retimed Data Output
Differential Retimed Data Output
Digital Ground
Differential Recovered Clock Output
Differential Recovered Clock Output
Digital VEE
Digital VEE
Digital Ground
Analog VEE
Analog Substrate
Loop Damping Capacitor Input
Loop Damping Capacitor Input
Analog Ground
Digital Ground
Digital VEE
Differential Data Input
Differential Data Input
Digital Substrate
Differential Frequency Acquisition
Indicator Output
Differential Frequency Acquisition
Indicator Output
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.
Data Transition Density, r
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).
Jitter Tolerance
Jitter tolerance is a measure of the PLL’s ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.
ORDERING GUIDE
Device
Center Frequency
Fractional Loop
Bandwidth
Description
Operating Temperature
Package Option
AD800-45BQ
AD800-52BR
AD802-155BR
AD802-155KR
44.736 MHz
51.84 MHz
155.52 MHz
155.52 MHz
0.1%
0.1%
0.08%
0.08%
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
Q-20
R-20
R-20
R-20
REV. B
20-Pin Cerdip
20-Pin Plastic SOIC
20-Pin Plastic SOIC
20-Pin Plastic SOIC
–3–
AD800/AD802
The PLL must provide a clock signal which tracks this phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation which tracks
the input jitter, some modulation signal must be generated at
the output of the phase detector (see Figure 21). The
modulation output from the phase detector can only be
produced by a phase error between the data input and the clock
input. Hence, the PLL can never perfectly track jittered data.
However, the magnitude of the phase error depends on the gain
around the loop. At low frequencies the integrator provides very
high gain, and thus very large jitter can be tracked with small
phase errors between input data and recovered clock. At
frequencies closer to the loop bandwidth, the gain of the
integrator is much smaller, and thus less input jitter can be
tolerated. The PLL data output will have a bit error rate less
than 1 3 10–10 when in lock and retiming input data that has the
specified jitter applied to it.
Symmetry
Symmetry is calculated as (100 3 on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Error Rate vs. Signal-to-Noise Ratio
The AD800 and AD802 were designed to operate with standard
ECL signal levels at the data input. Although not recommended, smaller input signals are tolerable. Figure 8, 14, and
20 show the bit error rate performance versus input signal-tonoise ratio for input signal amplitudes of full 900 mV ECL, and
decreased amplitudes of 80 mV and 20 mV. Wideband amplitude noise is summed with the data signals as shown in Figure
2. The full ECL and 80 mV signals give virtually indistinguishable results. The 20 mV signals also provide adequate performance when in lock, but signal acquisition may be impaired.
POWER
COMBINER
Jitter Transfer
∑
The PLL exhibits a low-pass filter response to jitter applied to
its input data.
DATA IN
0.47µF
DIFFERENTIAL
SIGNAL
SOURCE
Bandwidth
D.U.T.
AD800/AD802
0.47µF
This describes the frequency at which the PLL attenuates
sinusoidal input jitter by 3 dB.
50Ω
50Ω
∑
DATA IN
POWER
COMBINER
Peaking
This describes the maximum jitter gain of the PLL in dB.
75Ω
1.0µF
POWER
SPLITTER
Damping Factor, z
180Ω
–5.2V
GND
ζ describes how the PLL will track an input signal with a phase
step. A greater value of ζ corresponds to less overshoot in the
PLL response to a phase step. ζ is a standard constant in second
FILTER
100MHz – AD802-155
33MHz – AD800-52
NOISE
SOURCE
order feedback systems.
Acquisition Time
This is the transient time, measured in bit periods, required for
the PLL to lock on input data from its free-running state.
USING THE AD800 AND THE AD802 SERIES
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended. Output signal sensitivity to
power supply noise (PECL configuration, Figure 22) is less
using one ground plane than when using separate analog and
digital ground planes.
Power Supply Connections
Use of a 10 µF tantalum capacitor between VEE and ground is
recommended.
Use of 0.1 µF ceramic capacitors between IC power supply or
substrate pins and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to schematics, Figure 22 and Figure 26, for advised
connections.
Sensitivity of IC output signals (PECL configuration,
Figure 22) to high frequency power supply noise (at 2 3 the
nominal data rate) can be reduced through the connection of
signals AVCC and VCC1, and the addition of a bypass network.
The type of bypass network to consider depends on the noise
tolerance required. The more complex bypass network schemes
tolerate greater power supply noise levels. Refer to Figures 23
and 24 for bypassing schemes and power supply sensitivity
curves.
Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:
Block Diagram
Transmission Lines
Use of 50 Ω transmission lines are recommended for DATAIN,
CLKOUT, DATAOUT, and FRAC signals.
Terminations
Termination resistors should be used for DATAIN, CLKOUT,
DATAOUT, and FRAC signals. Metal, thick film, 1% tolerance
resistors are recommended. Termination resistors for the
DATAIN signals should be placed as close as possible to the
DATAIN pins.
Connections from VEE to lead resistors for DATAIN, DATAOUT, FRAC, and CLKOUT signals should be individual, not
daisy chained. This will avoid crosstalk on these signals.
Loop Damping Capacitor, C D
A ceramic capacitor may be used for the loop damping
capacitor.
Input Buffer
Use of an input buffer, such as a 10H116 Line Receiver IC, is
suggested for an application where the DATAIN signals do not
come directly from an ECL gate, or where noise immunity on
the DATAIN signals is an issue.
–4–
REV. B
Typical Characteristics–AD800/AD802
52
10
9
8
48
JITTER – Degrees rms
CENTER FREQUENCY – MHz
50
46
44
42
7
6
5
4
3
2
40
1
38
–40
–20
0
20
40
60
80
0
–40
100
–20
0
TEMPERATURE – °C
20
40
60
80
100
TEMPERATURE – °C
Figure 3. AD800-45 Center Frequency vs. Temperature
Figure 4. AD800-45 Jitter vs. Temperature
100
52
UNIT INTERVALS – p-p
DATA RATE – Mbps
50
48
46
44
42
AD800-45
10
DS-3 MASK
1
40
38
–40
0.1
–20
0
20
40
60
80
10
100
0
10
1
2
3
4
5
10
10
10
JITTER FREQUENCY – Hz
TEMPERATURE – °C
10
10
6
Figure 6. AD800-45 Jitter Tolerance
Figure 5. AD800-45 Capture and Tracking Range vs.
Temperature
1E-1
55
CD = 0.68µF
51
5E-2
3E-2
2E-2
49
1E-2
BIT ERROR RATE
DATA RATE – Mbps
53
47
45
43
41
20
80
1
S
1
erfc
2 2 N
2
1E-3
80
1E-4
1E-5
ECL
20
1E-7
39
1E-9
1E-11
37
35
0
0.05
0.10
0.15
0.20
0.25
10
0.30
INPUT JITTER – UI p-p
Figure 7. AD800-45 Acquisition Range vs. Input Jitter
REV. B
12
14
16
18
S/N – dB
20
22
24
Figure 8. AD800-45 Bit Error Rate vs. Input Jitter
–5–
58
10
56
9
8
54
JITTER – Degrees rms
CENTER FREQUENCY – MHz
AD800/AD802
52
50
48
46
7
6
5
4
3
44
2
42
1
40
–40
–20
0
20
40
60
80
0
–40
100
–20
0
20
40
60
80
100
TEMPERATURE – °C
TEMPERATURE – °C
Figure 9. AD800-52 Center Frequency vs. Temperature
Figure 10. AD800-52 Jitter vs. Temperature
100
58
56
UNIT INTERVALS – p-p
DATA RATE – Mbps
54
52
50
48
46
AD800-52
10
OC-1 MASK
1
44
42
40
–40
0.1
–20
0
20
40
60
80
100
10
0
10
1
2
Figure 11. AD800-52 Capture and Tracking Range vs.
Temperature
10
4
10
5
Figure 12. AD800-52 Jitter Tolerance
60
1E-1
CD = 0.68µF
58
5E-2
3E-2
2E-2
56
54
BIT ERROR RATE
DATA RATE – Mbps
3
10
10
JITTER FREQUENCY – Hz
TEMPERATURE – °C
52
50
48
46
44
80
20
1E-2
1
S
1
erfc
2 2 N
2
1E-3
1E-4
80
1E-5
1E-6
ECL
20
1E-8
1E-10
42
40
0
0.05
0.10
0.15
0.20
0.25
0.30
10
INPUT JITTER – UI p-p
Figure 13. AD800-52 Acquisition Range vs. Input Jitter
12
14
16
18
S/N – dB
20
22
24
Figure 14. AD800-52 Bit Error Rate vs. Input Jitter
–6–
REV. B
AD800/AD802
180
10
9
8
160
JITTER – Degrees rms
CENTER FREQUENCY – MHz
170
150
140
130
7
6
5
4
3
120
2
110
1
100
–40
–20
0
20
40
60
80
0
–40
100
–20
0
TEMPERATURE – °C
20
40
60
80
100
TEMPERATURE – °C
Figure 15. AD802-155 Center Frequency vs. Temperature
Figure 16. AD802-155 Output Jitter vs. Temperature
100
200
180
AD802-155
10
UI – Pk-Pk
DATA RATE – Mbps
190
170
160
1
150
140
130
–40
CCITT G.958 STM1 TYPE A MASK
0.1
–20
0
20
40
60
80
100
10
2
10
3
4
Figure 17. AD802-155 Capture Range, Tracking Range vs.
Temperature
6
10
7
10
8
Figure 18. AD802-155 Jitter Tolerance
100
1E-1
5E-2
3E-2
2E-2
10
BIT ERROR RATE
1
1E-2
ECL
1
S
1
erfc
2 2 N
2
1E-3
1E-4
1E-5
1E-6
CCITT G.958 STM1 TYPE A MASK
0.1
80mV
20mV
AD802 – 155
INPUT JITTER – UI
5
10
10
10
JITTER FREQUENCY – Hz
TEMPERATURE – °C
80mV
&
ECL
20mV
1E-8
1E-10
1E-12
0
1
100
10
JITTER FREQUENCY – Hz
1000
10
Figure 19. AD802-155 Minimum Acquisition Range vs.
Jitter Frequency, TMIN to TMAX VMIN to VMAX
REV. B
12
14
16
18
S/N – dB
20
22
24
Figure 20. AD802-155 Bit Error Rate vs. Input Jitter
–7–
AD800/AD802
THEORY OF OPERATION
The AD800 and AD802 are phase-locked loop circuits for recovery of clock from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition, refer to
Figure 21 for a block diagram. Note the frequency detector is always in the circuit. When the PLL is locked, the frequency error
is zero and the frequency detector has no further effect. Since
the frequency detector is always in circuit, no control functions
are needed to initiate acquisition or change mode after acquisition. The frequency detector also supplies a frequency acquisition (FRAC) output to indicate when the loop is acquiring lock.
During the frequency acquisition process the FRAC output is a
series of pulses of width equal to the period of the VCO. These
pulses occur on the cycle slips between the data frequency and
the VCO frequency. With a maximum density (1010 . . .) data
pattern, every cycle slip will produce a pulse at FRAC. However, with random data, not every cycle slip produces a pulse.
The density of pulses at FRAC increases with the density of
data transitions. The probability that a cycle slip will produce a
pulse increases as the frequency error approaches zero. After the
frequency error has been reduced to zero, the FRAC output will
have no further pulses. At this point the PLL begins the process
of phase acquisition, with a settling time of roughly 2000 bit periods. Valid retimed data can be guaranteed by waiting 2000 bit
periods after the last FRAC pulse has occurred.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. The jitter created by a 27–1
pseudo-random code is 1/2 degree, and this is small compared
to random jitter.
The damping ratio of the phase-locked loop is user programmable with a single external capacitor. At 155 MHz a damping
ratio of 10 is obtained with a 0.22 µF capacitor. More generally,
the damping ratio scales as 1.7 × f DATA × CD . At 155 MHz a
damping ratio of 1 is obtained with a 2.2 nF capacitor. A lower
damping ratio allows a faster frequency acquisition; generally
the acquisition time scales directly with the capacitor value.
However, at damping ratios approaching one, the acquisition
time no longer scales directly with the capacitor value. The
acquisition time has two components: frequency acquisition and
phase acquisition. The frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop
bandwidth of the PLL and is independent of the damping ratio.
Thus, the 0.08% fractional loop bandwidth sets a minimum
acquisition time of 15,000 bit periods. Note the acquisition time
for a damping factor of 1 is specified as 15,000 bit periods. This
comprises 13,000 bit periods for frequency acquisition and
2,000 periods for phase acquisition. Compare this to the
400,000 bit periods acquisition time specified for a damping
ratio of 5; this consists entirely of frequency acquisition, and the
2,000 bit periods of phase acquisition is negligible.
While lower damping ratio affords faster acquisition, it also
allows more peaking in the jitter transfer response (jitter
peaking). For example, with a damping ratio of 10 the jitter
peaking is 0.02 dB, but with a damping factor of 1, the peaking
is 2 dB.
DATA
INPUT
Ø DET
TS + 1
∑
1
S
VCO
f DET
The jitter bandwidth for the AD802-155 is 0.08% of the center
frequency. This figure is chosen so that sinusoidal input jitter at
130 kHz will be attenuated by 3 dB. The jitter bandwidths of
the AD800-45 and AD800-52 are 0.1% of the respective center
frequencies. The jitter bandwidth of the AD800 or the AD802 is
mask programmable from 0.01% to 1% of the center frequency.
A device with a very low loop bandwidth (0.01% of the center
frequency) could effectively filter (clean up) a jittery timing
reference. Consult the factory if your application requires a
special loop bandwidth.
RECOVERED
CLOCK OUTPUT
RETIMING
DEVICE
RETIMED
DATA OUTPUT
FRAC OUTPUT
Figure 21. AD800 and AD802 Block Diagram
–8–
REV. B
AD800/AD802
5.0V C5
0.1
5.0V
C13 0.1
R13
154
R1
100
R2
100
C3 0.1
J1
R10
154
R9
154
DATAOUT
R5 100
R6 100
R12
154
R7 100
C6 0.1
J3
CLKOUT
1
DATAOUT
2
DATAOUT
3
VCC2
R11
154
4
CLKOUT
DATAIN 17
CLKOUT
DATAIN 16
5
J4
CLKOUT
6
R8 100
C7 0.1
R4
100
R3
100
5.0V
C10
0.1
FRAC 19
VEE
VCC1
VEE
AV CC
VCC1
8
C8
0.1
9
AV EE
10
ASUBST
Z1
IN
5.0V
C2
10µF
BYPASS
NETWORK
FRAC
FRAC
R16 100
C15 0.1
SUBST 18
VEE
7
C17 0.1
FRAC 20
C9
0.1
5.0V
C4 0.1
5.0V
R18
100
C14 0.1
R17
100
R15 100
DATAOUT
J2
R14
154
R19
130
R20
130
15
R21
80.6
14
12
CF2
11
5.0V
5.0V
C11
C16
0.1
CD
16
2
15
3
14
4
13
Z2
10H116
5
C12
0.1
13
CF1
R22
80.6
1
R23
130
R24
130
12
6
11
7
10
8
9
C19
0.1
J6
DATAIN
DATAIN
C20
0.1
AD800/802
OUT
J5
R26
80.6
R25
80.6
C21 0.1
5.0V
Figure 22. Evaluation Board Schematic, Positive Supply
Table I. Evaluation Board, Positive Supply: Components List
Reference
Designator
Description
Quantity
R1–8, R15–18
R9–14
R19, 20, 23, 24
R21, 22, 25, 26
CD
C2
C3–C21
Z1
Z2
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
Resistor, 130 Ω, 1%
Resistor, 80.6 Ω, 1%
Capacitor, Loop Damping (See Specifications Page)
Capacitor, 10 µF, Tantalum
Capacitor, 0.1 µF, Ceramic Chip
AD800/AD802
10H116, ECL Line Receiver
12
6
4
4
1
1
17
1
1
3.0
(A)
IN
0.1µF
TO DEVICE
(B)
IN
0.1µF
BEAD WITH
ONE LOOP
IN
C2
10µF
(C)
IN
5.0V
(A)
2.5
BEADS WITH ONE LOOP
BEAD WITH
TWO LOOPS
0.1µF
BEAD WITH
TWO LOOPS
(D)
IN
TO
DEVICE
JITTER – ns p-p
(B)
BYPASS
NETWORK
(A, B, C,
OR D)
TO
DEVICE
TO
DEVICE
(C)
1.5
1.0
(D)
BEAD WITH
TWO LOOPS
0.5
0.1µF
TO
DEVICE
BYPASS NETWORK
COMPONENTS:
CAPACITOR ..........CERAMIC CHIP
FERRITE BEAD......1/4 IN. STACKPOLE CARBO 57-1392
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NOISE – V p-p @ 311MHz
Figure 23. Bypass Network Schemes
REV. B
2.0
Figure 24. AD802-155 Output Jitter vs. Supply Noise
(PECL Configuration)
–9–
AD800/AD802
NOISE IN
50Ω
10 TURNS
SENSE
0.47µF
0.47µF
5V
10µF
AD802-155
BYPASS
NETWORK
(A, B, C,
OR D)
IN
MICRO
METALS
T50-10
TO
DEVICE
PINS
8, 13,
14
PIN
3
PINS
6, 7, 9
10, 15,
18
Figure 25. Power Supply Noise Sensitivity Test Circuit, PECL Configuration
–5.2V
R2
100
R1
100
J1
R10
154
–5.2V
C3
0.1
R9
154
C12
0.1
R21
274
DATAOUT
DATAOUT
R5 100
J2
R6 100
–5.2V
J3
R12
154
R7 100
R11
154
J4
CLKOUT
R4
100
DATAOUT
FRAC 20
2
DATAOUT
FRAC 19
FRAC
FRAC
C8 0.1
C4
0.1
CLKOUT
1
R22
274
R8 100
R3
100
C5
0.1
3
VCC2
4
CLKOUT
DATAIN 17
5
CLKOUT
DATAIN 16
6
VEE
VEE 15
7
VEE
VCC1 14
8
VCC1
9
–5.2V
–5.2V
SUBST 18
AV EE
10 ASUBST
C2
10
C6
0.1
–5.2V
C9 0.1
R15
130
R16
130
16
2
15
3
14
Z2
4
13
10H116
–5.2V
C7
0.1
—5.2V
1
5
12
AVCC 13
6
11
CF1 12
7
10
8
9
CF2
R13
80.6
R14
80.6
C11
0.1
R20
130
R19
130
J5
DATAIN
CD
11
J6
DATAIN
Z1
AD800/802
–5.2V
R17
80.6
C10
0.1
R18
80.6
Figure 26. Evaluation Board Schematic, Negative Supply
Table II. Evaluation Board, Negative Supply: Components List
Reference
Designator
Description
Quantity
R1–8
R9–12
R13, 14, 17, 18
R15, 16, 19, 20
R21, 22
CD
C2
C3–C12
Z1
Z2
Resistor, 100 Ω, 1%
Resistor, 154 Ω, 1%
Resistor, 80.6 Ω, 1%
Resistor, 130 Ω, 1%
Resistor, 274 Ω, 1%
Capacitor, Loop Damping (See Specifications Page)
Capacitor, 10 µF, Tantalum
Capacitor, 0.1 µF, Ceramic Chip
AD800/AD802
10H116, ECL Line Receiver
8
4
4
4
2
1
1
10
1
1
–10–
REV. B
AD800/AD802
Figure 27. Negative Supply Configuration: Component
Side (Top Layer)
Figure 29. Positive Supply Configuration: Component
Side (Top Layer)
Figure 28. Negative Supply Configuration: Solder Side
Figure 30. Positive Supply Configuration: Solder Side
REV. B
–11–
AD800/AD802
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Small Outline IC Package (R-20)
20
C1725a–7.5–12/93
0.512 (13.00)
0.496 (12.60)
11
0.300 (7.60)
0.292 (7.40)
0.419 (10.65)
0.394 (10.00)
1
10
0.50 (1.27)
BSC
0.019 (0.48)
0.014 (0.36)
0.104 (2.64)
0.093 (2.36)
0.011 (0.28)
0.004 (0.10)
0.015 (0.38)
0.007 (0.18)
0.050 (1.27)
0.016 (0.40)
20-Pin Cerdip Package (Q-20)
0.005 (0.13) MIN
0.098 (2.49) MAX
20
11
1
10
0.310 (7.87)
0.220 (5.59)
PIN 1
1.060 (26.92) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.015 (0.38)
0.008 (0.20)
15 °
0°
SEATING
PLANE
PRINTED IN U.S.A.
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
–12–
REV. B