ATMEL ATXMEGA256D3 8/16-bit xmega d3 microcontroller Datasheet

Features
• High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller
• Non-volatile Program and Data Memories
•
•
•
•
•
– 64K - 256K Bytes of In-System Self-Programmable Flash
– 4K - 8K Bytes Boot Code Section with Independent Lock Bits
– 2K - 4K Bytes EEPROM
– 4K - 16K Bytes Internal SRAM
Peripheral Features
– Four-channel Event System
– Five 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
One Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on two Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Three USARTs
IrDA Extension on 1 USART
– Two Two-Wire Interfaces with dual address match(I2C and SMBus compatible)
– Two SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– One Sixteen-channel, 12-bit, 200ksps Analog to Digital Converter
– Two Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interface
PDI (Program and Debug Interface) for programming, test and debugging
I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
8/16-bit
XMEGA D3
Microcontroller
ATxmega256D3
ATxmega192D3
ATxmega128D3
ATxmega64D3
Typical Applications
•
•
•
•
•
Industrial control
Factory automation
Building control
Board control
White Goods
•
•
•
•
•
Climate control
ZigBee
Motor control
Networking
Optical
•
•
•
•
•
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
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XMEGA D3
1. Ordering Information
Ordering Code
Flash (B)
E2 (B)
SRAM (B)
Speed (MHz)
Power Supply
ATxmega256D3-AU
256K + 8K
4K
16K
32
1.6 - 3.6V
ATxmega192D3-AU
192K + 8K
2K
16K
32
1.6 - 3.6V
ATxmega128D3-AU
128K + 8K
2K
8K
32
1.6 - 3.6V
ATxmega64D3-AU
64K + 4K
2K
4K
32
1.6 - 3.6V
ATxmega256D3-MH
256K + 8K
4K
16K
32
1.6 - 3.6V
ATxmega192D3-MH
192K + 8K
2K
16K
32
1.6 - 3.6V
ATxmega128D3-MH
128K + 8K
2K
8K
32
1.6 - 3.6V
ATxmega64D3-MH
64K + 4K
2K
4K
32
1.6 - 3.6V
Notes:
1.
2.
3.
Package(1)(2)(3)
Temp
64A
-40° - 85°C
64M2
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see ”Packaging information” on page 86.
Package Type
64A
64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64M2
64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
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2. Pinout/ Block Diagram
Notes:
PF5
PF4
PF3
PF6
VCC
GND
55
54
53
52
51
50
49
DATA BU S
Port A
ADC A
OSC/CLK
Control
BOD
VREF
POR
TEMP
RTC
OCD
AC A0
Power
Control
AC A1
FLASH
RAM
Reset
Control
CPU
E2PROM
Port B
Interrupt Controller
Watchdog
Event System ctrl
DATA BUS
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PF2
PF1
PF0
VCC
GND
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
GND
PD7
31
32
Port F
28
29
30
Port E
T/C0
USART0
TWI
T/C0
SPI
T/C0
USART0
Port D
19
20
21
22
23
24
25
26
27
Port C
SPI
TWI
USART0
T/C0:1
EVENT ROUTING NETWORK
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
PD1
PD2
PD3
PD4
PD5
PD6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Port R
17
18
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
48
47
1
PC1
PC2
PA3
62
61
60
59
58
57
56
64
63
INDEX CORNER
PA1
PA0
AVCC
GND
PR1
PR0
RESET/PDI
PDI
PF7
Block diagram and pinout
PA2
Figure 2-1.
1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 46.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good
mechanical stability.
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XMEGA D3
3. Overview
The Atmel® AVR® XMEGA D3 is a family of low power, high performance and peripheral rich
CMOS 8/16-bit microcontrollers based on the AVR® enhanced RISC architecture. By execug
powerful instructions in a single clock cycle, the XMEGA D3 achieves throughputs approaching
1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA D3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time
Counter (RTC), five flexible 16-bit Timer/Counters with compare modes and PWM, three
USARTs, two Two-Wire Interface (TWIs), two Serial Peripheral Interfaces (SPIs), one 16-channel 12-bit ADC with optional differential input with programmable gain, two analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available.
The XMEGA D3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Event System, Interrupt Controller and all peripherals
to continue functioning. The Power-down mode saves the SRAM and register contents but stops
the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset.
In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the
Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows
very fast start-up from external crystal combined with low power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further
reduce power consumption, the peripheral clock for each individual peripheral can optionally be
stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI. A Bootloader running in
the device can use any interface to download the application program to the Flash memory. The
Bootloader software in the Boot Flash section will continue to run while the Application Flash
section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC
CPU with In-System Self-Programmable Flash, the Atmel XMEGA D3 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded
applications.
The XMEGA D3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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3.1
Block Diagram
Figure 3-1.
XMEGA D3 Block Diagram
PR[0..1]
XTAL1
PORT R (2)
XTAL2
Oscillator
Circuits/
Clock
Generation
Watchdog
Oscillator
Real Time
Counter
Watchdog
Timer
DATA BUS
PA[0..7]
PORT A (8)
Event System
Controller
VCC
Power
Supervision
POR/BOD &
RESET
Oscillator
Control
GND
SRAM
Sleep
Controller
ACA
ADCA
BUS
Controller
AREFA
Prog/Debug
Controller
RESET/
PDI_CLK
PDI
PDI_DATA
VCC/10
Int. Refs.
Tempref
OCD
AREFB
CPU
Interrupt
Controller
PORT B (8)
NVM Controller
USARTF0
TCF0
Flash
EEPROM
PORT F (8)
PB[0..7]
PF[0..7]
IRCOM
DATA BUS
PORT D (8)
TWIE
USARTE0:1
TCE0:1
SPID
USARTD0:1
TCD0:1
SPIC
PORT C (8)
TWIC
TCC0:1
USARTC0:1
EVENT ROUTING NETWORK
To Clock
Generator
PORT E (8)
TOSC1
TOSC2
PC[0..7]
PD[0..7]
PE[0..7]
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XMEGA D3
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1
Recommended reading
• Atmel® AVR® XMEGATM D Manual
• XMEGA Application Notes
This device data sheet only contains part specific information and a short description of each
peripheral and module. The XMEGA D Manual describes the modules and peripherals in depth.
The XMEGA application notes contain example code and show applied use of the modules and
peripherals.
The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
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6. AVR CPU
6.1
Features
• 8/16-bit high performance AVR RISC Architecture
•
•
•
•
•
•
•
6.2
– 138 instructions
– Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
Overview
The Atmel® AVR® XMEGATM D3 uses the 8/16-bit AVR CPU. The main function of the AVR CPU
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations and control peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 7 shows the CPU block diagram.
Figure 6-1.
CPU block diagram
DATA BUS
Flash
Program
Memory
Program
Counter
OCD
Instruction
Register
STATUS/
CONTROL
Instruction
Decode
32 x 8 General
Purpose
Registers
ALU
Multiplier/
DES
DATA BUS
Peripheral
Module 1
Peripheral
Module 2
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
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XMEGA D3
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3
Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4
ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5
Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
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XMEGA D3
7. Memories
7.1
Features
• Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
16 bit-accessible General Purpose Register for global variables or flags
• Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC and temperature sensor calibration data
• User Signature Row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA D3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configurations are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.
7.3
In-System Programmable Flash Program Memory
The XMEGA D3 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each
Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-
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XMEGA D3
gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.
Figure 7-1.
Flash Program Memory (Hexadecimal address)
Word Address
0
Application Section
(256K/192K/128K/64K)
...
1EFFF
/
16FFF
/
EFFF
/
77FF
1F000
/
17000
/
F000
/
7800
1FFFF
/
17FFF
/
FFFF
/
7FFF
20000
/
18000
/
10000
/
8000
20FFF
/
18FFF
/
10FFF
/
87FF
Application Table Section
(8K/8K/8K/4K)
Boot Section
(8K/8K/8K/4K)
The Application Table Section and Boot Section can also be used for general application
software.
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7.4
Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2.
Data Memory Map (Hexadecimal address)
Byte Address
0
FFF
1000
17FF
ATxmega192D3
I/O Registers
(4KB)
EEPROM
(2K)
Byte Address
0
FFF
1000
17FF
RESERVED
2000
5FFF
Internal SRAM
(16K)
ATxmega128D3
I/O Registers
(4KB)
EEPROM
(2K)
Byte Address
0
FFF
1000
17FF
RESERVED
2000
3FFF
Internal SRAM
(8K)
ATxmega64D3
I/O Registers
(4KB)
EEPROM
(2K)
RESERVED
2000
2FFF
Byte Address
0
FFF
Internal SRAM
(4K)
ATxmega256D3
I/O Registers
(4KB)
1000
EEPROM
(4K)
1FFF
2000
5FFF
Internal SRAM
(16K)
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7.4.1
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA D3 is shown in the ”Peripheral Module Address Map” on page 51.
7.4.2
SRAM Data Memory
The XMEGA D3 devices have internal SRAM memory for data storage.
7.4.3
EEPROM Data Memory
The XMEGA D3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
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7.5
Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA D3 devices is shown in Table 7-1 on page 13. The serial number consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both application software and external programming.
Table 7-1.
Device ID bytes for XMEGA D3 devices.
Device
7.6
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega64D3
4A
96
1E
ATxmega128D3
48
97
1E
ATxmega192D3
49
97
1E
ATxmega256D3
44
98
1E
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or identification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase session and on-chip debug sessions.
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7.7
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2.
Devices
Flash
Page Size
Number of words and Pages in the Flash.
FWORD
FPAGE
Application
Boot
Size (Bytes)
(words)
Size
No of Pages
Size
No of Pages
ATxmega64D3
64K + 4K
128
Z[7:1]
Z[16:8]
64K
256
4K
16
ATxmega128D3
128K + 8K
256
Z[8:1]
Z[17:9]
128K
256
8K
16
ATxmega192D3
192K + 8K
256
Z[8:1]
Z[18:9]
192K
384
8K
16
ATxmega256D3
256K + 8K
256
Z[8:1]
Z[18:9]
256K
512
8K
16
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA D3 devices.
EEEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n] is used for addressing. The most significant bits in the address (E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3.
Devices
Number of bytes and Pages in the EEPROM.
EEPROM
Page Size
Size (Bytes)
(Bytes)
E2BYTE
E2PAGE
No of Pages
ATxmega64D3
2K
ATxmega128D3
2K
32
ADDR[4:0]
ADDR[10:5]
64
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega192D3
ATxmega256D3
2K
32
ADDR[4:0]
ADDR[10:5]
64
4K
32
ADDR[4:0]
ADDR[11:5]
128
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8. Event System
8.1
Features
•
•
•
•
•
•
•
•
8.2
Inter-peripheral communication and signalling with minimum latency
CPU independent operation
4 Event Channels allows for up to 4 signals to be routed at the same time
Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADC)
– Analog Comparators (AC)
– Ports (PORTx)
– System Clock (ClkSYS)
– Software (CPU)
Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADC)
– Ports (PORTx)
– IR Communication Module (IRCOM)
The same event can be used by multiple peripherals for synchronized timing
Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
Functions in Active and Idle mode
Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts or CPU resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 8-1 on page 16 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
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XMEGA D3
Figure 8-1.
Event system block diagram.
ClkSYS
CPU
PORTx
RTC
Event Routing
Network
ACx
ADCx
IRCOM
T/Cxn
The Event Routing Network can directly connect together ADCs, Analog Comparators (AC),
I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always routed into the Event Routing Network. This consist of
four multiplexers where each can be configured in software to select which event to be routed
into that event channel. All four event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
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9. System Clock and Clock options
9.1
Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
•
•
•
•
•
•
9.2
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32.768 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32.768 kHz Crystal Oscillator
– External clock
PLL with internal and external clock options with 2 to 31x multiplication
Clock Prescalers with 2 to 2048x division
Fast peripheral clock running at 2 and 4 times the CPU clock speed
Automatic Run-Time Calibration of internal oscillators
Crystal Oscillator failure detection
Overview
XMEGA D3 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 9-1 on page 18 shows the principal clock system in XMEGA D3.
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Figure 9-1.
Clock system overview
clkULP
WDT/BOD
32 kHz ULP
Internal Oscillator
clkRTC
RTC
32.768 kHz
Calibrated Internal
Oscillator
PERIPHERALS
ADC
2 MHz
Run-Time Calibrated
Internal Oscillator
32 MHz
Run-time Calibrated
Internal Oscillator
CLOCK CONTROL
clkPER
UNIT
with PLL and
Prescaler
PORTS
...
INTERRUPT
32.768 KHz
Crystal Oscillator
EVSYS
RAM
0.4 - 16 MHz
Crystal Oscillator
CPU
clkCPU NVM MEMORY
External
Clock Input
FLASH
EEPROM
Each clock source is briefly described in the following sub-sections.
9.3
9.3.1
Clock Options
32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
9.3.2
32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during production to provide a default frequency which is close to its nominal
frequency.
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9.3.3
32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
9.3.4
0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
9.3.5
2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
9.3.6
32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
9.3.7
External Clock input
The external clock input gives the possibility to connect a clock from an external source.
9.3.8
PLL with Multiplication factor 2 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 2 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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10. Power Management and Sleep Modes
10.1
Features
• 5 sleep modes
– Idle
– Power-down
– Power-save
– Standby
– Extended standby
• Power Reduction registers to disable clocks to unused peripherals
10.2
Overview
The XMEGA D3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the
CPU is executing application code. The application code decides when and what sleep mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
10.3
Sleep Modes
10.3.1
Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller and Event System are kept running. Interrupt requests from all enabled interrupts will wake the device.
10.3.2
Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
10.3.3
Power-save Mode
Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will
keep running during sleep and the device can also wake up from RTC interrupts.
10.3.4
Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
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10.3.5
Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
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11. System Control and Reset
11.1
Features
• Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– PDI reset
– Software reset
• Asynchronous reset
– No running clock in the device is required for reset
• Reset status register
11.2
Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector
address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, so no running clock is required to reset the device.
After the device is reset, the reset source can be determined by the application by reading the
Reset Status Register.
11.3
11.3.1
Reset Sources
Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
11.3.2
External Reset
The MCU is reset when a low level is present on the RESET pin.
11.3.3
Watchdog Reset
The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.
The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For
more details see ”WDT - Watchdog Timer” on page 23.
11.3.4
Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
11.3.5
PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
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11.3.6
Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
12. WDT - Watchdog Timer
12.1
Features
• 11 selectable timeout periods, from 8 ms to 8s.
• Two operation modes
– Standard mode
– Window mode
• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
• Configuration lock to prevent unwanted changes
12.2
Overview
The XMEGA D3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable the WDT.
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13. PMIC - Programmable Multi-level Interrupt Controller
13.1
Features
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
13.2
Overview
XMEGA D3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
13.3
Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA D3 devices are
shown in Table 13-1. Offset addresses for each interrupt available in the peripheral are
described for each peripheral in the XMEGA A manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word
address.
Table 13-1.
Reset and Interrupt Vectors
Program Address
(Base Address)
Source
0x000
RESET
0x002
OSCF_INT_vect
Crystal Oscillator Failure Interrupt vector (NMI)
0x004
PORTC_INT_base
Port C Interrupt base
0x008
PORTR_INT_base
Port R Interrupt base
0x014
RTC_INT_base
Real Time Counter Interrupt base
0x018
TWIC_INT_base
Two-Wire Interface on Port C Interrupt base
0x01C
TCC0_INT_base
Timer/Counter 0 on port C Interrupt base
0x028
TCC1_INT_base
Timer/Counter 1 on port C Interrupt base
0x030
SPIC_INT_vect
SPI on port C Interrupt vector
0x032
USARTC0_INT_base
USART 0 on port C Interrupt base
0x040
NVM_INT_base
Non-Volatile Memory Interrupt base
0x044
PORTB_INT_base
Port B Interrupt base
0x056
PORTE_INT_base
Port E INT base
Interrupt Description
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Table 13-1.
Reset and Interrupt Vectors (Continued)
Program Address
(Base Address)
Source
Interrupt Description
0x05A
TWIE_INT_base
Two-Wire Interface on Port E Interrupt base
0x05E
TCE0_INT_base
Timer/Counter 0 on port E Interrupt base
0x074
USARTE0_INT_base
USART 0 on port E Interrupt base
0x080
PORTD_INT_base
Port D Interrupt base
0x084
PORTA_INT_base
Port A Interrupt base
0x088
ACA_INT_base
Analog Comparator on Port A Interrupt base
0x08E
ADCA_INT_base
Analog to Digital Converter on Port A Interrupt base
0x09A
TCD0_INT_base
Timer/Counter 0 on port D Interrupt base
0x0AE
SPID_INT_vector
SPI D Interrupt vector
0x0B0
USARTD0_INT_base
USART 0 on port D Interrupt base
0x0D0
PORTF_INT_base
Port F Interrupt base
0x0D8
TCF0_INT_base
Timer/Counter 0 on port F Interrupt base
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14. I/O Ports
14.1
Features
• Selectable input and output configuration for each pin individually
• Flexible pin configuration through dedicated Pin Configuration Register
• Synchronous and/or asynchronous input sensing with port interrupts and events
•
•
•
•
•
•
•
•
•
•
14.2
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
Asynchronous wake-up from all input sensing configurations
Two port interrupts with flexible pin masking
Highly configurable output driver and pull settings:
–
Totem-pole
–
Pull-up/-down
–
Wired-AND
–
Wired-OR
–
Bus-keeper
–
Inverted I/O
Optional Slew rate control
Configuration of multiple pins in a single operation
Read-Modify-Write (RMW) support
Toggle/clear/set registers for Output and Direction registers
Clock output on port pin
Event Channel 0 output on port pin 7
Mapping of port registers (virtual ports) into bit accessible I/O memory space
Overview
The XMEGA D3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asynchronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
14.3
I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate
functions.
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14.3.1
Push-pull
Figure 14-1. I/O configuration - Totem-pole
DIRn
OUTn
Pn
INn
14.3.2
Pull-down
Figure 14-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn
OUTn
Pn
INn
14.3.3
Pull-up
Figure 14-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn
Pn
INn
14.3.4
Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
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Figure 14-4. I/O configuration - Totem-pole with bus-keeper
DIRn
OUTn
Pn
INn
14.3.5
Others
Figure 14-5. Output configuration - Wired-OR with optional pull-down
OUTn
Pn
INn
Figure 14-6. I/O configuration - Wired-AND with optional pull-up
INn
Pn
OUTn
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14.4
Input sensing
•
•
•
•
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 14-7 on page 29.
Figure 14-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
D Q D Q
INVERTED I/O
R
EDGE
DETECT
Event
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
14.5
Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can
be individually selected as source for each of the interrupts. The interrupts are then triggered
according to the input sense configuration for each pin configured as source for the interrupt.
14.6
Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 46 shows which modules on peripherals that enable alternate functions on a pin, and
which alternate functions that is available on a pin.
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15. T/C - 16-bits Timer/Counter with PWM
15.1
Features
• Five 16-bit Timer/Counters
•
•
•
•
•
•
•
•
•
•
•
15.2
– Four Timer/Counters of type 0
– One Timer/Counters of type 1
Four Compare or Capture (CC) Channels in Timer/Counter 0
Two Compare or Capture (CC) Channels in Timer/Counter 1
Double Buffered Timer Period Setting
Double Buffered Compare or Capture Channels
Waveform Generation:
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
– Frequency Generation
Input Capture:
– Input Capture with Noise Cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
Event Counter with Direction Control
Timer Overflow and Timer Error Interrupts and Events
One Compare Match or Capture Interrupt and Event per CC Channel
Hi-Resolution Extension (Hi-Res)
Advanced Waveform Extension (AWEX)
Overview
XMEGA D3 has five Timer/Counters, four Timer/Counter 0 and one Timer/Counter 1. The difference between them is that Timer/Counter 0 has four Compare/Capture channels, while
Timer/Counter 1 has two Compare/Capture channels.
The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the
microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of
Timer and Compare registers are double buffered to ensure glitch free operation. Single slope
PWM, dual slope PWM and frequency generation waveforms can be generated using the Compare Channels.
Through the Event System, any input pin or event in the microcontroller can be used to trigger
input capture, hence no dedicated pins are required for this. The input capture has a noise canceller to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width
measurements.
A wide range of interrupt or event sources are available, including T/C Overflow, Compare
match and Capture for each Compare/Capture channel in the T/C.
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE and PORTF each
have one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0,
and TCF0, respectively.
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Figure 15-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Control Logic
Counter
Event
System
clkPER4
Buffer
Capture
Control
Waveform
Generation
DTI
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORT
Comparator
AWeX
Hi-Res
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by
2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on
page 33 for more details.
The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See ”AWEX - Advanced
Waveform Extension” on page 32 for more details.
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16. AWEX - Advanced Waveform Extension
16.1
Features
•
•
•
•
•
•
•
•
16.2
Output with complementary output from each Capture channel
Four Dead Time Insertion (DTI) Units, one for each Capture channel
8-bit DTI Resolution
Separate High and Low Side Dead-Time Setting
Double Buffered Dead-Time
Event Controlled Fault Protection
Single Channel Multiple Output Operation (for BLDC motor control)
Double Buffered Pattern Generation
Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in
Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for
example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.
Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any
AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that
enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG
output with dead time insertion between LS and HS switching. The DTI output will override the
normal port value according to the port override setting. Optionally the final output can be
inverted by using the invert I/O setting for the port pin.
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from Compare Channel A can be distributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is
bypassed.
The Fault Protection unit is connected to the Event System. This enables any event to trigger a
fault condition that will disable the AWEX output. Several event channels can be used to trigger
fault on several different conditions.
The AWEX is available for TCC0. The notation of this is AWEXC.
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17. Hi-Res - High Resolution Extension
17.1
Features
• Increases Waveform Generator resolution by 2-bits (4x)
• Supports Frequency, single- and dual-slope PWM operation
• Supports the AWEX when this is enabled and used for the same Timer/Counter
17.2
Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running
at four times the CPU clock speed will be as input to the Timer/Counter.
The High Resolution Extension can also be used when an AWEX is enabled and used with a
Timer/Counter.
XMEGA D3 devices have one Hi-Res Extension that can be enabled for each Timer/Counters
on PORTC. The notation of this is HIRESC.
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18. RTC - Real-Time Counter
18.1
Features
•
•
•
•
•
•
18.2
16-bit Timer
Flexible Tick resolution ranging from 1 Hz to 32.768 kHz
One Compare register
One Period register
Clear timer on Overflow or Compare Match
Overflow or Compare Match event and interrupt generation
Overview
The XMEGA D3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an
accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the
32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare
register. For details, see Figure 18-1.
A wide range of Resolution and Time-out periods can be configured using the RTC. With a maximum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1
second, the maximum time-out period is over 18 hours (65536 seconds).
Figure 18-1. Real-time Counter overview
Period
Overflow
32.768 kHz
=
10-bit
prescaler
1.024 kHz
Counter
=
Compare Match
Compare
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19. TWI - Two Wire Interface
19.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
19.2
Two Identical TWI peripherals
Simple yet Powerful and Flexible Communication Interface
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when in Sleep Mode
I2C and System Management Bus (SMBus) compatible
Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 individually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
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20. SPI - Serial Peripheral Interface
20.1
Features
•
•
•
•
•
•
•
•
•
20.2
Two Identical SPI peripherals
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer
between different devices. Devices can communicate using a master-slave scheme, and data is
transferred both to and from the devices simultaneously.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID,
respectively.
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21. USART
21.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
21.2
Three Identical USART peripherals
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High-resolution Arithmetic Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
Master SPI mode for SPI communication
IrDA support through the IRCOM module
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are
USARTC0, USARTD0 and USARTE0, respectively.
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XMEGA D3
22. IRCOM - IR Communication Module
22.1
Features
• Pulse modulation/demodulation for infrared communication
• Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps
• Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
• Built in filtering
• Can be connected to and used by one USART at the time
22.2
Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with
baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,
fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation disabled. There is one IRCOM available which can be connected to any USART to enable infrared
pulse coding/decoding for that USART.
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XMEGA D3
23. ADC - 12-bit Analog to Digital Converter
23.1
Features
•
•
•
•
•
•
•
•
•
•
•
23.2
One ADC with 12-bit resolution
200 ksps sample rate
Signed and Unsigned conversions
16 single ended inputs
8x4 differential inputs
3 internal inputs:
–
Integrated Temperature Sensor
–
VCC voltage divided by 10
–
Bandgap voltage
Software selectable gain of 1, 2, 4, 8, 16, 32 or 64
Software selectable resolution of 8- or 12-bit.
Internal or External Reference selection
Event triggered conversion for accurate timing
Interrupt/Event on compare result
Overview
XMEGA D3 devices have one Analog to Digital Converters (ADC), see Figure 23-1 on page 40.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is
capable of converting up to 200K samples per second. The input selection is flexible, and both
singleended and differential measurements can be done. For differential measurements an
optional gain stage is available to increase the dynamic range. In addition several internal signal
inputs are available. The ADC can provide both signed and unsigned results.
ADC measurements can either be started by application software or an incoming event from
another peripheral in the device. The latter ensure the ADC measurements can be started with
predictable timing, and without software intervention. The ADC has one channel, meaning there
is one input selection (MUX selection) and one result register available.
Both internal and external analog reference voltages can be used. A very accurate internal
1.00V reference is available.
An integrated temperature sensor is available and the output from this can be measured with the
ADC. A VCC/10 signal and the Bandgap voltage can also be measured by the ADC.
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8134I–AVR–12/10
XMEGA D3
Figure 23-1. ADC overview
Internal inputs
C hannel A M U X selection
Pin inputs
Pin inputs
C onfiguration
R eference selection
ADC
1-64 X
C hannel A
R egister
E vent
Trigger
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 0.5 µs for 12-bit to 3.7 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
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8134I–AVR–12/10
XMEGA D3
24. AC - Analog Comparator
24.1
Features
• Two Analog Comparators
• Selectable hysteresis
•
•
•
•
24.2
– No, Small or Large
Analog Comparator output available on pin
Flexible Input Selection
– All pins on the port
– Bandgap reference voltage.
– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
Interrupt and event generation on
– Rising edge
– Falling edge
– Toggle
Window function interrupt and event generation on
– Signal above window
– Signal inside window
– Signal below window
Overview
XMEGA D3 features two Analog Comparators (AC). An Analog Comparator compares two voltages, and the output indicates which input is largest. The Analog Comparator may be configured
to give interrupt requests and/or events upon several different combinations of input change.
Hysteresis can be adjusted in order to find the optimal operation for each application.
A wide range of input selection is available, both external pins and several internal signals can
be used.
The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They
have identical behavior but separate control registers.
Optionally, the state of the comparator is directly available on a pin.
PORTA and has one AC pair. Notations of this peripheral is ACA.
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XMEGA D3
Figure 24-1. Analog comparator overview
Pin inputs
Internal inputs
+
Pin 0 output
AC0
Pin inputs
-
Internal inputs
VCC scaled
Interrupt
sensitivity
control
Pin inputs
Interrupts
Events
Internal inputs
+
AC1
Pin inputs
-
Internal inputs
VCC scaled
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8134I–AVR–12/10
XMEGA D3
24.3
Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped
in a pair may be used to realize a window function. One pair of analog comparators is shown in
Figure 24-1 on page 42.
• Input selection from pin
– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator
– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator
• Internal signals available on positive analog comparator inputs
• Internal signals available on negative analog comparator inputs
– 64-level scaler of the VCC, available on negative analog comparator input
– Bandgap voltage reference
24.4
Window Function
The window function is realized by connecting the external inputs of the two analog comparators
in a pair as shown in Figure 24-2.
Figure 24-2. Analog comparator window function
+
AC0
Upper limit of window
Interrupt
sensitivity
control
Input signal
Interrupts
Events
+
AC1
Lower limit of window
-
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XMEGA D3
25. OCD - On-chip Debug
25.1
Features
• Complete Program Flow Control
– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
Debugging on C and high-level language source code level
Debugging on Assembler and disassembler level
1 dedicated program address or source level breakpoint for AVR Studio / debugger
4 Hardware Breakpoints
Unlimited Number of User Program Breakpoints
Unlimited Number of User Data Breakpoints, with break on:
– Data location read, write or both read and write
– Data location content equal or not equal to a value
– Data location content is greater or less than a value
– Data location content is within or outside a range
– Bits of a data location are equal or not equal to a value
• Non-Intrusive Operation
– No hardware or software resources in the device are used
• High Speed Operation
– No limitation on debug/programming clock frequency versus system clock frequency
•
•
•
•
•
•
25.2
Overview
The XMEGA D3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s
development tools - provides all the necessary functions to debug an application. It has support
for program and data breakpoints, and can debug an application from C and high level language
source code level, as well as assembler and disassembler level. It has full Non-Intrusive Operation and no hardware or software resources in the device are used. The ODC system is
accessed through an external debugging tool which connects to the PDI interface. Refer to ”PDI
- Program and Debug Interface” on page 45.
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8134I–AVR–12/10
XMEGA D3
26. PDI - Program and Debug Interface
26.1
Features
• PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
• Access to the OCD system
• Programming of Flash, EEPROM, Fuses and Lock Bits
26.2
Overview
The programming and debug facilities are accessed through the PDI interface. The PDI physical
interface uses one dedicated pin together with the Reset pin, and no general purpose pins are
used.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
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8134I–AVR–12/10
XMEGA D3
27. Pinout and Pin Functions
The pinout of XMEGA D3 is shown in ”” on page 2. In addition to general I/O functionality, each
pin may have several function. This will depend on which peripheral is enabled and connected to
the actual pin. Only one of the alternate pin functions can be used at time.
27.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
27.1.1
27.1.2
27.1.3
27.1.4
Operation/Power Supply
VCC
Digital supply voltage
AVCC
Analog supply voltage
GND
Ground
Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
Analog functions
ACn
Analog Comparator input pin n
AC0OUT
Analog Comparator 0 Output
ADCn
Analog to Digital Converter input pin n
AREF
Analog Reference input pin
Timer/Counter and AWEX functions
OCnx
Output Compare Channel x for Timer/Counter n
OCnx
Inverted Output Compare Channel x for Timer/Counter n
OCnxLS
Output Compare Channel x Low Side for Timer/Counter n
OCnxHS
Output Compare Channel x High Side for Timer/Counter n
46
8134I–AVR–12/10
XMEGA D3
27.1.5
27.1.6
27.1.7
Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
Serial Clock In for TWI when external driver interface is enabled
SCLOUT
Serial Clock Out for TWI when external driver interface is enabled
SDAIN
Serial Data In for TWI when external driver interface is enabled
SDAOUT
Serial Data Out for TWI when external driver interface is enabled
XCKn
Transfer Clock for USART n
RXDn
Receiver Data for USART n
TXDn
Transmitter Data for USART n
SS
Slave Select for SPI
MOSI
Master Out Slave In for SPI
MISO
Master In Slave Out for SPI
SCK
Serial Clock for SPI
Oscillators, Clock and Event
TOSCn
Timer Oscillator pin n
XTALn
Input/Output for inverting Oscillator pin n
CLKOUT
Peripheral Clock Output
EVOUT
Event Channel 0 Output
Debug/System functions
RESET
Reset pin
PDI_CLK
Program and Debug Interface Clock pin
PDI_DATA
Program and Debug Interface Data pin
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8134I–AVR–12/10
XMEGA D3
27.2
Alternate Pin Functions
The tables below show the main and alternate pin functions for all pins on each port. They also
show which peripheral that makes use of or enables the alternate pin function.
Table 27-1.
PORT A
PIN #
Port A - Alternate functions
INTERRUPT
ADCA POS
ADCA NEG
ADAA
GAINPOS
SYNC
ADC0
ADC0
ADCA
GAINNEG
ACA POS
ACA NEG
ADC0
AC0
AC0
ADC1
ADC1
AC1
AC1
ADC2
ADC2
AC2
GND
60
AVCC
61
PA0
62
PA1
63
SYNC
ADC1
PA2
64
SYNC/ASYNC
ADC2
PA3
1
SYNC
ADC3
ADC3
PA4
2
SYNC
ADC4
ADC4
ADC4
AC4
PA5
3
SYNC
ADC5
ADC5
ADC5
AC5
PA6
4
SYNC
ADC6
ADC6
ADC6
AC6
PA7
5
SYNC
ADC7
ADC7
ADC7
Table 27-2.
PORT B
ADC3
AC3
ACA OUT
REFA
AREFA
AC3
AC5
AC7
AC0 OUT
Port B - Alternate functions
PIN #
INTERRUPT
ADCA POS
REFB
PB0
6
SYNC
ADC8
AREFB
PB1
6
SYNC
ADC9
PB2
8
SYNC/ASYNC
ADC10
PB3
9
SYNC
ADC11
PB4
10
SYNC
ADC12
PB5
11
SYNC
ADC13
PB6
12
SYNC
ADC14
PB7
13
SYNC
ADC15
GND
14
VCC
15
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8134I–AVR–12/10
XMEGA D3
Table 27-3.
PORT C
Port C - Alternate functions
PIN #
INTERRUPT
TCC0
AWEXC
PC0
16
SYNC
OC0A
OC0ALS
PC1
17
SYNC
OC0B
OC0AHS
XCK0
PC2
18
SYNC/ASYNC
OC0C
OC0BLS
RXD0
PC3
19
SYNC
OC0D
OC0BHS
PC4
20
SYNC
OC0CLS
OC1A
SS
PC5
21
SYNC
OC0CHS
OC1B
MOSI
PC6
22
SYNC
OC0DLS
MISO
PC7
23
SYNC
OC0DHS
SCK
GND
24
VCC
25
Table 27-4.
PORT D
TCC1
TWIC
CLOCKOUT
EVENTOUT
CLKOUT
EVOUT
SCL
TXD0
Port D - Alternate functions
PIN #
INTERRUPT
TCD0
26
SYNC
OC0A
PD1
27
SYNC
OC0B
XCK0
PD2
28
SYNC/ASYNC
OC0C
RXD0
PD3
29
SYNC
OC0D
TXD0
PD4
30
SYNC
SS
PD5
31
SYNC
MOSI
PD6
32
SYNC
MISO
PD7
33
SYNC
GND
34
VCC
35
PORT E
SPIC
SDA
PD0
Table 27-5.
USARTC0
USARTD0
SPID
CLOCKOUT
EVENTOUT
SCK
CLKOUT
EVOUT
CLOCKOUT
EVENTOUT
Port E - Alternate functions
PIN #
INTERRUPT
TCE0
USARTE0
PE0
36
SYNC
OC0A
PE1
37
SYNC
OC0B
XCK0
PE2
38
SYNC/ASYNC
OC0C
RXD0
PE3
39
SYNC
OC0D
TXD0
PE4
40
SYNC
PE5
41
SYNC
PE6
42
SYNC
PE7
43
SYNC
GND
44
VCC
45
TOSC
TWIE
SDA
SCL
TOSC1
CLKOUT
EVOUT
TOSC1
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8134I–AVR–12/10
XMEGA D3
Table 27-6.
PORT F
Port F - Alternate functions
PIN #
INTERRUPT
TCF0
PF0
46
SYNC
OC0A
PF1
47
SYNC
OC0B
PF2
48
SYNC/ASYNC
OC0C
PF3
49
SYNC
OC0D
PF4
50
SYNC
PF5
51
SYNC
PF6
54
SYNC
PF7
55
SYNC
GND
52
VCC
53
Table 27-7.
PORT R
PIN #
INTERRUPT
Port R - Alternate functions
PDI
PDI
56
PDI_DATA
RESET
57
PDI_CLOCK
XTAL
PRO
58
SYNC
XTAL2
PR1
59
SYNC
XTAL1
50
8134I–AVR–12/10
XMEGA D3
28. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA D3. For
complete register description and summary for each peripheral module, refer to the XMEGA A
Manual.
Table 28-1.
Base Address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x0180
0x01C0
0x0200
0x0380
0x0400
0x0480
0x04A0
0x0600
0x0620
0x0640
0x0660
0x0680
0x06A0
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08C0
0x08F8
0x0900
0x09A0
0x09C0
0x0A00
0x0A80
0x0AA0
0x0AC0
0x0B00
Peripheral Module Address Map
Name
Description
GPIO
VPORT0
VPORT1
VPORT2
VPORT3
CPU
CLK
SLEEP
OSC
DFLLRC32M
DFLLRC2M
PR
RST
WDT
MCU
PMIC
PORTCFG
EVSYS
NVM
ADCA
ACA
RTC
TWIC
TWIE
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTR
TCC0
TCC1
AWEXC
HIRESC
USARTC0
SPIC
IRCOM
TCD0
USARTD0
SPID
TCE0
AWEXE
USARTE0
SPIE
TCF0
General Purpose IO Registers
Virtual Port 0
Virtual Port 1
Virtual Port 2
Virtual Port 2
CPU
Clock Control
Sleep Controller
Oscillator Control
DFLL for the 32 MHz Internal RC Oscillator
DFLL for the 2 MHz RC Oscillator
Power Reduction
Reset Controller
Watch-Dog Timer
MCU Control
Programmable MUltilevel Interrupt Controller
Port Configuration
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog Comparator pair on port A
Real Time Counter
Two Wire Interface on port C
Two Wire Interface on port E
Port A
Port B
Port C
Port D
Port E
Port F
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port D
USART 0 on port D
Serial Peripheral Interface on port D
Timer/Counter 0 on port E
Advanced Waveform Extensionon port E
USART 0 on port E
Serial Peripheral Interface on port E
Timer/Counter 0 on port F
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XMEGA D3
29. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
Add without Carry
Rd
←
Rd + Rr
Z,C,N,V,S,H
1
Rd, Rr
Add with Carry
Rd
←
Rd + Rr + C
Z,C,N,V,S,H
1
Rd, K
Add Immediate to Word
Rd
←
Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd
←
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
←
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
←
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
←
Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd
←
Rd + 1:Rd - K
Z,C,N,V,S
2
ADD
Rd, Rr
ADC
ADIW
AND
Rd, Rr
Logical AND
Rd
←
Rd • Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
←
Rd • K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
←
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
←
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
←
Rd ⊕ Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
←
$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
←
$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
←
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
←
Rd • ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
←
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
←
Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
←
Rd • Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
←
Rd ⊕ Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
←
$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0
←
Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0
←
Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0
←
Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0
←
Rd x Rr<<1 (UU)
Z,C
2
FMULS
Rd,Rr
Fractional Multiply Signed
R1:R0
←
Rd x Rr<<1 (SS)
Z,C
2
FMULSU
Rd,Rr
Fractional Multiply Signed with Unsigned
R1:R0
←
Rd x Rr<<1 (SU)
Z,C
2
RJMP
k
Relative Jump
PC
←
PC + k + 1
None
2
Branch Instructions
IJMP
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
None
2
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
2
JMP
k
Jump
PC
←
k
None
3
RCALL
k
Relative Call Subroutine
PC
←
PC + k + 1
None
2 / 3(1)
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
None
2 / 3(1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
3(1)
PC
←
k
None
3 / 4(1)
CALL
k
call Subroutine
52
8134I–AVR–12/10
XMEGA D3
Mnemonics
Operands
Description
Operation
Flags
#Clocks
RET
Subroutine Return
PC
←
STACK
None
4 / 5(1)
RETI
Interrupt Return
PC
←
STACK
I
4 / 5(1)
if (Rd = Rr) PC
←
PC + 2 or 3
None
1/2/3
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
SBRS
Rr, b
Skip if Bit in Register Set
SBIC
A, b
Skip if Bit in I/O Register Cleared
SBIS
A, b
Skip if Bit in I/O Register Set
BRBS
s, k
BRBC
BREQ
Rd - Rr
Z,C,N,V,S,H
1
Rd - Rr - C
Z,C,N,V,S,H
1
Rd - K
Z,C,N,V,S,H
1
if (Rr(b) = 0) PC
←
PC + 2 or 3
None
1/2/3
if (Rr(b) = 1) PC
←
PC + 2 or 3
None
1/2/3
if (I/O(A,b) = 0) PC
←
PC + 2 or 3
None
2/3/4
If (I/O(A,b) =1) PC
←
PC + 2 or 3
None
2/3/4
Branch if Status Flag Set
if (SREG(s) = 1) then PC
←
PC + k + 1
None
1/2
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC
←
PC + k + 1
None
1/2
k
Branch if Equal
if (Z = 1) then PC
←
PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC
←
PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC
←
PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC
←
PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC
←
PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC
←
PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC
←
PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC
←
PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC
←
PC + k + 1
None
1/2
BRLT
k
Branch if Less Than, Signed
if (N ⊕ V= 1) then PC
←
PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC
←
PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC
←
PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC
←
PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC
←
PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC
←
PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC
←
PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if (I = 1) then PC
←
PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if (I = 0) then PC
←
PC + k + 1
None
1/2
Data Transfer Instructions
MOV
Rd, Rr
Copy Register
MOVW
Rd, Rr
Copy Register Pair
LDI
Rd, K
Load Immediate
Rd
←
Rr
None
1
Rd+1:Rd
←
Rr+1:Rr
None
1
Rd
←
K
None
1
LDS
Rd, k
Load Direct from data space
Rd
←
(k)
None
2
LD
Rd, X
Load Indirect
Rd
←
(X)
None
1(1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
←
←
(X)
X+1
None
1(1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X ← X - 1,
Rd ← (X)
←
←
X-1
(X)
None
2(1)(2)
LD
Rd, Y
Load Indirect
Rd ← (Y)
←
(Y)
None
1(1)(2)
LD
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
←
←
(Y)
Y+1
None
1(1)(2)
(1)(2)
53
8134I–AVR–12/10
XMEGA D3
Mnemonics
Operands
Description
Flags
#Clocks
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
←
←
Y-1
(Y)
None
2(1)(2)
LDD
Rd, Y+q
Load Indirect with Displacement
Rd
←
(Y + q)
None
2(1)(2)
LD
Rd, Z
Load Indirect
Rd
←
(Z)
None
1(1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
←
←
(Z),
Z+1
None
1(1)(2)
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
←
←
Z - 1,
(Z)
None
2(1)(2)
LDD
Rd, Z+q
Load Indirect with Displacement
Rd
←
(Z + q)
None
2(1)(2)
STS
k, Rr
Store Direct to Data Space
(k)
←
Rd
None
2(1)
ST
X, Rr
Store Indirect
(X)
←
Rr
None
1(1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
←
←
Rr,
X+1
None
1(1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
←
←
X - 1,
Rr
None
2(1)
ST
Y, Rr
Store Indirect
(Y)
←
Rr
None
1(1)
ST
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
←
←
Rr,
Y+1
None
1(1)
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
←
←
Y - 1,
Rr
None
2(1)
STD
Y+q, Rr
Store Indirect with Displacement
(Y + q)
←
Rr
None
2(1)
ST
Z, Rr
Store Indirect
(Z)
←
Rr
None
1(1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
←
←
Rr
Z+1
None
1(1)
ST
-Z, Rr
Store Indirect and Pre-Decrement
Z
←
Z-1
None
2(1)
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)
←
Rr
None
2(1)
Load Program Memory
R0
←
(Z)
None
3
LPM
Operation
LPM
Rd, Z
Load Program Memory
Rd
←
(Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
←
←
(Z),
Z+1
None
3
Extended Load Program Memory
R0
←
(RAMPZ:Z)
None
3
ELPM
ELPM
Rd, Z
Extended Load Program Memory
Rd
←
(RAMPZ:Z)
None
3
ELPM
Rd, Z+
Extended Load Program Memory and PostIncrement
Rd
Z
←
←
(RAMPZ:Z),
Z+1
None
3
Store Program Memory
(RAMPZ:Z)
←
R1:R0
None
-
(RAMPZ:Z)
Z
←
←
R1:R0,
Z+2
None
-
Rd
←
I/O(A)
None
1
I/O(A)
←
Rr
None
1
STACK
←
Rr
None
1(1)
Rd
←
STACK
None
2(1)
Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H
1
Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Z,C,N,V
1
SPM
SPM
Z+
Store Program Memory and Post-Increment
by 2
IN
Rd, A
In From I/O Location
OUT
A, Rr
Out To I/O Location
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
Bit and Bit-test Instructions
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
54
8134I–AVR–12/10
XMEGA D3
Mnemonics
Operands
Description
Operation
ROL
Rd
Rotate Left Through Carry
ROR
Rd
ASR
Flags
#Clocks
Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
Rotate Right Through Carry
Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
Z,C,N,V
1
Rd
Arithmetic Shift Right
Rd(n)
←
Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
↔
Rd(7..4)
None
1
BSET
s
Flag Set
SREG(s)
←
1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
←
0
SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)
←
1
None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b)
←
0
None
1
BST
Rr, b
Bit Store from Register to T
T
←
Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)
←
T
None
1
SEC
Set Carry
C
←
1
C
1
CLC
Clear Carry
C
←
0
C
1
SEN
Set Negative Flag
N
←
1
N
1
CLN
Clear Negative Flag
N
←
0
N
1
SEZ
Set Zero Flag
Z
←
1
Z
1
CLZ
Clear Zero Flag
Z
←
0
Z
1
SEI
Global Interrupt Enable
I
←
1
I
1
CLI
Global Interrupt Disable
I
←
0
I
1
SES
Set Signed Test Flag
S
←
1
S
1
CLS
Clear Signed Test Flag
S
←
0
S
1
SEV
Set Two’s Complement Overflow
V
←
1
V
1
CLV
Clear Two’s Complement Overflow
V
←
0
V
1
SET
Set T in SREG
T
←
1
T
1
CLT
Clear T in SREG
T
←
0
T
1
SEH
Set Half Carry Flag in SREG
H
←
1
H
1
CLH
Clear Half Carry Flag in SREG
H
←
0
H
1
MCU Control Instructions
BREAK
Break
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
Notes:
(See specific descr. for BREAK)
None
1
None
1
(see specific descr. for Sleep)
None
1
(see specific descr. for WDR)
None
1
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
55
8134I–AVR–12/10
XMEGA D3
30. Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other
conditions are given.
30.1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin with respect to Ground. -0.5V to VCC+0.5V
Maximum Operating Voltage ............................................ 3.6V
DC Current per I/O Pin ............................................... 20.0 mA
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Current VCC and GND Pins................................ 200.0 mA
30.2
DC Characteristics
Table 30-1.
Symbol
Current Consumption
Parameter
Condition
Min
Typ
Max
VCC = 1.8V
25
VCC = 3.0V
71
VCC = 1.8V
317
VCC = 3.0V
697
VCC = 1.8V
613
800
VCC = 3.0V
1340
1800
VCC = 3.0V
15.7
18
VCC = 1.8V
3.6
VCC = 3.0V
6.9
VCC = 1.8V
112
VCC = 3.0V
215
VCC = 1.8V
224
350
VCC = 3.0V
430
650
VCC = 3.0V
6.9
8
All Functions Disabled, T = 25°C
VCC = 3.0V
0.1
3
All Functions Disabled, T = 85°C
VCC = 3.0V
1.75
5
VCC = 1.8V
1
6
VCC = 3.0V
1
6
VCC = 3.0V
2.7
10
32 kHz, Ext. Clk
1 MHz, Ext. Clk
Active
2 MHz, Ext. Clk
32 MHz, Ext. Clk
Power Supply Current(1)
32 kHz, Ext. Clk
ICC
1 MHz, Ext. Clk
Idle
2 MHz, Ext. Clk
32 MHz, Ext. Clk
Power-down mode
ULP, WDT, Sampled BOD, T = 25°C
ULP, WDT, Sampled BOD, T=85°C
Units
µA
mA
µA
mA
µA
56
8134I–AVR–12/10
XMEGA D3
Table 30-1.
Symbol
Current Consumption
Parameter
Condition
Power-save mode
RTC 1 kHz from Low Power 32 kHz
TOSC, T = 25°C
ICC
Reset Current
Consumption
Min
Typ
Max
VCC = 1.8V
0.5
4
VCC = 3.0V
0.7
4
RTC from Low Power 32 kHz TOSC
VCC = 3.0V
1.16
without Reset pull-up resistor current
VCC = 3.0V
1300
Units
µA
Module current consumption(2)
RC32M
RC32M w/DFLL
460
Internal 32.768 kHz oscillator as DFLL source
RC2M
RC2M w/DFLL
101
Internal 32.768 kHz oscillator as DFLL source
RC32K
PLL
ICC
134
27
Multiplication factor = 10x
202
Watchdog normal mode
1
BOD Continuous mode
128
BOD Sampled mode
1
Internal 1.00 V ref
80
Temperature reference
74
RTC with int. 32 kHz RC as
source
No prescaling
27
RTC with ULP as source
No prescaling
1
AC
Notes:
594
µA
103
USART
Rx and Tx enabled, 9600 BAUD
5.4
Timer/Counter
Prescaler DIV1
20
Flash/EEPROM
Programming
Vcc = 2V
25
Vcc = 3V
33
mA
1. All Power Reduction Registers set.
2. All parameters measured as the difference in current consumption between module enabled and disabled.
All data at VCC = 3.0V, ClkSYS = 1 MHz External clock with no prescaling.
57
8134I–AVR–12/10
XMEGA D3
30.3
Operating Voltage and Frequency
Table 30-2.
Symbol
ClkCPU
Operating voltage and frequency
Parameter
CPU clock frequency
Condition
Min
Typ
Max
VCC = 1.6V
0
12
VCC = 1.8V
0
12
VCC = 2.7V
0
32
VCC = 3.6V
0
32
Units
MHz
The maximum CPU clock frequency of the XMEGA D3 devices is depending on VCC. As shown
in Figure 30-1 on page 58 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V.
Figure 30-1. Maximum Frequency vs. Vcc
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
58
8134I–AVR–12/10
XMEGA D3
30.4
Flash and EEPROM Memory Characteristics
Table 30-3.
Symbol
Endurance and Data Retention
Parameter
Condition
Min
25°C
10K
85°C
10K
25°C
100
55°C
25
25°C
80K
85°C
30K
25°C
100
55°C
25
Typ
Max
Write/Erase cycles
Units
Cycle
Flash
Data retention
Year
Write/Erase cycles
Cycle
EEPROM
Data retention
Table 30-4.
Symbol
Programming time
Parameter
Chip Erase
Flash
EEPROM
Notes:
Year
Condition
Flash, EEPROM
(2)
and SRAM Erase
Min
Typ(1)
Max
Units
40
Page Erase
6
Page Write
6
Page WriteAutomatic Page Erase and Write
12
Page Erase
6
Page Write
6
Page WriteAutomatic Page Erase and Write
12
ms
1. Programming is timed from the internal 2 MHz oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
59
8134I–AVR–12/10
XMEGA D3
30.5
ADC Characteristics
Table 30-5.
ADC Characteristics
Symbol
Parameter
RES
Resolution
INL
DNL
Condition
Min
Typ
Max
Units
Programmable: 8/12
8
12
12
Bits
Integral Non-Linearity
Differential mode, 80ksps
-5
±2
5
Differential Non-Linearity
Differential mode, 80ksps
LSB
< ±1
Gain Error
< ±10
Offset Error
< ±2
mV
ADCclk
ADC Clock frequency
Max is 1/4 of Peripheral Clock
Conversion rate
Conversion time
(propagation delay)
(RES+2)/2+GAIN
RES = 8 or 12, GAIN = 0, 1, 2 or 3
Sampling Time
1/2 ADCclk cycle
Analog Supply Voltage
VREF
Reference voltage
7
kHz
200
ksps
10
ADCclk
cycles
0.36
Conversion range
AVCC
5
1400
uS
0
VREF
Vcc-0.3
Vcc+0.3
1.0
Vcc-0.6V
Input bandwidth
INT1V
kHz
(1)
1.00
Internal 1.00V reference
INTVCC
Internal VCC/1.6
VCC/1.6
SCALEDVCC
Scaled internal VCC/10 input
VCC/10
Reference input resistance
> 10
RAREF
Start-up time
Internal input sampling speed
Note:
V
12
Temp. sensor, VCC/10, Bandgap
V
MΩ
24
ADCclk
cycles
100
ksps
Max
Units
1. Refer to ”Bandgap Characteristics” on page 61 for more parameter details.
Table 30-6.
Symbol
ADC Gain Stage Characteristics
Parameter
Gain error
Condition
1 to 64 gain
Noise level at input
Clock rate
Typ
< ±1
Offset error
Vrms
Min
%
< ±1
VREF = Int. 1V
0.12
VREF = Ext. 2V
0.06
mV
64x gain
Same as ADC
200
kHz
60
8134I–AVR–12/10
XMEGA D3
30.6
Analog Comparator Characteristics
Table 30-7.
Symbol
Analog Comparator Characteristics
Parameter
Condition
Input Offset Voltage
VCC = 1.6 - 3.6V
<±10
mV
Input Leakage Current
VCC = 1.6 - 3.6V
< 1000
pA
Vhys1
Hysteresis, No
VCC = 1.6 - 3.6V
0
mV
Vhys2
Hysteresis, Small
VCC = 1.6 - 3.6V
20
Vhys3
Hysteresis, Large
VCC = 1.6 - 3.6V
40
tdelay
Propagation delay
VCC = 1.6 - 3.6V
175
Voff
Ilk
30.7
Min
Typ
Max
Units
mV
ns
Bandgap Characteristics
Table 30-8.
Symbol
Bandgap Voltage Characteristics
Parameter
Condition
Min
Typ
Max
As reference for ADC
1 Clk_PER + 2.5µs
As input to AC or ADC
1.5
Bandgap Startup Time
Units
µs
Bandgap voltage
1.1
V
INT1V
30.8
Internal 1.00V reference
T= 85°C, After calibration
Variation over voltage and temperature
VCC = 1.6 - 3.6V, TA = -40°C to 85°C
0.99
1
1.01
±2
%
Brownout Detection Characteristics
Brownout Detection Characteristics(1)
Table 30-9.
Symbol
Parameter
BOD level 0 falling Vcc
Condition
T= 85°C
Min
Typ
Max
1.62
1.63
1.7
BOD level 1 falling Vcc
1.9
BOD level 2 falling Vcc
2.17
BOD level 3 falling Vcc
2.43
BOD level 4 falling Vcc
2.68
BOD level 5 falling Vcc
2.96
BOD level 6 falling Vcc
3.22
BOD level 7 falling Vcc
3.49
Units
V
Hysteresis
Note:
BOD level 0-5
1
%
1. BOD is calibrated at 85°C within the BOD level 0 values, and BOD level 0 is the default level.
61
8134I–AVR–12/10
XMEGA D3
30.9
PAD Characteristics
Table 30-10. PAD Characteristics
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOL
VOH
Output Low Voltage GPIO
Output High Voltage GPIO
Condition
Min
Typ
Max
VCC = 2.4 - 3.6V
0.7*VCC
VCC+0.5
VCC = 1.6 - 2.4V
0.8*VCC
VCC+0.5
VCC = 2.4 - 3.6V
-0.5
0.3*VCC
VCC = 1.6 - 2.4V
-0.5
0.2*VCC
IOH = 8 mA, VCC = 3.3V
0.4
0.76
IOH = 5 mA, VCC = 3.0V
0.3
0.64
IOH = 3 mA, VCC = 1.8V
0.2
0.46
V
IOH = -4 mA, VCC = 3.3V
2.6
2.9
IOH = -3 mA, VCC = 3.0V
2.1
2.7
IOH = -1 mA, VCC = 1.8V
1.4
1.6
IIL
Input Leakage Current I/O pin
<0.001
1
IIH
Input Leakage Current I/O pin
<0.001
1
RP
I/O pin Pull/Buss keeper Resistor
20
Reset pin Pull-up Resistor
20
Input hysteresis
0.5
RRST
Units
µA
kΩ
V
30.10 POR Characteristics
Table 30-11. Power-on Reset Characteristics
Symbol
Parameter
VPOT-
POR threshold voltage falling VCC
VPOT+
POR threshold voltage rising VCC
Condition
Min
Typ
VCC falls faster than 1V/ms
0.4
0.8
VCC falls at 1V/ms or slower
0.8
1.3
Max
Units
V
1.3
1.59
Typ
Max
Units
90
1000
ns
30.11 Reset Characteristics
Table 30-12. Reset Characteristics
Symbol
Parameter
Condition
Minimum reset pulse width
Reset threshold voltage
Min
VCC = 2.7 - 3.6V
0.45*VCC
VCC = 1.6 - 2.7V
0.42*VCC
V
62
8134I–AVR–12/10
XMEGA D3
30.12 Oscillator Characteristics
Table 30-13. Internal 32.768kHz Oscillator Characteristics
Symbol
Parameter
Accuracy
Condition
T = 85°C, VCC = 3V,
After production calibration
Min
Typ
-0.5
Max
Units
0.5
%
Max
Units
Table 30-14. Internal 2MHz Oscillator Characteristics
Symbol
Parameter
Accuracy
DFLL Calibration step size
Condition
T = 85°C, VCC = 3V,
After production calibration
Min
Typ
-1.5
1.5
%
T = 25°C, VCC = 3V
0.15
Table 30-15. Internal 32MHz Oscillator Characteristics
Symbol
Parameter
Accuracy
DFLL Calibration stepsize
Condition
T = 85°C, VCC = 3V,
After production calibration
Min
Typ
-1.5
Max
Units
1.5
%
T = 25°C, VCC = 3V
0.2
Table 30-16. Internal 32kHz, ULP Oscillator Characteristics
Symbol
Parameter
Output frequency 32 kHz ULP OSC
Condition
Min
T = 85°C, VCC = 3.0V
Typ
Max
26
Units
kHz
Table 30-17. External 32.768kHz Crystal Oscillator and TOSC characteristics
Symbol
SF
Parameter
Safety factor
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
CIN_TOSC
Input capacitance between TOSC
pins
Note:
Condition
Capacitive load matched to crystal
specification
Min
Typ
Max
Units
3
Crystal load capacitance 6.5pF
60
Crystal load capacitance 9.0pF
35
kΩ
Normal mode
1.7
Low power mode
2.2
pF
1. See Figure 30-2 on page 64 for definition
63
8134I–AVR–12/10
XMEGA D3
Figure 30-2. TOSC input capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768 KHz crystal
The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal
when oscillating without external capacitors.
Table 30-18. Device wake-up time from sleep
Symbol
Parameter
Condition(1)
Int. 32.768 kHz RC
Idle Sleep, Standby and Extended
Standby sleep mode
Min
Typ(2)
Max
Units
130
Int. 2 MHz RC
2
Ext. 2 MHz Clock
2
Int. 32 MHz RC
0.17
Int. 32.768 kHz RC
320
Int. 2 MHz RC
10.3
Ext. 2 MHz Clock
4.5
Int. 32 MHz RC
5.8
µS
Power-save and Power-down Sleep
mode
Notes:
1. Non-prescaled System Clock source.
2. Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response time is minimum
5 system clock source cycles.
64
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XMEGA D3
31. Typical Characteristics
31.1
Active Supply Current
Figure 31-1. Active Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz External clock, T = 25°C
ICC [uA]
900
800
3.3 V
700
3.0 V
600
2.7 V
500
2.2 V
400
1.8 V
300
200
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 31-2. Active Supply Current vs. Frequency
fSYS = 1 - 32 MHz External clock, T = 25°C
ICC [mA]
20
18
3.3 V
16
3.0 V
14
2.7 V
12
10
8
2.2 V
6
4
1.8 V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
65
8134I–AVR–12/10
XMEGA D3
Figure 31-3. Active Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
85 °C
25 °C
-40 °C
1000
900
800
ICC [uA]
700
600
500
400
300
200
100
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-4. Active Supply Current vs. VCC
fSYS = 32.768 kHz internal RC
140
-40 °C
25 °C
85 °C
120
ICC [uA]
100
80
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
66
8134I–AVR–12/10
XMEGA D3
Figure 31-5. Active Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
2000
-40 °C
25 °C
85 °C
1800
1600
ICC [uA]
1400
1200
1000
800
600
400
200
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-6. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
8
-40 °C
25 °C
85 °C
7
6
ICC [mA]
5
4
3
2
1
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
67
8134I–AVR–12/10
XMEGA D3
Figure 31-7. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC
25
-40 °C
25 °C
85 °C
ICC [mA]
20
15
10
5
0
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
31.2
Idle Supply Current
Figure 31-8. Idle Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz, T = 25°C
250
3.3 V
3.0 V
200
ICC [uA]
2.7 V
150
2.2 V
1.8 V
100
50
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
68
8134I–AVR–12/10
XMEGA D3
Figure 31-9. Idle Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25°C
8
3.3 V
7
3.0 V
6
2.7 V
ICC [mA]
5
4
3
2.2 V
2
1.8 V
1
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
Figure 31-10. Idle Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
300
85 °C
25 °C
-40 °C
250
ICC [uA]
200
150
100
50
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
69
8134I–AVR–12/10
XMEGA D3
Figure 31-11. Idle Supply Current vs. Vcc
fSYS = 32.768 kHz internal RC
40
85 °C
-40 °C
25 °C
35
30
ICC [uA]
25
20
15
10
5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-12. Idle Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
700
-40 °C
25 °C
85 °C
600
ICC [uA]
500
400
300
200
100
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
70
8134I–AVR–12/10
XMEGA D3
Figure 31-13. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
3.5
-40 °C
25 °C
85 °C
3.0
ICC [mA]
2.5
2.0
1.5
1.0
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-14. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC
10
-40 °C
25 °C
85 °C
ICC [mA]
8
6
4
2
0
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
71
8134I–AVR–12/10
XMEGA D3
31.3
Power-down Supply Current
Figure 31-15. Power-down Supply Current vs. Temperature
2
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.8
1.6
ICC [uA]
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
Figure 31-16. Power-down Supply Current vs. Temperature
With WDT and sampled BOD enabled.
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
3
2.5
ICC [uA]
2
1.5
1
0.5
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
72
8134I–AVR–12/10
XMEGA D3
31.4
Power-save Supply Current
Figure 31-17. Power-save Supply Current vs. Temperature
With WDT, sampled BOD and RTC from ULP enabled
3
3.3 V
3.0 V
2.7 V
1.8 V
2.2 V
2.5
ICC [uA]
2
1.5
1
0.5
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
31.5
Pin Pull-up
Figure 31-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
100
IRESET [uA]
80
60
40
20
-40 °C
25 °C
85 °C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VRESET [V]
73
8134I–AVR–12/10
XMEGA D3
Figure 31-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
160
140
IRESET [uA]
120
100
80
60
40
-40 °C
25 °C
85 °C
20
0
0
0.5
1
1.5
2
2.5
3
VRESET [V]
Figure 31-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
180
160
140
IRESET [uA]
120
100
80
60
40
-40 °C
25 °C
85 °C
20
0
0
0.5
1
1.5
2
2.5
3
VRESET [V]
74
8134I–AVR–12/10
XMEGA D3
31.6
Pin Output Voltage vs. Sink/Source Current
Figure 31-21. I/O Pin Output Voltage vs. Source Current
Vcc = 1.8V
2
-40 °C
25 °C
85 °C
1.8
1.6
VPIN [V]
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
Figure 31-22. I/O Pin Output Voltage vs. Source Current
Vcc = 3.0V
3.5
-40 °C
25 °C
85 °C
3
VPIN [V]
2.5
2
1.5
1
0.5
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
75
8134I–AVR–12/10
XMEGA D3
Figure 31-23. I/O Pin Output Voltage vs. Source Current
Vcc = 3.3V
3.5
-40 °C
25 °C
85 °C
3
VPIN [V]
2.5
2
1.5
1
0.5
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
Figure 31-24. I/O Pin Output Voltage vs. Sink Current
Vcc = 1.8V
85°C 25°C
1.8
1.6
1.4
VPIN [V]
1.2
-40 °C
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
IPIN [mA]
6
7
8
9
10
76
8134I–AVR–12/10
XMEGA D3
Figure 31-25. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.0V
0.7
85 °C
0.6
25 °C
-40 °C
VPIN [V]
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
Figure 31-26. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.3V
VPIN [V]
0.7
0.6
85 °C
0.5
25 °C
-40 °C
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
77
8134I–AVR–12/10
XMEGA D3
31.7
Pin Thresholds and Hysteresis
Figure 31-27. I/O Pin Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
2.5
-40 °C
25 °C
85 °C
Vthreshold [V]
2
1.5
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-28. I/O Pin Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
1.8
85 °C
25 °C
-40 °C
1.6
1.4
Vthreshold [V]
1.2
1
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
78
8134I–AVR–12/10
XMEGA D3
Figure 31-29. I/O Pin Input Hysteresis vs. VCC
0.7
0.6
Vthreshold [V]
0.5
85 °C
25 °C
-40 °C
0.4
0.3
0.2
0.1
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-30. Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
1.8
-40 °C
25 °C
85 °C
1.6
VTHRESHOLD [V]
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
79
8134I–AVR–12/10
XMEGA D3
Figure 31-31. Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
1.8
-40 °C
25 °C
85 °C
1.6
VTHRESHOLD [V]
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
31.8
Bod Thresholds
Figure 31-32. BOD Thresholds vs. Temperature
BOD Level = 1.6V
VBOT [V]
1.67
1.66
Rising Vcc
1.65
Falling Vcc
1.64
1.63
1.62
1.61
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
80
8134I–AVR–12/10
XMEGA D3
Figure 31-33. BOD Thresholds vs. Temperature
BOD Level = 2.9V
3.06
3.04
Rising Vcc
3.02
VBOT [V]
3
2.98
Falling Vcc
2.96
2.94
2.92
2.9
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
31.9
31.9.1
Oscillators and Wake-up Time
Internal 32.768 kHz Oscillator
Figure 31-34. Internal 32.768 kHz Oscillator Calibration Step Size
T = -40 to 85°C, VCC = 3V
0.80 %
Step size: f [kHz]
0.65 %
0.50 %
0.35 %
0.20 %
0.05 %
0
32
64
96
128
160
192
224
256
RC32KCAL[7..0]
81
8134I–AVR–12/10
XMEGA D3
31.9.2
Internal 2 MHz Oscillator
Figure 31-35. Internal 2 MHz Oscillator CALA Calibration Step Size
T = -40 to 85°C, VCC = 3V
0.50 %
0.40 %
Step size: f [MHz]
0.30 %
0.20 %
0.10 %
0.00 %
-0.10 %
-0.20 %
-0.30 %
0
16
32
48
64
80
96
112
128
56
64
DFLLRC2MCALA
Figure 31-36. Internal 2 MHz Oscillator CALB Calibration Step Size
T = -40 to 85°C, VCC = 3V
3.00 %
Step size: f [MHz]
2.50 %
2.00 %
1.50 %
1.00 %
0.50 %
0.00 %
0
8
16
24
32
40
48
DFLLRC2MCALB
82
8134I–AVR–12/10
XMEGA D3
31.9.3
Internal 32 MHZ Oscillator
Figure 31-37. Internal 32 MHz Oscillator CALA Calibration Step Size
T = -40 to 85°C, VCC = 3V
0.60 %
0.50 %
Step size: f [MHz]
0.40 %
0.30 %
0.20 %
0.10 %
0.00 %
-0.10 %
-0.20 %
0
16
32
48
64
80
96
112
128
56
64
DFLLRC32MCALA
Figure 31-38. Internal 32 MHz Oscillator CALB Calibration Step Size
T = -40 to 85°C, VCC = 3V
3.00 %
Step size: f [MHz]
2.50 %
2.00 %
1.50 %
1.00 %
0.50 %
0.00 %
0
8
16
24
32
40
48
DFLLRC32MCALB
83
8134I–AVR–12/10
XMEGA D3
31.10 Module current consumption
Figure 31-39. AC current consumption vs. Vcc
Low-power Mode
Module current consumption [uA]
120
85 °C
25 °C
100
-40 °C
80
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 31-40. Power-up current consumption vs. Vcc
-40 °C
25 °C
85 °C
700
600
ICC [uA]
500
400
300
200
100
0
0.4
0.6
0.8
1
1.2
1.4
1.6
VCC [V]
84
8134I–AVR–12/10
XMEGA D3
31.11 Reset Pulsewidth
Figure 31-41. Minimum Reset Pulse Width vs. Vcc
120
100
85 °C
25 °C
-40 °C
tRST [ns]
80
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
31.12 PDI Speed
Figure 31-42. PDI Speed vs. Vcc
35
25 °C
30
fMAX [MHz]
25
20
15
10
5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
85
8134I–AVR–12/10
XMEGA D3
32. Packaging information
32.1
64A
PIN 1
B
e
PIN 1 IDENTIFIER
E1
E
D1
D
C
0°~7°
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
2010-10-20
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
64A
C
86
8134I–AVR–12/10
XMEGA D3
32.2
64M2
D
Marked Pin# 1 ID
E
C
SEATING PLANE
A1
TOP VIEW
A3
A
K
0.08 C
L
Pin #1 Corner
D2
1
2
3
SIDE VIEW
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
Option B
Pin #1
Chamfer
(C 0.30)
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
A3
K
Option C
b
e
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
0.20 REF
b
0.18
0.25
0.30
D
8.90
9.00
9.10
D2
7.50
7.65
7.80
E
8.90
9.00
9.10
E2
7.50
7.65
7.80
e
Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
NOTE
0.50 BSC
L
0.35
0.40
0.45
K
0.20
0.27
0.40
2010-10-20
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
7.65 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
64M2
REV.
E
87
8134I–AVR–12/10
XMEGA D3
33. Errata
33.1
33.1.1
ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3
rev. E
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4 V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8x -64x gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Crystal start-up time required after power-save even if crystal is source for RTC
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
TWIE is not available
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
88
8134I–AVR–12/10
XMEGA D3
Figure 33-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
3.5
3.3 V
3
2.7 V
VSCALE [V]
2.5
2
1.8 V
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
SCALEFAC
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and
started from software or event system.
Problem fix/Workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
– 6LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error. Use the ADC in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
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XMEGA D3
–
1x
gain:
2.4
V
–
2x
gain:
1.2
V
–
4x
gain:
0.6
V
–
8x
gain:
300
mV
–
16x
gain:
150
mV
–
32x
gain:
75
mV
–
64x
gain:
38
mV
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8x -64x gain is used
The propagation delay will increase by only one ADC clock cycle for 8x and 16x gain setting,
and 32x and 64x gain settings.
Problem fix/Workaround
None
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
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Problem fix/Workaround
Table 33-1. Configure PWM and CWCM according to this table:
PGM
CWCM
Description
0
0
PGM and CWCM disabled
0
1
PGM enabled
1
0
PGM and CWCM enabled
1
1
PGM enabled
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
17. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
18. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
19. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
20. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
21. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
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((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
22. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
23. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
24. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
25. TWIE is not available
The TWI module on PORTE, TWIE is not available
Problem fix/Workaround
Use the identical TWI module on PORTC, TWIC instead.
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33.1.2
rev. B
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
ADC gain stage cannot be used for single conversion
ADC has increased INL error for some operating conditions
ADC gain stage output range is limited to 2.4 V
ADC Event on compare match non-functional
ADC propagation delay is not correct when 8x -64x gain is used
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
NMI Flag for Crystal Oscillator Failure automatically cleared
Writing EEPROM or Flash while reading any of them will not work
Crystal start-up time required after power-save even if crystal is source for RTC
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag (DIF) erroneously read as set
WDR instruction inside closed window will not issue reset
TWIE is not available
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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Figure 33-2. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
3.5
3.3 V
3
2.7 V
VSCALE [V]
2.5
2
1.8 V
1.5
1
0.5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
SCALEFAC
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversion that is triggered and
started from software or event system.
Problem fix/Workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate.
– 6LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error. Use the ADC in signed mode also for single ended measurements.
5. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
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XMEGA D3
–
1x
gain:
2.4
V
–
2x
gain:
1.2
V
–
4x
gain:
0.6
V
–
8x
gain:
300
mV
–
16x
gain:
150
mV
–
32x
gain:
75
mV
–
64x
gain:
38
mV
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
7. ADC propagation delay is not correct when 8x -64x gain is used
The propagation delay will increase by only one ADC clock cycle for 8x and 16x gain setting,
and 32x and 64x gain settings.
Problem fix/Workaround
None
8. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
9. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
10. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
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Problem fix/Workaround
Table 33-2. Configure PWM and CWCM according to this table:
PGM
CWCM
Description
0
0
PGM and CWCM disabled
0
1
PGM enabled
1
0
PGM and CWCM enabled
1
1
PGM enabled
11. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
12. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
13. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
14. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
15. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
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16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
17. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.
Problem fix/Workaround
Enter IDLE sleep mode within 2.5 µs (Five 2 MHz clock cycles and 80 32 MHz clock cycles)
after starting an EEPROM or flash write operation. Wake-up source must either be
EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an
overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic
erase-and-write operation has started, and then enter IDLE sleep mode.
18. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
19. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
20. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
21. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
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22. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
23. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
24. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
25. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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26. TWIE is not available
The TWI module on PORTE, TWIE is not available
Problem fix/Workaround
Use the identical TWI module on PORTC, TWIC instead.
33.1.3
All rev. A
Not sampled.
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34. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revisions in this section are referring to the document revision.
34.1
34.2
34.3
34.4
8134I – 12/10
1.
Datasheet status changed to complete: Preliminary removed from front page.
2.
Updated all tables in the “Electrical Characteristics” .
3.
Replaced Table 30-11 on page 62
4.
Replaced Table 30-17 on page 63 and added the figure ”TOSC input capacitance” on page 64
5.
Added ERRATA ”rev. E” on page 88.
6.
Updated ERRATA for ADC (ADC has increased INL error for some operating conditions).
7
Updated ERRATA ”rev. B” on page 94 with TWIE (TWIE is not available).
8.
Updated the last page by Atmel new Brand Style Guide.
1.
Updated ”Errata” on page 88.
1.
Updated the Footnote 3 of ”Ordering Information” on page 2.
2.
All references to CRC removed. Updated Figure 3-1 on page 5.
3.
Updated ”Features” on page 26. Event Channel 0 output on port pin 7.
4.
Updated ”DC Characteristics” on page 56 by adding Icc for Flash/EEPROM Programming.
5.
Added AVCC in ”ADC Characteristics” on page 60.
6.
Updated Start up time in ”ADC Characteristics” on page 60.
7.
Updated and fixed typo in “Errata” section.
1.
Added ”PDI Speed” on page 85.
8134H – 09/10
8134G – 08/10
8134F – 02/10
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34.5
34.6
34.7
34.8
8134E – 01/10
1.
Updated the device pin-out Figure 2-1 on page 3. PDI_CLK and PDI_DATA renamed only PDI.
2.
Updated ”ADC - 12-bit Analog to Digital Converter” on page 39.
3.
Updated Figure 23-1 on page 40.
4.
Updated ”Alternate Pin Function Description” on page 46.
5.
Updated ”Alternate Pin Functions” on page 48.
6.
Updated ”Timer/Counter and AWEX functions” on page 46.
7.
Added Table 30-17 on page 63.
8.
Added Table 30-18 on page 64.
9.
Changed Internal Oscillator Speed to ”Oscillators and Wake-up Time” on page 81.
10.
Updated ”Errata” on page 88.
1.
Added Table 30-3 on page 59, Endurance and Data Retention.
2.
Updated Table 30-10 on page 62, Input hysteresis is in V and not in mV.
3.
Added ”Errata” on page 88.
4.
Editing updates.
1.
Updated ”Features” on page 1 with Two Two-Wire Interfaces.
2.
Updated ”Block diagram and pinout” on page 3.
3.
Updated ”Overview” on page 4.
4.
Updated ”XMEGA D3 Block Diagram” on page 5.
5.
Updated Table 13-1 on page 24.
6.
Updated ”Overview” on page 35.
7.
Updated Table 27-5 on page 49.
8.
Updated ”Peripheral Module Address Map” on page 51.
1.
Added ”Electrical Characteristics” on page 56.
2.
Added ”Typical Characteristics” on page 65.
8134D – 11/09
8134C – 10/09
8134B – 08/09
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XMEGA D3
34.9
8134A – 03/09
1.
Initial revision.
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XMEGA D3
Table of Contents
Features ..................................................................................................... 1
Typical Applications ................................................................................ 1
1
Ordering Information ............................................................................... 2
2
Pinout/ Block Diagram ............................................................................. 3
3
Overview ................................................................................................... 4
3.1Block Diagram ...........................................................................................................5
4
Resources ................................................................................................. 6
4.1Recommended reading .............................................................................................6
5
Disclaimer ................................................................................................. 6
6
AVR CPU ................................................................................................... 7
6.1Features ....................................................................................................................7
6.2Overview ...................................................................................................................7
6.3Register File ..............................................................................................................8
6.4ALU - Arithmetic Logic Unit .......................................................................................8
6.5Program Flow ............................................................................................................8
7
Memories .................................................................................................. 9
7.1Features ....................................................................................................................9
7.2Overview ...................................................................................................................9
7.3In-System Programmable Flash Program Memory ...................................................9
7.4Data Memory ...........................................................................................................11
7.5Production Signature Row .......................................................................................13
7.6User Signature Row ................................................................................................13
7.7Flash and EEPROM Page Size ...............................................................................14
8
Event System ......................................................................................... 15
8.1Features ..................................................................................................................15
8.2Overview .................................................................................................................15
9
System Clock and Clock options ......................................................... 17
9.1Features ..................................................................................................................17
9.2Overview .................................................................................................................17
9.3Clock Options ..........................................................................................................18
10 Power Management and Sleep Modes ................................................. 20
i
8134I–AVR–12/10
10.1Features ................................................................................................................20
10.2Overview ...............................................................................................................20
10.3Sleep Modes .........................................................................................................20
11 System Control and Reset .................................................................... 22
11.1Features ................................................................................................................22
11.2Resetting the AVR .................................................................................................22
11.3Reset Sources .......................................................................................................22
12 WDT - Watchdog Timer ......................................................................... 23
12.1Features ................................................................................................................23
12.2Overview ...............................................................................................................23
13 PMIC - Programmable Multi-level Interrupt Controller ....................... 24
13.1Features ................................................................................................................24
13.2Overview ...............................................................................................................24
13.3Interrupt vectors ....................................................................................................24
14 I/O Ports .................................................................................................. 26
14.1Features ................................................................................................................26
14.2Overview ...............................................................................................................26
14.3I/O configuration ....................................................................................................26
14.4Input sensing .........................................................................................................29
14.5Port Interrupt .........................................................................................................29
14.6Alternate Port Functions ........................................................................................29
15 T/C - 16-bits Timer/Counter with PWM ................................................. 30
15.1Features ................................................................................................................30
15.2Overview ...............................................................................................................30
16 AWEX - Advanced Waveform Extension ............................................. 32
16.1Features ................................................................................................................32
16.2Overview ...............................................................................................................32
17 Hi-Res - High Resolution Extension ..................................................... 33
17.1Features ................................................................................................................33
17.2Overview ...............................................................................................................33
18 RTC - Real-Time Counter ...................................................................... 34
18.1Features ................................................................................................................34
18.2Overview ...............................................................................................................34
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19 TWI - Two Wire Interface ....................................................................... 35
19.1Features ................................................................................................................35
19.2Overview ...............................................................................................................35
20 SPI - Serial Peripheral Interface ............................................................ 36
20.1Features ................................................................................................................36
20.2Overview ...............................................................................................................36
21 USART ..................................................................................................... 37
21.1Features ................................................................................................................37
21.2Overview ...............................................................................................................37
22 IRCOM - IR Communication Module .................................................... 38
22.1Features ................................................................................................................38
22.2Overview ...............................................................................................................38
23 ADC - 12-bit Analog to Digital Converter ............................................. 39
23.1Features ................................................................................................................39
23.2Overview ...............................................................................................................39
24 AC - Analog Comparator ....................................................................... 41
24.1Features ................................................................................................................41
24.2Overview ...............................................................................................................41
24.3Input Selection .......................................................................................................43
24.4Window Function ...................................................................................................43
25 OCD - On-chip Debug ............................................................................ 44
25.1Features ................................................................................................................44
25.2Overview ...............................................................................................................44
26 PDI - Program and Debug Interface ..................................................... 45
26.1Features ................................................................................................................45
26.2Overview ...............................................................................................................45
27 Pinout and Pin Functions ...................................................................... 46
27.1Alternate Pin Function Description ........................................................................46
27.2Alternate Pin Functions .........................................................................................48
28 Peripheral Module Address Map .......................................................... 51
29 Instruction Set Summary ...................................................................... 52
30 Electrical Characteristics ...................................................................... 56
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30.1Absolute Maximum Ratings* .................................................................................56
30.2DC Characteristics ................................................................................................56
30.3Operating Voltage and Frequency ........................................................................58
30.4Flash and EEPROM Memory Characteristics .......................................................59
30.5ADC Characteristics ..............................................................................................60
30.6Analog Comparator Characteristics .......................................................................61
30.7Bandgap Characteristics .......................................................................................61
30.8Brownout Detection Characteristics ......................................................................61
30.9PAD Characteristics ..............................................................................................62
30.10POR Characteristics ............................................................................................62
30.11Reset Characteristics ..........................................................................................62
30.12Oscillator Characteristics ....................................................................................63
31 Typical Characteristics .......................................................................... 65
31.1Active Supply Current ............................................................................................65
31.2Idle Supply Current ................................................................................................68
31.3Power-down Supply Current .................................................................................72
31.4Power-save Supply Current ..................................................................................73
31.5Pin Pull-up .............................................................................................................73
31.6Pin Output Voltage vs. Sink/Source Current .........................................................75
31.7Pin Thresholds and Hysteresis ..............................................................................78
31.8Bod Thresholds .....................................................................................................80
31.9Oscillators and Wake-up Time ..............................................................................81
31.10Module current consumption ...............................................................................84
31.11Reset Pulsewidth .................................................................................................85
31.12PDI Speed ...........................................................................................................85
32 Packaging information .......................................................................... 86
32.164A ........................................................................................................................86
32.264M2 .....................................................................................................................87
33 Errata ....................................................................................................... 88
33.1ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3 ...................88
34 Datasheet Revision History ................................................................ 101
34.18134I – 12/10 ......................................................................................................101
34.28134H – 09/10 .....................................................................................................101
34.38134G – 08/10 .....................................................................................................101
34.48134F – 02/10 .....................................................................................................101
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34.58134E – 01/10 .....................................................................................................102
34.68134D – 11/09 .....................................................................................................102
34.78134C – 10/09 .....................................................................................................102
34.88134B – 08/09 .....................................................................................................102
34.98134A – 03/09 .....................................................................................................103
Table of Contents....................................................................................... i
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8134I–AVR–12/10