250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar, 16-/14-/12-Bit ADC AD7656-1/AD7657-1/AD7658-1 FEATURES Pin and software compatible with AD7656/AD7657/AD7658 featuring reduced decoupling requirements 6 independent ADCs True bipolar analog inputs Pin-/software-selectable ranges: ±10 V, ±5 V Fast throughput rate: 250 kSPS iCMOS process technology Low power 140 mW at 250 kSPS with 5 V supplies High noise performance with wide bandwidth 88 dB SNR at 10 kHz input frequency On-chip reference and reference buffers High speed parallel, serial, and daisy-chain interface modes High speed serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Standby mode: 25 μW max 64-lead LQFP FUNCTIONAL BLOCK DIAGRAM CONVST A CONVST B CONVST C AVCC DVCC VDD REF CLK OSC CS SER/PAR SEL VDRIVE CONTROL LOGIC STBY BUF V1 T/H 16-/14-/ 12-BIT SAR V2 T/H 16-/14-/ 12-BIT SAR OUTPUT DRIVERS DB8/DOUT A DB6/SCLK OUTPUT DRIVERS BUF V3 V4 T/H 16-/14-/ 12-BIT SAR T/H 16-/14-/ 12-BIT SAR BUF V5 T/H 16-/14-/ 12-BIT SAR V6 T/H 16-/14-/ 12-BIT SAR DB9/DOUT B OUTPUT DRIVERS DB10/DOUT C OUTPUT DRIVERS DATA/ CONTROL LINES RD AD7656-1/AD7657-1/AD7658-1 Power line monitoring and measuring systems Instrumentation and control systems Multiaxis positioning systems VSS AGND 07017-001 WR/REFEN/DIS APPLICATIONS DGND Figure 1. GENERAL DESCRIPTION The AD7656-1/AD7657-1/AD7658-11 are reduced decoupling pinand software-compatible versions of AD7656/AD7657/AD7658. The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/ 14-/12-bit, fast, low power successive approximation ADCs in a package designed on the iCMOS® process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size. The conversion process and data acquisition are controlled using the CONVST signals and an internal oscillator. Three CONVST pins (CONVST A, CONVST B, and CONVST C) allow independent, simultaneous sampling of the three ADC pairs. The AD7656-1/AD7657-1/AD7658-1 have a high speed parallel and serial interface, allowing the devices to interface with microprocessors or DSPs. When the serial interface is selected, each part has a daisy-chain feature that allows multiple ADCs to connect to a single serial interface. The AD7656-1/AD7657-1/ AD7658-1 can accommodate true bipolar input signals in the ±4 × VREF and ±2 × VREF ranges. Each AD7656-1/AD7657-1/ AD7658-1 also contains an on-chip 2.5 V reference. The AD7656-1/AD7657-1/AD7658-1 feature throughput rates of up to 250 kSPS. The parts contain low noise, wide bandwidth track-and-hold amplifiers that can handle input frequencies up to 4.5 MHz. 1. 2. 3. 4. 1 PRODUCT HIGHLIGHTS Six 16-/14-/12-bit, 250 kSPS ADCs on board. Six true bipolar, high impedance analog inputs. High speed parallel and serial interfaces. Reduced decoupling requirements and reduced bill of materials cost compared with the AD7656/AD7657/ AD7658 devices. Protected by U.S. Patent No. 6,731,232. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD7656-1/AD7657-1/AD7658-1 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions........................... 11 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 14 Functional Block Diagram .............................................................. 1 Terminology .................................................................................... 18 General Description ......................................................................... 1 Theory of Operation ...................................................................... 20 Product Highlights ........................................................................... 1 Converter Details ....................................................................... 20 Revision History ............................................................................... 2 ADC Transfer Function ............................................................. 21 Specifications..................................................................................... 3 Internal/External Reference ...................................................... 21 AD7656-1 ...................................................................................... 3 Typical Connection Diagram ................................................... 21 AD7657-1 ...................................................................................... 5 Driving the Analog Inputs ........................................................ 22 AD7658-1 ...................................................................................... 7 Interface Options ........................................................................ 22 Timing Specifications .................................................................. 9 Application Hints ........................................................................... 29 Absolute Maximum Ratings.......................................................... 10 Layout .......................................................................................... 29 Thermal Resistance .................................................................... 10 Outline Dimensions ....................................................................... 30 ESD Caution ................................................................................ 10 Ordering Guide .......................................................................... 30 REVISION HISTORY 7/08—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7656-1/AD7657-1/AD7658-1 SPECIFICATIONS AD7656-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for the ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for the ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Delay Matching Aperture Jitter Channel-to-Channel Isolation2 Full-Power Bandwidth DC ACCURACY Resolution No Missing Codes Integral Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Matching2 Bipolar Zero-Scale Error2 Bipolar Zero-Scale Error Matching2 Negative Full-Scale Error2 Negative Full-Scale Error Matching2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance3 Reference Output Voltage Long-Term Stability Reference Temperature Coefficient B Version 1 Y Version1 Unit 88 88 −90 −105 −100 88 88 −90 −105 −100 dB typ dB typ dB max dB typ dB typ −112 −107 10 4 35 −100 4.5 2.2 −112 −107 10 4 35 −100 4.5 2.2 dB typ dB typ ns max ns max ps typ dB typ MHz typ MHz typ 16 15 ±3 ±1 ±0.8 ±0.35 ±0.048 ±0.038 ±0.8 ±0.35 16 14 ±3 ±1 ±0.8 ±0.35 ±0.023 ±0.038 ±0.8 ±0.35 Bits Bits min LSB max LSB typ % FS max % FS max % FS max % FS max % FS max % FS max Test Conditions/Comments fIN = 10 kHz sine wave VDD/VSS = ±5 V to ±16.5 V fa = 10.5 kHz, fb = 9.5 kHz ±4 × VREF ±2 × VREF ±1 10 14 ±4 × VREF ±2 × VREF ±1 10 14 V V μA max pF typ pF typ 2.5 ±1 18.5 2.49/2.51 150 25 6 2.5 ±1 18.5 2.49/2.51 150 25 6 V min/max μA max pF typ V min/max ppm typ ppm/°C max ppm/°C typ Rev. 0 | Page 3 of 32 fIN on unselected channels up to 100 kHz @ −3 dB @ −0.1 dB ±0.381% FSR typical ±0.0137% FSR typical ±0.381% FSR typical See Table 8 for minimum VDD/VSS for each range RNGx bits or RANGE pin = 0 RNGx bits or RANGE pin = 1 ±4 × VREF range when in track ±2 × VREF range when in track REFEN/DIS = 1 1000 hours AD7656-1/AD7657-1/AD7658-1 Parameter LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS AVCC DVCC VDRIVE ITOTAL 4 Normal Mode—Static Normal Mode—Operational ISS (Operational) IDD (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) B Version 1 Y Version1 Unit 0.7 × VDRIVE 0.3 × VDRIVE ±10 10 0.7 × VDRIVE 0.3 × VDRIVE ±10 10 V min V max μA max pF max VDRIVE − 0.2 VDRIVE − 0.2 0.2 0.2 ±10 ±10 10 10 Twos complement V min V max μA max pF max 3.1 550 250 3.1 550 250 μs max ns max kSPS 5/15 −5/−15 5 5 3/5 5/15 −5/−15 5 5 3/5 V nom min/max V nom min/max V nom V nom V nom min/max 18 18 mA max 26 26 mA max 0.25 0.25 7 0.25 0.25 7 mA max mA max mA max 400 400 μA max 94 140 40 25 94 140 40 25 mW max mW max mW max μW max Power Dissipation Normal Mode—Static Normal Mode—Operational Partial Power-Down Mode Full Power-Down Mode (STBY Pin) 1 The temperature range for the B version is −40°C to +85°C and for the Y version is −40°C to +125°C. See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC. 2 Rev. 0 | Page 4 of 32 Test Conditions/Comments Typically 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 μA ISINK = 200 μA Parallel interface mode only For the 4 × VREF range, VDD = 10 V to 16.5 V For the 4 × VREF range, VDD = −10 V to −16.5 V Digital inputs = 0 V or VDRIVE AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V VSS = −16.5 V, fSAMPLE = 250 kSPS VDD = 16.5 V, fSAMPLE = 250 kSPS AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS AD7656-1/AD7657-1/AD7658-1 AD7657-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for the ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for the ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Delay Matching Aperture Jitter Channel-to-Channel Isolation2 Full-Power Bandwidth DC ACCURACY Resolution No Missing Codes Integral Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Matching2 Bipolar Zero-Scale Error2 Bipolar Zero-Scale Error Matching2 Negative Full-Scale Error2 Negative Full-Scale Error Matching2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance3 Reference Output Voltage Long-Term Stability Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 B Version 1 Y Version1 Unit 82.5 83.5 −90 −105 −100 82.5 83.5 −90 −105 −100 dB typ dB typ dB max dB typ dB typ −109 −104 10 4 35 −100 4.5 2.2 −109 −104 10 4 35 −100 4.5 2.2 dB typ dB typ ns max ns max ps typ dB typ MHz typ MHz typ 14 14 ±1 ±1 ±0.95 ±0.366 ±0.04 ±0.0427 ±0.95 ±0.366 14 14 ±1 ±1 ±0.95 ±0.366 ±0.04 ±0.0427 ±0.95 ±0.366 Bits Bits min LSB max LSB typ % FS max % FS max % FS max % FS max % FS max % FS max Test Conditions/Comments fIN = 10 kHz sine wave fa = 10.5 kHz, fb = 9.5 kHz ±4 × VREF ±2 × VREF ±1 10 14 ±4 × VREF ±2 × VREF ±1 10 14 V V μA max pF typ pF typ 2.5 ±1 18.5 2.49/2.51 150 25 6 2.5 ±1 18.5 2.49/2.51 150 25 6 V min/max μA max pF typ V min/max ppm typ ppm/°C max ppm/°C typ 0.7 × VDRIVE 0.3 × VDRIVE ±10 10 0.7 × VDRIVE 0.3 × VDRIVE ±10 10 V min V max μA max pF max Rev. 0 | Page 5 of 32 fIN on unselected channels up to 100 kHz @ −3 dB @ −0.1 dB ±0.27% FSR typical ±0.016% FSR typical ±0.27% FSR typical See Table 8 for minimum VDD/VSS for each range RNGx bits or RANGE pin = 0 RNGx bits or RANGE pin = 1 ±4 × VREF range when in track ±2 × VREF range when in track REFEN/DIS = 1 1000 hours Typically 10 nA, VIN = 0 V or VDRIVE AD7656-1/AD7657-1/AD7658-1 Parameter LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS AVCC DVCC VDRIVE ITOTAL 4 Normal Mode—Static Normal Mode—Operational ISS (Operational) IDD (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) B Version 1 Y Version1 Unit Test Conditions/Comments VDRIVE − 0.2 VDRIVE − 0.2 0.2 0.2 ±10 ±10 10 10 Twos complement V min V max μA max pF max ISOURCE = 200 μA ISINK = 200 μA 3.1 550 250 3.1 550 250 μs max ns max kSPS 5/15 −5/−15 5 5 3/5 5/15 −5/−15 5 5 3/5 V nom min/max V nom min/max V nom V nom V nom min/max 18 18 mA max 26 26 mA max 0.25 0.25 7 0.25 0.25 7 mA max mA max mA max 400 400 μA max 94 140 40 25 94 140 40 25 mW max mW max mW max μW max Power Dissipation Normal Mode—Static Normal Mode—Operational Partial Power-Down Mode Full Power-Down Mode (STBY Pin) 1 The temperature range for the B version is −40°C to +85°C and for the Y version is −40°C to +125°C. See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC. 2 Rev. 0 | Page 6 of 32 Parallel interface mode only For the 4 × VREF range, VDD = 10 V to 16.5 V For the 4 × VREF range, VDD = −10 V to −16.5 V Digital inputs = 0 V or VDRIVE AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V VSS = −16.5 V, fSAMPLE = 250 kSPS VDD = 16.5 V, fSAMPLE = 250 kSPS AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS AD7656-1/AD7657-1/AD7658-1 AD7658-1 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; for ±4 × VREF range, VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; for ±2 × VREF range, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Delay Matching Aperture Jitter Channel-to-Channel Isolation2 Full-Power Bandwidth DC ACCURACY Resolution No Missing Codes Differential Nonlinearity Integral Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Matching2 Bipolar Zero-Scale Error2 Bipolar Zero-Scale Error Matching2 Negative Full-Scale Error2 Negative Full-Scale Error Matching2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance3 Reference Output Voltage Long-Term Stability Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 B Version 1 Y Version1 Unit 73.5 73.5 −88 −100 −97 73.5 73.5 −88 −100 −97 dB typ dB typ dB max dB typ dB typ −106 −101 10 4 35 −100 4.5 2.2 −106 −101 10 4 35 −100 4.5 2.2 dB typ dB typ ns max ns max ps typ dB typ MHz typ MHz typ 12 12 ±0.7 ±0.5 ±0.95 ±0.366 ±2 ±2 ±0.95 ±0.366 12 12 ±0.7 ±0.5 ±0.95 ±0.366 ±2 ±2 ±0.95 ±0.366 Bits Bits min LSB max LSB max % FS max % FS max LSB max LSB max % FS max % FS max Test Conditions/Comments fIN = 10 kHz sine wave fa = 10.5 kHz, fb = 9.5 kHz ±4 × VREF ±2 × VREF ±1 10 14 ±4 × VREF ±2 × VREF ±1 10 14 V V μA max pF typ pF typ 2.5 ±1 18.5 2.49/2.51 150 25 6 2.5 ±1 18.5 2.49/2.51 150 25 6 V min/max μA max pF typ V min/max ppm typ ppm/°C max ppm/°C typ 0.7 × VDRIVE 0.3 × VDRIVE ±10 10 0.7 × VDRIVE 0.3 × VDRIVE ±10 10 V min V max μA max pF max Rev. 0 | Page 7 of 32 fIN on unselected channels up to 100 kHz @ −3 dB @ −0.1 dB ±0.317% FSR typical ±0.0125% FSR typical ±0.317% FSR typical See Table 8 for minimum VDD/VSS for each range RNGx bits or RANGE pin = 0 RNGx bits or RANGE pin = 1 ±4 × VREF range when in track ±2 × VREF range when in track REFEN/DIS = 1 1000 hours Typically 10 nA, VIN = 0 V or VDRIVE AD7656-1/AD7657-1/AD7658-1 Parameter LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS AVCC DVCC VDRIVE ITOTAL 4 Normal Mode—Static Normal Mode—Operational ISS (Operational) IDD (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) B Version 1 Y Version1 Unit Test Conditions/Comments VDRIVE − 0.2 VDRIVE − 0.2 0.2 0.2 ±10 ±10 10 10 Twos complement V min V max μA max pF max ISOURCE = 200 μA ISINK = 200 μA 3.1 550 250 3.1 550 250 μs max ns max kSPS 5/15 −5/−15 5 5 3/5 5/15 −5/−15 5 5 3/5 V nom min/max V nom min/max V nom V nom V nom min/max 18 18 mA max 26 26 mA max 0.25 0.25 7 0.25 0.25 7 mA max mA max mA max 400 400 μA max 94 140 40 25 94 140 40 25 mW max mW max mW max μW max Power Dissipation Normal Mode—Static Normal Mode—Operational Partial Power-Down Mode Full Power-Down Mode (STBY Pin) 1 The temperature range for the B version is −40°C to +85°C and for the Y version is −40°C to +125°C See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC. 2 Rev. 0 | Page 8 of 32 Parallel interface mode only For the 4 × VREF range, VDD = 10 V to 16.5 V For the 4 × VREF range, VDD = −10 V to −16.5 V Digital inputs = 0 V or VDRIVE AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V VSS = −16.5 V, fSAMPLE = 250 kSPS VDD = 16.5 V, fSAMPLE = 250 kSPS AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS AD7656-1/AD7657-1/AD7658-1 TIMING SPECIFICATIONS AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. Table 4. Limit at tMIN, tMAX VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V Unit Description 3 150 3 150 μs typ ns min 550 25 60 2 25 550 25 60 2 25 ns min ns min ns min ms max μs max Conversion time, internal clock Minimum quiet time required between bus relinquish and start of next conversion Acquisition time Minimum CONVST low pulse CONVST high to BUSY high STBY rising edge to CONVST rising edge Partial power-down mode 15 0 5 5 5 15 0 5 5 5 ns min ns min ns min ns min ns min WR pulse width CS to WR setup time CS to WR hold time Data setup time before WR rising edge Data hold after WR rising edge 0 0 0 45 45 10 12 6 0 0 0 36 36 10 12 6 ns min ns min ns min ns min ns max ns min ns max ns min BUSY to RD delay CS to RD setup time CS to RD hold time RD pulse width Data access time after RD falling edge Data hold time after RD rising edge Bus relinquish time after RD rising edge Minimum time between reads 18 12 18 12 MHz max ns max t17 2 22 22 ns max t18 t19 t20 0.4 × tSCLK 0.4 × tSCLK 10 0.4 × tSCLK 0.4 × tSCLK 10 ns min ns min ns min t21 18 18 ns max Frequency of serial read clock Delay from CS until DOUTx three-state disabled Data access time after SCLK rising edge/CS falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time after SCLK falling edge CS rising edge to DOUTx high impedance Parameter 1 PARALLEL INTERFACE tCONVERT tQUIET tACQ t10 t1 tWAKE-UP PARALLEL WRITE OPERATION t11 t12 t13 t14 t15 PARALLEL READ OPERATION t2 t3 t4 t5 t6 t7 t8 t9 SERIAL INTERFACE fSCLK t16 2 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. A buffer is used on the DOUTx pins (Pin 5 to Pin 7) for this measurement. 200µA TO OUTPUT PIN IOL 1.6V CL 25pF 200µA IOH 07017-002 1 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 9 of 32 AD7656-1/AD7657-1/AD7658-1 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to AGND, DGND VSS to AGND, DGND VDD to AVCC AVCC to AGND, DGND DVCC to AVCC DVCC to DGND, AGND AGND to DGND VDRIVE to DGND Analog Input Voltage to AGND1 Digital Input Voltage to DGND Digital Output Voltage to DGND REFIN/REFOUT to AGND Input Current to Any Pin Except Supplies2 Operating Temperature Range B Version Y Version Storage Temperature Range Junction Temperature Pb/Sn Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow ESD Rating −0.3 V to +16.5 V +0.3 V to −16.5 V VCC − 0.3 V to 16.5 V −0.3 V to +7 V −0.3 V to AVCC + 0.3 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to DVCC + 0.3 V VSS − 0.3 V to VDD + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to AVCC + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a 4-layer board. Table 6. Thermal Resistance Package Type 64-Lead LQFP ±10 mA −40°C to +85°C −40°C to +125°C −65°C to +150°C 150°C ESD CAUTION 240(+0)°C 260(+0)°C 700 V 1 If the analog inputs are driven from alternative VDD and VSS supply circuitry, a 240 Ω series resistor should be placed on the analog inputs and Schottky diodes should be placed in series with the AD7656-1/AD7657-1/AD7658-1’s VDD and VSS supplies. 2 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. 0 | Page 10 of 32 θJA 45 θJC 11 Unit °C/W AD7656-1/AD7657-1/AD7658-1 64 63 62 61 60 59 58 AGND AVCC REFIN/REFOUT AGND AGND REFCAPA AGND REFCAPB AGND REFCAPC AGND AVCC SER/PAR SEL H/S SEL WR/REFEN/DIS DB15 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 DB14/REFBUF EN/DIS 1 DB13 2 48 V6 DB12 3 46 AVCC PIN 1 47 AVCC DB11 4 45 V5 DB10/DOUT C 5 44 AGND DB9/DOUT B 6 DB8/DOUT A 7 DGND 8 VDRIVE 9 43 AGND AD7656-1/AD7657-1/AD7658-1 42 V4 TOP VIEW (Not to Scale) 41 AVCC 40 AVCC DB7/HBEN/DCEN 10 39 V3 DB6/SCLK 11 38 AGND DB5/DCIN A 12 37 AGND DB4/DCIN B 13 36 V2 DB3/DCIN C 14 35 AVCC DB2/SEL C 15 34 AVCC DB1/SEL B 16 33 V1 07017-003 AGND VDD VSS W/B RESET RANGE DVCC DGND STBY CONVST A CONVST B CONVST C RD CS BUSY DB0/SEL A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 54, 56, 58 Mnemonic REFCAPA, REFCAPB, REFCAPC 33, 36, 39, 42, 45, 48 V1 to V6 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 AGND 26 DVCC 9 VDRIVE 8, 25 DGND 34, 35, 40, 41, 46, 47, 50, 60 23, 22, 21 AVCC CONVST A, CONVST B, CONVST C Description Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are connected to these pins to decouple the reference buffer for each ADC pair. Each REFCAP pin should be decoupled to AGND using a 1 μF capacitor. Analog Input 1 to Analog Input 6. These pins are single-ended analog inputs. In hardware mode, the analog input range of these channels is determined by the RANGE pin. In software mode, it is determined by the RNGC to RNGA bits of the control register (see Table 11). Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7656-1/ AD7657-1/AD7658-1. All analog input signals and external reference signals should be referred to this pin. All AGND pins should be connected to the AGND plane of the system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Digital Power, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to DGND by placing a 1 μF decoupling capacitor on the DVCC pin. Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface. Digital Ground. This is the ground reference point for all digital circuitry on the AD7656-1/AD7657-1/ AD7658-1. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Conversion Start Input A, Conversion Start Input B, and Conversion Start Input C. These logic inputs are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is used to initiate simultaneous conversions on V5 and V6. When one of these pins switches from low to high, the track-and-hold switch on the selected ADC pair switches from track to hold, and the conversion is initiated. These inputs can also be used to place the ADC pairs into partial powerdown mode. Rev. 0 | Page 11 of 32 AD7656-1/AD7657-1/AD7658-1 Pin No. 19 Mnemonic CS 20 RD 63 WR/REFEN/DIS 18 BUSY 51 REFIN/REFOUT 61 SER/PAR SEL 17 DB0/SEL A 16 DB1/SEL B 15 DB2/SEL C 14 DB3/DCIN C 13 DB4/DCIN B 12 DB5/DCIN A 11 DB6/SCLK 10 DB7/HBEN/DCEN Description Chip Select. This active low logic input frames the data transfer. If both CS and RD are logic low and the parallel interface is selected, the output bus is enabled and the conversion result is output on the parallel data bus lines. If both CS and WR are logic low and the parallel interface is selected, DB[15:8] are used to write data to the on-chip control register. When the serial interface is selected, the CS is used to frame the serial read transfer and clock out the MSB of the serial output data. Read Data. If both CS and RD are logic low and the parallel interface is selected, the output bus is enabled. When the serial interface is selected, the RD line should be held low. Write Data/Reference Enable and Disable. When the H/S SEL pin is high and both CS and WR are logic low, DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin. When H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin should be decoupled. See the Internal/External Reference section. Busy Output. This pin transitions to high when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. A new conversion should not be initiated on the AD7656-1/AD7657-1/AD7658-1 when the BUSY signal is high. Reference Input/Reference Output. The on-chip reference is available via this pin. Alternatively, the internal reference can be disabled and an external reference can be applied to this input. See the Internal/External Reference section. When the internal reference is enabled, this pin should be decoupled using at least a 1 μF decoupling capacitor. Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high, the serial interface is selected. When the serial interface is selected, DB[10:8] function as DOUT[C:A], DB[0:2] function as DOUT, and DB7 functions as DCEN. When the serial interface is selected, DB15 and DB[13:11] should be tied to DGND. Data Bit 0/Select DOUT A. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SEL A and is used to configure the serial interface. If this pin is 1, the serial interface operates with one, two, or three DOUT output pins and enables DOUT A as a serial output. When the serial interface is selected, this pin should always be set to 1. Data Bit 1/Select DOUT B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SEL B and is used to configure the serial interface. If this pin is 1, the serial interface operates with two or three DOUT output pins and enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected. Data Bit 2/Select DOUT C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SEL C and is used to configure the serial interface. If this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin. Unused serial DOUT pins should be left unconnected. Data Bit 3/Daisy-Chain Input C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When the serial interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Data Bit 4/Daisy-Chain Input B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When the serial interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Data Bit 5/Daisy-Chain Input A. When SER/PAR SEL is low, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When the serial interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Data Bit 6/Serial Clock. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin functions as SCLK input and is the read serial clock for the serial transfer. Data Bit 7/High Byte Enable/Daisy-Chain Enable. When the parallel interface is selected and the device is used in word mode (SER/PAR SEL = 0 and W/B = 0), this pin functions as Data Bit 7. When the parallel interface is selected and the device is used in byte mode (SER/PAR SEL = 0 and W/B = 1), this pin functions as HBEN. If the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. If the HBEN pin is logic low, the data is output LSB byte first on DB[15:8]. When the serial interface is selected (SER/PAR SEL = 1), this pin functions as DCEN. If the DCEN pin is logic high, the parts operate in daisy-chain mode with DB[5:3] functioning as DCIN[A:C]. When the serial interface is selected but the device is not used in daisy-chain mode, this pin should be tied to DGND. Rev. 0 | Page 12 of 32 AD7656-1/AD7657-1/AD7658-1 Pin No. 7 Mnemonic DB8/DOUT A 6 DB9/DOUT B 5 DB10/DOUT C 4 DB11 3, 2, 64 DB12, DB13, DB15 1 DB14/REFBUFEN/DIS 28 RESET 27 RANGE 31 30 24 VDD VSS STBY 62 H/S SEL 29 W/B Description Data Bit 8/Serial Data Output A. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL A = 1, this pin functions as DOUT A and outputs serial conversion data. Data Bit 9/Serial Data Output B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL B = 1, this pin functions as DOUT B and outputs serial conversion data. This configures the serial interface to have two DOUT output lines. Data Bit 10/Serial Data Output C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1 and SEL C = 1, this pin functions as DOUT C and outputs serial conversion data. This configures the serial interface to have three DOUT output lines. Data Bit 11/Digital Ground. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR SEL = 1, this pin should be tied to DGND. Data Bit 12, Data Bit 13, Data Bit 15. When SER/PAR SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output the conversion result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR SEL = 1, these pins should be tied to DGND. For the AD7657-1, DB15 contains a leading 0. For the AD7658-1, DB15, DB13, and DB12 contain leading 0s. Data Bit 14/Reference Buffer Enable and Disable. When SER/PAR SEL = 0, this pin acts as a threestate digital input/output pin. For the AD7657-1 and AD7658-1, DB14 contains a leading 0. When SER/PAR SEL = 1, this pin can be used to enable or disable the internal reference buffers. Reset Input. When set to logic high, this pin resets the AD7656-1/AD7657-1/AD7658-1. In software mode, the current conversion is aborted and the internal register is set to all 0s. In hardware mode, the AD7656-1/AD7657-1/AD7658-1 are configured depending on the logic levels on the hardware select pins. In all modes, the parts should receive a RESET pulse after power-up. The RESET high pulse should be typically 100 ns wide. After the RESET pulse, the AD7656-1/AD7657-1/AD7658-1 need to see a valid CONVST pulse to initiate a conversion; this should consist of a high-to-low CONVST edge followed by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse. In hardware mode, the user can initiate a RESET pulse between conversion cycles, that is, a 100 ns RESET pulse can be applied to the device after BUSY has transitioned from high to low and the data has been read. The RESET can then be used prior to the next CONVST pulse. Ensure that in such a case RESET is logic low prior to the next CONVST pulse. Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is determined by the RNGA, RNGB, and RNGC bits in the control register. Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is high for normal operation and low for standby operation. Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656-1/AD7657-1/AD7658-1 operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the control register. When the serial interface is selected, CONVST A is used to initiate conversions on the selected ADC pairs. Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656-1/ AD7657-1/AD7658-1 using the parallel data lines DB[15:0]. When this pin is logic high and the parallel interface is selected, byte mode is enabled. In this mode, data is transferred using Data Lines DB[15:8], and DB[7] function as HBEN. To obtain the 16-bit conversion result, 2-byte reads are required. When the serial interface is selected, this pin should be tied to DGND. Rev. 0 | Page 13 of 32 AD7656-1/AD7657-1/AD7658-1 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 0 –40 –60 –80 1.0 DNL (LSB) –20 –100 –120 0 –0.5 –1.0 –140 –1.5 07017-004 –160 –180 0.5 0 20 40 60 80 100 –2.0 120 07017-007 AMPLITUDE (dB) VDD/VSS = ±12V TA = –40°C AVCC/DVCC/VDRIVE = 5V DNL WCP = 0.61LSB 1.5 f = 250kSPS DNL WCN = –0.82LSB SAMPLE 2 × VREF RANGE VDD/VSS = ±15V AVCC/DVCC/VDRIVE = 5V ±10V RANGE INTERNAL REFERENCE TA = 25°C fSAMPLE = 250kSPS fIN = 10kHz SNR = 88.44dB SINAD = 88.43dB THD = –111.66dB 0 10k 20k Figure 4. AD7656-1 FFT for ±5 V Range (VDD/VSS = ±15 V) 0 2.0 –60 –80 1.2 –120 0.4 0 –0.4 –0.8 –140 07017-005 0 20 40 60 80 100 07017-008 –1.2 –160 –1.6 –2.0 120 0 2000 4000 6000 Figure 5. AD7656-1 FFT for ±5 V Range (VDD/VSS = ±12 V) 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 20k 30k 40k 50k –2.0 60k 65535 07017-009 DNL (LSB) VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V 1.5 f SAMPLE = 250kSPS ±5V RANGE 07017-006 INL (LSB) 2.0 VDD/VSS = ±12V TA = –40°C AVCC/DVCC/VDRIVE = 5V INL WCP = 0.97LSB 1.5 fSAMPLE = 250kSPS INL WCN = –0.72LSB 2 × VREF RANGE 10k 10000 12000 14000 16000 Figure 8. AD7657-1 Typical INL 2.0 0 8000 CODE FREQUENCY (kHz) –2.0 60k 65535 0.8 –100 –180 50k VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V fSAMPLE = 250kSPS ±5V RANGE 1.6 INL (LSB) AMPLITUDE (dB) –40 40k Figure 7. AD7656-1 Typical DNL VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V ±5V RANGE INTERNAL REFERENCE TA = 25°C fSAMPLE = 250kSPS fIN = 10kHz SNR = 88.25dB SINAD = 88.24dB THD = –112.46dB –20 30k CODE FREQUENCY (kHz) 0 2000 4000 6000 8000 10000 12000 14000 16000 ADC CODE CODE Figure 6. AD7656-1 Typical INL Figure 9. AD7657-1 Typical DNL Rev. 0 | Page 14 of 32 AD7656-1/AD7657-1/AD7658-1 1.0 –80 VDD/VSS = ±12V 0.8 AVCC/DVCC/VDRIVE = 5V fSAMPLE = 250kSPS 0.6 ±5V RANGE –90 0.4 0.2 THD (dB) INL (LSB) fSAMPLE = 250kSPS TA = 25°C INTERNAL REFERENCE –85 0 –0.2 –0.4 –95 ±10V RANGE VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V –100 –105 –0.6 0 500 1000 1500 2000 2500 3000 3500 –115 10 4000 CODE Figure 13. AD7656-1 THD vs. Analog Input Frequency –80 VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V fSAMPLE = 250kSPS ±5V RANGE 0.8 0.6 –90 0.4 0.2 THD (dB) DNL (LSB) 100 ANALOG INPUT FREQUENCY (kHz) Figure 10. AD7658-1 Typical INL 1.0 ±5V RANGE VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V 07017-013 –1.0 –110 07017-010 –0.8 0 –0.2 VDD/VSS = ±16.5V AVCC/DVCC/VDRIVE = 5.25V TA = 25°C INTERNAL REFERENCE ±4 × VREF RANGE RSOURCE = 1000Ω RSOURCE = 220Ω –100 RSOURCE = 50Ω –0.4 –110 –0.6 –1.0 0 500 1000 1500 2000 2500 3000 3500 –120 10 4000 CODE 87 86 –80 ±10V RANGE VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V –85 –90 ±5V RANGE VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V 85 –95 VDD/VSS = ±12V AVCC/DVCC/VDRIVE = 5V TA = 25°C INTERNAL REFERENCE ±2 × VREF RANGE RSOURCE = 1000Ω –100 –105 RSOURCE = 220Ω RSOURCE = 100Ω 84 –110 83 10 –115 10 100 ANALOG INPUT FREQUENCY (kHz) Figure 12. AD7656-1 SINAD vs. Analog Input Frequency RSOURCE = 10Ω 07017-015 RSOURCE = 50Ω 07017-012 SINAD (dB) 88 Figure 14. AD7656-1 THD vs. Analog Input Frequency for Various Source Impedances, ±4 × VREF Range THD (dB) 89 fSAMPLE = 250kSPS TA = 25°C INTERNAL REFERENCE 100 ANALOG INPUT FREQUENCY (kHz) Figure 11. AD7658-1 Typical DNL 90 07017-014 07017-011 –0.8 RSOURCE = 100Ω RSOURCE = 10Ω 100 ANALOG INPUT FREQUENCY (kHz) Figure 15. AD7656-1 THD vs. Analog Input Frequency for Various Source Impedances, ±2 × VREF Range Rev. 0 | Page 15 of 32 AD7656-1/AD7657-1/AD7658-1 2.510 2.508 100 AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V fSAMPLE = 250kSPS ±2 × VREF RANGE INTERNAL REFERENCE TA = 25°C fIN = 10kHz 100nF ON VDD AND VSS 80 2.504 PSRR (dB) REFERENCE VOLTAGE (V) 90 2.506 2.502 2.500 2.498 70 VSS 60 VDD 2.496 07017-016 2.492 –55 –35 –15 5 25 45 65 85 105 40 30 125 07017-019 50 2.494 80 130 Figure 16. Reference Voltage vs. Temperature 3.20 89 330 380 430 530 480 ±10V RANGE AVCC/DVCC/VDRIVE = 5.25V VDD/VSS = ±16.5V 3.05 3.00 SNR (dB) 2.95 2.90 88 ±5V RANGE AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V 87 2.85 2.80 07017-017 2.70 –55 fSAMPLE = 250kSPS fIN = 10kHz –35 –15 5 25 45 65 85 105 85 –40 125 INTERNAL REFERENCE –20 0 20 TEMPERATURE (°C) –90 3212 VDD/VSS = ±15V AVCC/DVCC/VDRIVE = 5V INTERNAL REFERENCE 8192 SAMPLES 2500 80 100 120 140 Figure 20. AD7656-1 SNR vs. Temperature 3500 2806 60 TEMPERATURE (°C) Figure 17. Conversion Time vs. Temperature 3000 40 07017-020 86 2.75 fSAMPLE = 250kSPS fIN = 10kHz –95 INTERNAL REFERENCE –100 THD (dB) 2000 1532 1500 ±5V RANGE AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V –105 –110 1000 168 57 –4 –3 –2 –1 0 1 25 0 2 3 07017-018 0 0 –5 ±10V RANGE AVCC/DVCC/VDRIVE = 5.25V VDD/VSS = ±16.5V –115 392 500 –120 –60 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) CODE Figure 18. AD7656-1 Histogram of Codes Figure 21. AD7656-1 THD vs. Temperature Rev. 0 | Page 16 of 32 120 07017-021 CONVERSION TIME (µs) 280 90 3.10 NUMBER OF OCCURRENCES 230 Figure 19. PSRR vs. Supply Ripple Frequency AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V 3.15 180 SUPPLY RIPPLE FREQUENCY (kHz) TEMPERATURE (°C) 140 AD7656-1/AD7657-1/AD7658-1 95 90 110 85 90 80 60 0 20 40 60 80 100 120 140 Figure 22. Channel-to-Channel Isolation vs. Frequency of Input Noise 22 ±5V RANGE ±10V RANGE 16 14 AVCC/DVCC/VDRIVE = 5V fSAMPLE = 250kSPS FOR ±5V RANGE VDD/VSS = ±12V FOR ±10V RANGE VDD/VSS = ±16.5V 10 –40 –20 0 20 40 60 07017-023 DYNAMIC CURRENT (mA) 18 12 fSAMPLE = 250kSPS ±2 × VREF RANGE INTERNAL REFERENCE TA = 25°C fIN = 10kHz 1µF ON AVCC SUPPLY PIN ±100mV SUPPLY RIPPLE AMPLITUDE 80 65 60 30 70 110 150 190 230 SUPPLY RIPPLE FREQUENCY (kHz) FREQUENCY OF INPUT NOISE (kHz) 20 75 70 AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE ±2 × VREF RANGE 30kHz ON SELECTED CHANNEL 70 80 100 120 TEMPERATURE (°C) Figure 23. Dynamic Current vs. Temperature Rev. 0 | Page 17 of 32 Figure 24. PSRR vs. Supply Ripple Frequency for AVCC Supply 07017-036 PSRR (dB) 100 07017-022 CHANNEL-TO-CHANNEL ISOLATION (dB) 120 AD7656-1/AD7657-1/AD7658-1 TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at a ½ LSB below the first code transition and full scale at ½ LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Scale Error The deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, that is, AGND − 1 LSB. Bipolar Zero Scale Error Matching The difference in bipolar zero code error between any two input channels. Positive Full-Scale Error The deviation of the last code transition (011 … 110 to 011 … 111) from the ideal (+4 × VREF − 1 LSB, +2 × VREF − 1 LSB) after adjusting for the bipolar zero scale error. Positive Full-Scale Error Matching The difference in positive full-scale error between any two input channels. Negative Full-Scale Error The deviation of the first code transition (10 … 000 to 10 … 001) from the ideal (−4 × VREF + 1 LSB, −2 × VREF + 1 LSB) after adjusting for the bipolar zero scale error. Negative Full-Scale Error Matching The difference in negative full-scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of the conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Track-and-Hold section for more details. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) (SINAD) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fSAMPLE/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02 N + 1.76) dB Therefore, SINAD is 98 dB for a 16-bit converter, 86.04 dB for a 14-bit converter, and 74 dB for a 12-bit converter. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7656-1/AD7657-1/AD7658-1, it is defined as THD (dB) = 20 log V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fSAMPLE/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at the sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7656-1/AD7657-1/AD7658-1 are tested using the CCIF standard in which two input frequencies near the maximum input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals and is expressed in decibels. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 30 kHz signal. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. See the Typical Performance Characteristics section. Rev. 0 | Page 18 of 32 AD7656-1/AD7657-1/AD7658-1 Figure 19 shows the power supply rejection ratio vs. supply ripple frequency for the AD7656-1/AD7657-1/AD7658-1. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC’s VDD and VSS supplies at a frequency sampled, fSAMPLE: PSRR (dB) = 10 log(Pf/PfS) where: Pf is equal to the power at frequency f in the ADC output. PfS is equal to the power at frequency fSAMPLE coupled onto the VDD and VSS supplies. Rev. 0 | Page 19 of 32 AD7656-1/AD7657-1/AD7658-1 THEORY OF OPERATION CONVERTER DETAILS Analog Input The AD7656-1/AD7657-1/AD7658-1 are pin- and softwarecompatible, reduced decoupling versions of the AD7656/AD7657/ AD7658 devices. In addition, the AD7656-1/AD7657-1/AD7658-1 are high speed, low power converters that allow the simultaneous sampling of six on-chip ADCs. The analog inputs on the AD7656-1/ AD7657-1/AD7658-1 can accept true bipolar input signals. The RANGE pin or RNGx bits are used to select either ±4 × VREF or ±2 × VREF as the input range for the next conversion. The AD7656-1/AD7657-1/AD7658-1 can handle true bipolar input voltages. The logic level on the RANGE pin or the value written to the RNGx bits in the control register determines the analog input range on the AD7656-1/AD7657-1/AD7658-1 for the next conversion. When the RANGE pin or RNGx bits are 1, the analog input range for the next conversion is ±2 × VREF. When the RANGE pin or RNGx bits are 0, the analog input range for the next conversion is ±4 × VREF. A conversion is initiated on the AD7656-1/AD7657-1/AD7658-1 by pulsing the CONVST input. On the rising edge of CONVST, the track-and-hold amplifier of the selected ADC pair is placed into hold mode and the conversions are started. After the rising edge of CONVST, the BUSY signal goes high to indicate that the conversion is taking place. The conversion clock for the AD7656-1/ AD7657-1/AD7658-1 is internally generated, and the conversion time for the parts is 3 μs. The BUSY signal returns low to indicate the end of a conversion. On the falling edge of BUSY, the trackand-hold amplifier returns to track mode. Data can be read from the output register via the parallel or serial interface. Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7656-1/AD7657-1/ AD7658-1 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 16-/14-/12-bit resolution, respectively. The input bandwidth of the track-and-hold amplifiers is greater than the Nyquist rate of the ADC, even when the AD7656-1/AD7657-1/AD7658-1 are operating at the maximum throughput rate. The parts can handle input frequencies of up to 4.5 MHz. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST. The aperture time (that is, the delay time between the external CONVST signal actually going into hold) for the track-and-hold amplifier is 10 ns. This is well matched across all six track-and-hold amplifiers on one device and from device to device. This allows more than six ADCs to be sampled simultaneously. The end of the conversion is signaled by the falling edge of BUSY, and it is at this point that the trackand-hold amplifiers return to track mode and the acquisition time begins. VDD D1 V1 C1 R1 C2 D2 07017-024 Each AD7656-1/AD7657-1/AD7658-1 contains six SAR ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference, reference buffers, and high speed parallel and serial interfaces. The parts allow the simultaneous sampling of all six ADCs when the three CONVST pins (CONVST A, CONVST B, and CONVST C) are tied together. Alternatively, the six ADCs can be grouped into three pairs. Each pair has an associated CONVST signal used to initiate simultaneous sampling on each ADC pair, on four ADCs, or on all six ADCs. CONVST A is used to initiate simultaneous sampling on V1 and V2, CONVST B is used to initiate simultaneous sampling on V3 and V4, and CONVST C is used to initiate simultaneous sampling on V5 and V6. VSS Figure 25. Equivalent Analog Input Structure Figure 25 shows an equivalent circuit of the analog input structure of the AD7656-1/AD7657-1/AD7658-1. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the VDD and VSS supply rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward-biased and to start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the parts is 10 mA. Capacitor C1 in Figure 25 is typically about 4 pF and can be attributed primarily to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch (that is, a track-and-hold switch). This resistor is typically about 3.5 kΩ. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 10 pF typically. The AD7656-1/AD7657-1/AD7658-1 require VDD and VSS dual supplies for the high voltage analog input structures. These supplies must be equal to or greater than the analog input range (see Table 8 for the requirements on these supplies for each analog input range). The AD7656-1/AD7657-1/AD7658-1 require a low voltage AVCC supply of 4.75 V to 5.25 V to power the ADC core, a DVCC supply of 4.75 V to 5.25 V for the digital power, and a VDRIVE supply of 2.7 V to 5.25 V for the interface power. To meet the specified performance when using the minimum supply voltage for the selected analog input range, it may be necessary to reduce the throughput rate from the maximum throughput rate. Table 8. Minimum VDD/VSS Supply Voltage Requirements Analog Input Range (V) ±4 × VREF ±2 × VREF Rev. 0 | Page 20 of 32 Reference Voltage (V) 2.5 2.5 Full-Scale Input (V) ±10 ±5 Minimum VDD/VSS (V) ±10 ±5 AD7656-1/AD7657-1/AD7658-1 ADC TRANSFER FUNCTION The output coding of the AD7656-1/AD7657-1/AD7658-1 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/65,536 for the AD7656-1, FSR/16,384 for the AD7657-1, and FSR/4096 for the AD7658-1. The ideal transfer characteristic is shown in Figure 26. ADC CODE 011 ... 111 011 ... 110 000 ... 001 000 ... 000 111 ... 111 100 ... 010 100 ... 001 100 ... 000 the control register to set DB9 of the register to 1. For the internal reference mode, the REFIN/REFOUT pin should be decoupled using a 1 μF capacitor. The AD7656-1/AD7657-1/AD7658-1 each contain three onchip reference buffers. Each of the three ADC pairs has an associated reference buffer. These reference buffers require external decoupling capacitors, using 1 μF capacitors, on the REFCAPA, REFCAPB, and REFCAPC pins. The internal reference buffers can be disabled in software mode by writing to Bit DB8 in the internal control register. If serial interface is selected, the internal reference buffers can be disabled in hardware mode by setting the DB14/REFBUFEN/DIS pin high. If the internal reference and its buffers are disabled, an external buffered reference should be applied to the REFCAPx pins. –FSR/2 + 1/2LSB AGND – 1LSB +FSR/2 – 3/2LSB ANALOG INPUT 07017-025 TYPICAL CONNECTION DIAGRAM Figure 26. AD7656-1/AD7657-1/AD7658-1 Transfer Characteristic The LSB size is dependent on the analog input range selected (see Table 9). INTERNAL/EXTERNAL REFERENCE The REFIN/REFOUT pin allows access to the 2.5 V reference of the AD7656-1/AD7657-1/AD7658-1, or it allows an external reference to be connected to provide the reference source for conversions. The AD7656-1/AD7657-1/AD7658-1 can each accommodate a 2.5 V external reference range. When using an external reference, the internal reference must be disabled. After a reset, the AD7656-1/ AD7657-1/AD7658-1 default to operating in external reference mode with the internal reference buffers enabled. The internal reference can be enabled in either hardware or software mode. To enable the internal reference in hardware mode, set the H/S SEL pin to 0 and the REFEN/DIS pin to 1. To enable the internal reference in software mode, set H/S SEL to 1 and write to Figure 27 shows the typical connection diagram for the AD7656-1/ AD7657-1/AD7658-1, illustrating the reduction in the number and value of decoupling capacitors required. There are eight AVCC supply pins on each part. The AVCC supplies are the supplies used for the AD7656-1/AD7657-1/AD7658-1 conversion process; therefore, they should be well decoupled. The AVCC supply which is applied to eight AVCC pins can be decoupled using just one 1 μF capacitor The AD7656-1/AD7657-1/AD7658-1 can operate with the internal reference or an externally applied reference. In this configuration, the parts are configured to operate with the external reference. The REFIN/REFOUT pin is decoupled with a 1 μF capacitor. The three internal reference buffers are enabled. Each of the REFCAPx pins is decoupled with a 1 μF capacitor. If the same supply is being used for the AVCC and DVCC supplies, a ferrite or small RC filter should be placed between the supply pins. AGND pins are connected to the AGND plane of the system. The DGND pins are connected to the digital ground plane in the system. The AGND and DGND planes should be connected together at one place in the system. This connection should be as close as possible to the AD7656-1/AD7657-1/AD7658-1 in the system. Table 9. LSB Size for Each Analog Input Range Parameter LSB Size FS Range Input Range for AD7656-1 ±10 V ±5 V 0.305 mV 0.152 mV 20 V/65,536 10 V/65,536 Input Range for AD7657-1 ±10 V ±5 V 1.22 mV 0.610 mV 20 V/16,384 10 V/16,384 Rev. 0 | Page 21 of 32 Input Range for AD7658-1 ±10 V ±5 V 4.88 mV 2.44 mV 20 V/4096 10 V/4096 AD7656-1/AD7657-1/AD7658-1 DVCC ANALOG SUPPLY VOLTAGE 5V 1µF +9.5V TO +16.5V SUPPLY 1µF + + 1µF AGND AVCC VDD + DVCC DGND 2.5V REF 1µF AGND REFIN/OUT + 1µF AD7656-1/ AD7657-1/ AD7658-1 CONVST A, B, C µP/µC/DSP SCHMITT 1 TRIGGER SER/PAR H/S W/B RANGE VSS AGND 1 PARALLEL INTERFACE RESET CS RD BUSY AGND + 1µF VDRIVE DGND REFCAPA, B, C + SIX ANALOG INPUTS –9.5V TO –16.5V SUPPLY + D0 TO D15 AGND 1µF DIGITAL SUPPLY VOLTAGE +3V OR +5V STBY VDRIVE See Applications Hints Section Figure 27. Typical Connection Diagram The VDRIVE supply is connected to the same supply as the processor. The voltage on VDRIVE controls the voltage value of the output logic signals. The VDD and VSS signals should be decoupled with a minimum 1 μF decoupling capacitor. These supplies are used for the high voltage analog input structures on the AD7656-1/AD7657-1/AD7658-1 analog inputs. DRIVING THE ANALOG INPUTS Together, the driver amplifier and the analog input circuit used for the AD7656-1 must settle for a full-scale step input to a 16-bit level (0.0015%), which is within the specified 550 ns acquisition time of the AD7656-1. The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7656-1. In addition, the driver also needs to have a THD performance suitable for the AD7656-1. The AD8021 meets these requirements. The AD8021 needs an external compensation capacitor of 10 pF. If a dual version of the AD8021 is required, the AD8022 can be used. The AD8610 and the AD797 can also be used to drive the AD7656-1/AD7657-1/ AD7658-1. INTERFACE OPTIONS The AD7656-1/AD7657-1/AD7658-1 provide two interface options: a high speed parallel interface and a high speed serial interface. The required interface mode is selected via the SER/PAR SEL pin. The parallel interface can operate in word (W/B = 0) or byte (W/B = 1) mode. When in serial mode, the AD7656-1/AD7657-1/AD7658-1 can be configured into daisychain mode. Parallel Interface (SER/PAR SEL = 0) The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/ 12-bit ADCs, respectively. A simultaneous sample of all six ADCs can be performed by connecting all three CONVST pins (CONVST A, CONVST B, and CONVST C) together. The AD7656-1/AD7657-1/AD7658-1 need to see a CONVST pulse to initiate a conversion; this should consist of a falling CONVST edge followed by a rising CONVST edge. The rising edge of CONVST initiates simultaneous conversions on the selected ADCs. The AD7656-1/AD7657-1/AD7658-1 each contain an on-chip oscillator that is used to perform the conversions. The conversion time, tCONV, is 3 μs. The BUSY signal goes low to indicate the end of a conversion. The falling edge of the BUSY signal is used to place the track-and-hold amplifier into track mode. The AD7656-1/AD7657-1/AD7658-1 also allow the six ADCs to be converted simultaneously in pairs by pulsing the three CONVST pins independently. CONVST A is used to initiate simultaneous conversions on V1 and V2, CONVST B is used to initiate simultaneous conversions on V3 and V4, and CONVST C is used to initiate simultaneous conversions on V5 and V6. The conversion results from the simultaneously sampled ADCs are stored in the output data registers. Data can be read from the AD7656-1/AD7657-1/AD7658-1 via the parallel data bus with standard CS and RD signals (W/B = 0). To read the data over the parallel bus, SER/PAR SEL should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines DB0 to DB15 leave their high impedance state when both CS and RD are logic low. Rev. 0 | Page 22 of 32 AD7656-1/AD7657-1/AD7658-1 may affect the performance of the conversion. For the specified performance, it is recommended to perform the read after the conversion. For unused input channel pairs, the associated CONVST pin should be tied to VDRIVE. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results. A read operation can take place after the BUSY signal goes low. The number of required read operations depends on the number of ADCs that are simultaneously sampled (see Figure 28). If CONVST A and CONVST B are simultaneously brought low, four read operations are required to obtain the conversion results from V1, V2, V3, and V4. If CONVST A and CONVST C are simultaneously brought low, four read operations are required to obtain the conversion results from V1, V2, V5, and V6. The conversion results are output in ascending order. For the AD7657-1, DB15 and DB14 contain two leading 0s, and DB[13:0] output the 14-bit conversion result. For the AD7658-1, DB[15:12] contain four leading 0s, and DB[11:0] output the 12-bit conversion result. If there is only an 8-bit bus available, the AD7656-1/AD7657-1/ AD7658-1 parallel interface can be configured to operate in byte mode (W/B = 1). In this configuration, the DB7/HBEN/DCEN pin takes on its HBEN function. Each channel conversion result from the AD7656-1/AD7657-1/AD7658-1 can be accessed in two read operations, with eight bits of data provided on DB15 to DB8 for each of the read operations (see Figure 29). The HBEN pin determines whether the read operation first accesses the high byte or the low byte of the 16-bit conversion result. To always access the low byte first on DB15 to DB8, the HBEN pin should be tied low. To always access the high byte first on DB15 to DB8, the HBEN pin should be tied high. In byte mode when all three CONVST pins are pulsed together to initiate simultaneous conversions on all six ADCs, 12 read operations are necessary to read back the six 16-/14-/12-bit conversion results. DB[6:0] should be left unconnected in byte mode. When using the three CONVST signals to independently initiate conversions on the three ADC pairs, care should be taken to ensure that a conversion is not initiated on a channel pair when the BUSY signal is high. It is also recommended not to initiate a conversion during a read sequence because doing so CONVST A, CONVST B, CONVST C t10 tCONV tACQ BUSY t4 CS t3 t5 t9 t2 DATA t7 t6 V1 V2 V3 V4 t8 V5 tQUIET 07017-027 RD V6 Figure 28. Parallel Interface Timing Diagram (W/B = 0) CS t4 t3 t5 t6 DB15 TO DB8 t8 t7 LOW BYTE HIGH BYTE Figure 29. Parallel Interface—Read Cycle for Byte Mode of Operation. (W/B = 1, HBEN = 0) Rev. 0 | Page 23 of 32 07017-028 RD t9 AD7656-1/AD7657-1/AD7658-1 Software Selection of ADCs Table 11. Control Register Bit Function Descriptions The H/S SEL pin determines the source of the combination of ADCs that are to be simultaneously sampled. When the H/S SEL pin is logic low, the combination of channels to be simultaneously sampled is determined by the CONVST A, CONVST B, and CONVST C pins. When the H/S SEL pin is logic high, the combination of channels selected for simultaneous sampling is determined by the contents of the DB15 to DB13 control registers. In this mode, a write to the control register is necessary. Bit DB15 Mnemonic VC DB14 VB DB13 VA DB12 RNGC DB11 RNGB DB10 RNGA DB9 REFEN DB8 REFBUF The control register is an 8-bit write-only register. Data is written to this register using the CS and WR pins and the DB[15:8] data pins (see Figure 30). The control register is detailed in Table 10 and Table 11. To select an ADC pair to be simultaneously sampled, set the corresponding data line high during the write operation. CS WR t12 t13 t11 t15 DB15 TO DB8 07017-029 t14 DATA Figure 30. Parallel Interface—Write Cycle for Word Mode (W/B = 0) The AD7656-1/AD7657-1/AD7658-1 control register allows individual ranges to be programmed on each ADC pair. DB12 to DB10 in the control register are used to program the range on each ADC pair. After a reset occurs on the AD7656-1/AD7657-1/AD7658-1, the control register contains all 0s. The CONVST A signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register. The CONVST B and CONVST C signals can be tied low when operating in software mode (H/S SEL = 1). The number of read pulses required depends on the number of ADCs selected in the control register and on whether the devices are operating in word or byte mode. The conversion results are output in ascending order. During the write operation, Data Bus Bit DB15 to Data Bus Bit DB8 are bidirectional and become inputs to the control register when RD is logic high and CS and WR are logic low. The logic state on DB15 through DB8 is latched into the control register when WR goes logic high. Table 10. Control Register Bit Map1 DB15 VC 1 DB14 VB DB13 VA DB12 RNGC DB11 RNGB DB10 RNGA DB9 REFEN DB8 REFBUF Default All 0s. Rev. 0 | Page 24 of 32 Description This bit is used to select the V5 and V6 analog inputs for the next conversion. When this bit is set to 1, V5 and V6 are simultaneously converted on the next CONVST A rising edge. This bit is used to select the V3 and V4 analog inputs for the next conversion. When this bit is set to 1, V3 and V4 are simultaneously converted on the next CONVST A rising edge. This bit is used to select the V1 and V2 analog inputs for the next conversion. When this bit is set to 1, V1 and V2 are simultaneously converted on the next CONVST A rising edge. This bit is used to select the analog input range for the V5 and V6 analog inputs. When this bit is set to 1, the ±2 × VREF range is selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion. This bit is used to select the analog input range for the V3 and V4 analog inputs. When this bit is set to 1, the ±2 × VREF range is selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion. This bit is used to select the analog input range for the V1 and V2 analog inputs. When this bit is set to 1, the ±2 × VREF range is selected for the next conversion. When this bit is set to 0, the ±4 × VREF range is selected for the next conversion. This bit is used to select the internal reference or an external reference. When this bit is set to 0, the external reference mode is selected. When this bit is set to 1, the internal reference is selected. This bit is used to select between using the internal reference buffers and choosing to bypass these reference buffers. When this bit is set to 0, the internal reference buffers are enabled and decoupling is required on the REFCAPx pins. When this bit is set to 1, the internal reference buffers are disabled and a buffered reference should be applied to the REFCAPx pins. AD7656-1/AD7657-1/AD7658-1 Changing the Analog Input Range (H/S SEL = 0) The AD7656-1/AD7657-1/AD7658-1 RANGE pin allows the user to select either ±2 × VREF or ±4 × VREF as the analog input range for the six analog inputs. When the H/S SEL pin is low, the logic state of the RANGE pin is sampled on the falling edge of the BUSY signal to determine the range for the next simultaneous conversion. When the RANGE pin is logic high at the falling edge of the BUSY signal, the range for the next conversion is ±2 × VREF. When the RANGE pin is logic low at the falling edge of the BUSY signal, the range for the next conversion is ±4 × VREF. After a RESET pulse, the range is updated on the first falling BUSY edge. Changing the Analog Input Range (H/S SEL = 1) When the H/S SEL pin is high, the range can be changed by writing to the control register. DB[12:10] in the control register are used to select the analog input ranges for the next conversion. Each analog input pair has an associated range bit, allowing independent ranges to be programmed on each ADC pair. When the RNGx bit is set to 1, the range for the next conversion is ±2 × VREF. When the RNGx bit is set to 0, the range for the next conversion is ±4 × VREF. Serial Interface (SER/PAR SEL = 1) By pulsing one, two, or all three CONVST signals, the AD7656-1/ AD7657-1/AD7658-1 use their on-chip trimmed oscillator to simultaneously convert the selected channel pairs on the rising edge of CONVST. After the rising edge of CONVST, the BUSY signal goes high to indicate that the conversion has started. It returns low when the conversion is complete, 3 μs later. The output register is loaded with the new conversion results, and data can be read from the AD7656-1/AD7657-1/AD7658-1. To read the data back from the parts over the serial interface, SER/PAR SEL should be tied high. The CS and SCLK signals are used to transfer data from the AD7656-1/AD7657-1/AD7658-1. The parts have three DOUT pins: DOUT A, DOUT B, and DOUT C. Data can be read back from each part using one, two, or all three DOUT lines. Figure 31 shows six simultaneous conversions and the read sequence using three DOUT lines. Also in Figure 31, 32 SCLK transfers are used to access data from the AD7656-1/AD7657-1/ AD7658-1; however, two 16-SCLK individually framed transfers with the CS signal can also be used to access the data on the three DOUT lines. When the serial interface is selected and conversion data is clocking out on all three DOUT lines, DB0/SEL A, DB1/SEL B, and DB2/SEL C should be tied to VDRIVE. These pins are used to enable the DOUT A to DOUT C lines, respectively. If it is required to clock conversion data out on two data output lines, DOUT A and DOUT B should be used. To enable DOUT A and DOUT B, DB0/SEL A and DB1/SEL B should be tied to VDRIVE, and DB2/SEL C should be tied low. When six simultaneous conversions are performed and only two DOUT lines are used, a 48 SCLK transfer can be used to access the data from the AD7656-1/AD7657-1/AD7658-1. The read sequence is shown in Figure 32 for a simultaneous conversion on all six ADCs using two DOUT lines. If a simultaneous conversion occurred on all six ADCs, and only two DOUT lines are used to read the results from the AD7656-1/AD7657-1/AD7658-1. DOUT A clocks out the result from V1, V2, and V5, whereas DOUT B clocks out the results from V3, V4, and V6. Data can also be clocked out using just one DOUT line, in which case DOUT A should be used to access the conversion data. To configure the AD7656-1/AD7657-1/AD7658-1 to operate in this mode, DB0/SEL A should be tied to VDRIVE, and DB1/SEL B and DB2/SEL C should be tied low. The disadvantage of using only one DOUT line is that the throughput rate is reduced. Data can be accessed from the AD7656-1/AD7657-1/AD7658-1 using one 96 SCLK transfer, three 32-SCLK individually framed transfers, or six 16-SCLK individually framed transfers. When using the serial interface, the RD signal should be tied low and the unused DOUT line(s) should be left unconnected. Serial Read Operation Figure 33 shows the timing diagram for reading data from the AD7656-1/AD7657-1/AD7658-1 when the serial interface is selected. The SCLK input signal provides the clock source for the serial interface. The CS signal goes low to access data from the AD7656-1/AD7657-1/AD7658-1. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. The ADCs output 16 bits for each conversion result; the data stream of the AD7656-1 consists of 16 bits of conversion data, provided MSB first. The data stream for the AD7657-1 consists of two leading 0s followed by 14 bits of conversion data, provided MSB first. The data stream for the AD7658-1 consists of four leading 0s and 12 bits of conversion data, provided MSB first. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The subsequent 15 data bits are clocked out on the rising edge of the SCLK signal. Data is valid on the SCLK falling edge. To access each conversion result, 16 clock pulses must be provided to the AD7656-1/AD7657-1/ AD7658-1. Figure 33 shows how a 16-SCLK read is used to access the conversion results. Rev. 0 | Page 25 of 32 AD7656-1/AD7657-1/AD7658-1 CONVST A, CONVST B, CONVST C tCONV tACQ BUSY CS 16 32 SCLK V1 V2 DOUT B V3 V4 DOUT C V5 V6 07017-030 tQUIET DOUT A Figure 31. Serial Interface with Three DOUT Lines CS 48 DOUT A V1 V2 V5 DOUT B V3 V4 V6 07017-031 SCLK Figure 32. Serial Interface with Two DOUT Lines t1 t2 BUSY ACQUISITION t10 tACQ tCONV CONVERSION ACQUISITION tQUIET CS SCLK DOUT A, DOUT B, DOUT C t19 t16 t18 t17 DB15 t20 DB14 DB13 Figure 33. Serial Read Operation Rev. 0 | Page 26 of 32 DB1 DB0 t21 07017-032 CONVST A, CONVST B, CONVST C AD7656-1/AD7657-1/AD7658-1 Daisy-Chain Mode (DCEN = 1, SER/PAR SEL = 1) When reading conversion data back from the AD7656-1/AD7657-1/ AD7658-1 using three/two/one DOUT pins, it is possible to configure the parts to operate in daisy-chain mode by using the DCEN pin. This daisy-chain feature allows multiple AD7656-1/ AD7657-1/AD7658-1 devices to be cascaded together and is useful for reducing the component count and wiring connections. An example connection of two devices is shown in Figure 34. This configuration shows two DOUT lines being used for each device. Simultaneous sampling of the 12 analog inputs is possible by using a common CONVST signal. The DB5, DB4, and DB3 data pins are used as the DCIN[A:C] data input pins for the daisy-chain mode. The rising edge of CONVST is used to initiate a conversion on the AD7656-1/AD7657-1/AD7658-1. After the BUSY signal has gone low to indicate that the conversion is complete, the user can begin to read the data from the two devices. Figure 35 shows the serial timing diagram when operating two AD7656-1/AD7657-1/ AD7658-1 devices in daisy-chain mode. The CS falling edge is used to frame the serial transfer from the AD7656-1/AD7657-1/AD7658-1 devices, to take the bus out of three-state, and to clock out the MSB of the first conversion result. In the example shown in Figure 35, all 12 ADC channels are simultaneously sampled. Two DOUT lines are used to read the conversion results in this example. CS frames a 96 SCLK transfer. During the first 48 SCLKs, the conversion data is transferred from Device 2 to Device 1. DOUT A on Device 2 transfers conversion data from V1, V2, and V5 into DCIN A in Device 1; DOUT B on Device 2 transfers conversion results from V3, V4, and V6 to DCIN B in Device 1. During the first 48 SCLKs, Device 1 transfers data into the digital host. DOUT A on Device 1 transfers conversion data from V1, V2, and V5; DOUT B on Device 1 transfers conversion data from V3, V4, and V6. During the last 48 SCLKs, Device 2 clocks out 0s, and Device 1 shifts the data clocked in from Device 2 during the first 48 SCLKs into the digital host. This example can also be implemented using six 16-SCLK individually framed transfers if DCEN remains high during the transfers. Figure 36 shows the timing if two AD7656-1/AD7657-1/AD7658-1 devices are configured in daisy-chain mode and are operating with three DOUT lines. Assuming that a simultaneous sampling of all 12 inputs occurs, the CS frames a 64 SCLK transfer during the read operation. During the first 32 SCLKs of this transfer, the conversion results from Device 1 are clocked into the digital host and the conversion results from Device 2 are clocked into Device 1. During the last 32 SCLKs of the transfer, the conversion results from Device 2 are clocked out of Device 1 and into the digital host, and Device 2 clocks out 0s. Standby/Partial Power-Down Modes of Operation (SER/PAR SEL = 0 or 1) Each ADC pair can be individually placed into partial powerdown mode by bringing the CONVST signal low before the falling edge of BUSY. To power the ADC pair back up, the CONVST signal should be brought high to tell the ADC pair to power up and place the track-and-hold amplifier into track mode. After the power-up time from partial power-down has elapsed, the CONVST signal should receive a rising edge to initiate a valid conversion. In partial power-down mode, the reference buffers remain powered up. When an ADC pair is in partial power-down mode, conversions can still occur on the other ADCs. The AD7656-1/AD7657-1/AD7658-1 have a standby mode whereby the devices can be placed into a low power consumption mode (25 μW maximum). The AD7656-1/AD7657-1/AD7658-1 are placed into standby mode by bringing the logic input STBY low and can be powered up again for normal operation by bringing STBY logic high. The output data buffers are still operational when the AD7656-1/AD7657-1/AD7658-1 are in standby mode, meaning the user can continue to access the conversion results of the parts. This standby feature can be used to reduce the average power consumed by the AD7656-1/AD7657-1/ AD7658-1 when operating at lower throughput rates. The parts can be placed into standby at the end of each conversion when BUSY goes low and are taken out of standby mode prior to the next conversion. The time for the AD7656-1/AD7657-1/ AD7658-1 to come out of standby is called the wake-up time. The wake-up time limits the maximum throughput rate at which the AD7656-1/AD7657-1/AD7658-1 can operate when powering down between conversions. See the Specifications section. Rev. 0 | Page 27 of 32 AD7656-1/AD7657-1/AD7658-1 CONVERT DIGITAL HOST CONVST CONVST AD7656-1/ AD7657-1/ AD7658-1 SCLK DOUT A DCIN A DOUT B DCIN B AD7656-1/ AD7657-1/ AD7658-1 SCLK CS DOUT A DATA IN1 DOUT B DATA IN2 CS CS 07017-033 SCLK DCEN = 0 DEVICE 2 DCEN = 1 DEVICE 1 Figure 34. Daisy-Chain Configuration CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 65 94 95 96 SCLK MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 07017-034 DEVICE 1, DOUT A Figure 35. Daisy-Chain Serial Interface Timing with Two DOUT Lines CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 DEVICE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 1, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 MSB V5 LSB V5 MSB V6 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 2, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 Figure 36. Daisy-Chain Serial Interface Timing with Three DOUT Lines Rev. 0 | Page 28 of 32 07017-035 SCLK AD7656-1/AD7657-1/AD7658-1 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7656-1/AD7657-1/ AD7658-1 should be designed so that the analog and digital sections are separated and confined to different areas of the board. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably underneath the AD7656-1/ AD7657-1/AD7658-1, or at least as close as possible to the part. If the AD7656-1/AD7657-1/AD7658-1 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point, a star ground point, which should be established as close as possible to the AD7656-1/AD7657-1/AD7658-1. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or multiple vias to the ground plane should be used for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7656-1/AD7657-1/AD7658-1 to avoid noise coupling. Fast-switching signals like CONVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC, DVCC, VDRIVE, VDD, and VSS pins on the AD7656-1/AD7657-1/AD7658-1 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good connections should be made between the AD7656-1/AD7657-1/AD7658-1 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. Good decoupling is also important to lower the supply impedance presented to the AD7656-1/AD7657-1/AD7658-1 and to reduce the magnitude of the supply spikes. The decoupling capacitors should be placed close to, ideally right up against, these pins and their corresponding ground pins. Additionally, low-ESR 1 μF capacitors should be placed on each of the supply pins, the REFIN/REFOUT pin, and each REFCAPx pin. Avoid sharing these capacitors between pins, and use vias to connect the capacitors to the power and ground planes. In addition, use wide, short traces between each via and the capacitor pad, or place the vias adjacent to the capacitor pad to minimize parasitic inductances. The AD7656-1/AD7657-1/AD7658-1 offer the user a reduced decoupling solution that is pin and software compatible with AD7656/AD7657/AD7658. The recommended reduced decoupling required for AD7656-1/AD7657-1/AD7658-1 is outlined in Figure 27. Figure 27 shows an external Schmitt trigger device on the CONVST A, CONVST B, CONVST C inputs. The Schmitt trigger can be placed close to the CONVST pins (decoupled to the digital ground) and is used to eliminate any system noise that couples onto long CONVST A, CONVST B, CONVST C traces from being applied to the CONVST pins. The Schmitt trigger offers noise immunity to any high frequency noise, providing a clean conversion edge to the AD7656-1/AD7657-1/AD7658-1 device in cases where there is large system noise capable of coupling onto the CONVST trace. Rev. 0 | Page 29 of 32 AD7656-1/AD7657-1/AD7658-1 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 37. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model AD7656BSTZ-1 1 AD7656BSTZ-1-RL1 AD7656YSTZ-11 AD7656YSTZ-1-RL1 AD7657BSTZ-11 AD7657BSTZ-1-RL1 AD7657YSTZ-11 AD7657YSTZ-1-RL1 AD7658BSTZ-11 AD7658BSTZ-1-RL1 AD7658YSTZ-11 AD7658YSTZ-1-RL1 EVAL-AD7656-1EDZ1 EVAL-AD7657-1EDZ1 EVAL-AD7658-1EDZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 30 of 32 Package Option ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 AD7656-1/AD7657-1/AD7658-1 NOTES Rev. 0 | Page 31 of 32 AD7656-1/AD7657-1/AD7658-1 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07017-0-7/08(0) Rev. 0 | Page 32 of 32