Product Folder Sample & Buy Support & Community Tools & Software Technical Documents AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 AFE4403 Ultra-Small, Integrated Analog Front-End for Heart Rate Monitors and Low-Cost Pulse Oximeters 1 Features 2 Applications • • • • 1 • • • • • • • Fully-Integrated AFE for Pulse Oximeter and Heart Rate Monitoring Applications: Transmit: – Integrated Dual LED Driver (H-Bridge or Common Anode) – Option for a Third LED Support for Optimized SPO2, HRM, or Multi-Wavelength HRM – Up to 110-dB Dynamic Range – LED Current: – Programmable to 100 mA with 8-Bit Current Resolution – 30 µA + Average LED Current – Programmable LED On-Time – Independent LED2 and LED1 Current Reference Receive Channel with High Dynamic Range: – 22-Bit Output in Twos Complement Format – Up to 105-dB Dynamic Range – Low Power: < 650 µA – Dynamic Power-Down Mode to Reduce Current to 300 µA – Adaptable to a Very Wide Range of Signal Amplitudes: – Total Programmable Gain: 10 kΩ to 4 MΩ – Integrated Digital Ambient Estimation and Subtraction Flexible Clocking by External Clock or Crystal: – Pulse Frequency: 62.5 SPS to 2000 SPS – Flexible Pulse sequencing and Timing Control – Input Clock Range: 4 MHz (Min) to 60 MHz (Max) Integrated Fault Diagnostics: – Photodiode and LED Open and Short Detection Supplies: – Rx = 2.0 V to 3.6 V – Tx = 3.0 V to 5.25 V Package: Compact DSBGA-36 (3.07 mm × 3.07 mm × 0.5 mm) Specified Temperature Range: –20°C to 70°C Medical Pulse Oximeter Applications Optical HRM Industrial Photometry Applications 3 Description The AFE4403 is a fully-integrated analog front-end (AFE) ideally suited for pulse oximeter applications. The device consists of a low-noise receiver channel with an integrated analog-to-digital converter (ADC), an LED transmit section, and diagnostics for sensor and LED fault detection. The device is a very configurable timing controller. This flexibility enables the user to have complete control of the device timing characteristics. To ease clocking requirements and provide a low-jitter clock to the AFE4403, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI™ interface. The device is a complete AFE solution packaged in a single, compact DSBGA-36 (3.07 mm × 3.07 mm × 0.5 mm) and is specified over the operating temperature range of –20°C to 70°C. Device Information(1) PART NUMBER AFE4403 PACKAGE DSBGA (36) BODY SIZE (NOM) 3.07 mm × 3.07 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Family Options .......................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Absolute Maximum Ratings ...................................... 5 Handling Ratings....................................................... 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements .............................................. 11 Timing Requirements: Supply Ramp and PowerDown ........................................................................ 12 7.8 Typical Characteristics ............................................ 14 8 Detailed Description ............................................ 20 8.1 Overview ................................................................. 20 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 20 21 45 53 58 Application and Implementation ........................ 83 9.1 Application Information............................................ 83 9.2 Typical Application .................................................. 83 10 Power Supply Recommendations ..................... 87 10.1 Power Consumption Considerations..................... 88 11 Layout................................................................... 90 11.1 Layout Guidelines ................................................. 90 11.2 Layout Example .................................................... 90 12 Device and Documentation Support ................. 91 12.1 Trademarks ........................................................... 91 12.2 Electrostatic Discharge Caution ............................ 91 12.3 Glossary ................................................................ 91 13 Mechanical, Packaging, and Orderable Information ........................................................... 91 4 Revision History Changes from Revision A (June 2014) to Revision B Page • Changed Pin Configuration diagram: changed Top View to Bottom View ............................................................................ 3 • Added footnote to Figure 41 ................................................................................................................................................ 27 Changes from Original (May 2014) to Revision A Page • Changed document status to Production Data ...................................................................................................................... 1 • Changed first and third sub-bullets of Flexible Clocking Features bullet .............................................................................. 1 • Changed MIN to NOM in Body Size column of Device Information table ............................................................................. 1 • Added Device Family Options table and Pin Configuration and Functions section ............................................................... 3 • Added Specifications section ................................................................................................................................................. 5 • Added Detailed Description section ..................................................................................................................................... 20 • Added Application and Implementation section.................................................................................................................... 83 • Added Power Supply Recommendations section ............................................................................................................... 87 • Added Layout section .......................................................................................................................................................... 90 2 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 5 Device Family Options LED DRIVE CURRENT (mA, max) Tx POWER SUPPLY (V) OPERATING TEMPERATURE RANGE PRODUCT PACKAGE-LEAD LED DRIVE CONFIGURATION AFE4400 VQFN-40 Bridge, push-pull 50 3 to 5.25 0°C to 70°C AFE4490 VQFN-40 Bridge, push-pull 50, 75, 100, 150, and 200 3 to 5.25 –40°C to 85°C AFE4403 DSBGA-36 Bridge, push-pull 25, 50, 75, and 100 3 to 5.25 –20°C to 70°C 6 Pin Configuration and Functions YZP Package DSBGA-36 (Bottom View) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 3 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Pin Functions PIN NAME (1) 4 NO. FUNCTION DESCRIPTION ADC_RDY D5 Digital Output signal that indicates ADC conversion completion. Can be connected to the interrupt input pin of an external microcontroller. AFE_PDN C3 Digital AFE-only power-down input; active low. Can be connected to the port pin of an external microcontroller. Decoupling capacitor for internal band-gap voltage to ground. Connect a decoupling capacitor to ground. To achieve the lowest transmitter noise, use a capacitor value of 2.2 µF. To reduce the recovery time from power-down (from 1 s to 0.1 s), use a capacitor value of 0.1 µF instead—but with slightly degraded transmitter noise. BG C2 Reference CLKOUT E6 Digital Buffered 4-MHz output clock output. Can be connected to the clock input pin of an external microcontroller. DIAG_END B4 Digital Output signal that indicates completion of diagnostics. Can be connected to the port pin of an external microcontroller. DNC (1) C1, A1, E3, D3, F5, B5, B6 — Do not connect these pins. Leave as open circuit. INN F1 Analog Receiver input pin. Connect to photodiode anode. INP E1 Analog Receiver input pin. Connect to photodiode cathode. LED_DRV_GND A3 Supply LED driver ground pin, H-bridge. Connect to common board ground. LED_DRV_SUP A6 Supply LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the large LED current, which is drawn by this supply pin. RESET D4 Digital AFE-only reset input, active low. Can be connected to the port pin of an external microcontroller RX_ANA_GND E2 Supply Rx analog ground pin. Connect to common board ground. RX_ANA_SUP F2, E4 Supply Rx analog supply pin; 0.1-µF decoupling capacitor to ground RX_DIG_GND B2, F6 Supply Rx digital ground pin. Connect to common board ground. RX_DIG_SUP E5 Supply Rx digital supply pin; 0.1-µF decoupling capacitor to ground SCLK C6 SPI SPI clock pin SPISIMO C4 SPI SPI serial in master out SPISOMI C5 SPI SPI serial out master in SPISTE D6 SPI SPI serial interface enable TX_CTRL_SUP A2 Supply Transmit control supply pin (0.1-µF decoupling capacitor to ground) Transmitter reference voltage, 0.25 V default after reset. Connect a decoupling capacitor to ground. To achieve the lowest transmitter noise, use a capacitor value of 2.2 µF. To reduce the recovery time from power-down (from 1 s to 0.1 s), use a capacitor value of 0.1 µF instead—but with slightly degraded transmitter noise. TX_REF B1 Reference TXN A4 Analog LED driver out. Connect to LED in common anode or H-bridge configuration. TXP A5 Analog LED driver out. Connect to LED in common anode or H-bridge configuration. TX3 B3 Analog LED driver out for third LED. Connect to optional third LED supported in common anode configuration. Input common-mode voltage output. This signal can be used to shield (guard) the INP, INN traces. If used as a shield, then connect a series resistor (1 kΩ) and a decoupling capacitor (10 nF) to ground. If VCM is not used externally, then these external components are not required. VCM D1 Reference VSS D2 Supply Substrate ground. Connect to common board ground. XOUT F4 Digital Crystal oscillator pins. Connect an external crystal between these pins with the correct load capacitor (as specified by vendor) to ground. XIN F3 Digital Crystal oscillator pins. Connect an external crystal between these pins with the correct load capacitor (as specified by vendor) to ground. Leave pins as open circuit. Do not connect. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT RX_ANA_SUP, RX_DIG_SUP to RX_ANA_GND, RX_DIG_GND –0.3 4 V TX_CTRL_SUP, LED_DRV_SUP to LED_DRV_GND –0.3 6 V RX_ANA_GND, RX_DIG_GND to LED_DRV_GND –0.3 0.3 V Analog inputs RX_ANA_GND – 0.3 RX_ANA_SUP + 0.3 V Digital inputs RX_DIG_GND – 0.3 RX_DIG_SUP + 0.3 V ±7 mA ±50 mA ±7 mA 70 °C 125 °C Input current to any pin except supply pins (2) Input current Momentary Continuous Operating temperature range 0–20 Maximum junction temperature, TJ (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited to 10 mA or less. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT °C –60 150 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –1000 1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –250 250 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 5 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX UNIT SUPPLIES RX_ANA_SUP AFE analog supply 2.0 3.6 V RX_DIG_SUP AFE digital supply 2.0 3.6 V TX_CTRL_SUP Transmit controller supply 3.0 5.25 V 5.25 V [3.0 or (0.5 + VLED + VCABLE) , whichever is greater] 5.25 V Difference between LED_DRV_SUP and TX_CTRL_SUP –0.3 0.3 V Specified temperature range –20 70 °C Storage temperature range –60 150 °C (1) (2) H-bridge LED_DRV_SUP Transmit LED driver supply Common anode configuration [3.0 or (0.75 + VLED + VCABLE) , whichever is greater] (1) (2) TEMPERATURE (1) (2) VLED refers to the maximum voltage drop across the external LED (at maximum LED current) connected between the TXP and TXN pins (in H-bridge mode) and from the TXP and TXN pins to LED_DRV_SUP (in the common anode configuration). VCABLE refers to voltage drop across any cable, connector, or any other component in series with the LED. 7.4 Thermal Information AFE4403 THERMAL METRIC (1) YZP (WCSP) UNIT 36 BALLS RθJA Junction-to-ambient thermal resistance 49.8 RθJC(top) Junction-to-case (top) thermal resistance 0.2 RθJB Junction-to-board thermal resistance 8.5 ψJT Junction-to-top characterization parameter 0.8 ψJB Junction-to-board characterization parameter 8.5 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a (1) 6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 7.5 Electrical Characteristics Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled, detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V, and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2 amplifier disabled, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PERFORMANCE (Full-Signal Chain) IIN_FS Full-scale input current RF = 10 kΩ 50 µA RF = 25 kΩ 20 µA RF = 50 kΩ 10 µA RF = 100 kΩ 5 µA RF = 250 kΩ 2 µA RF = 500 kΩ 1 µA RF = 1 MΩ PRF Pulse repetition frequency DCPRF PRF duty cycle 0.5 62.5 µA 2000 SPS 25% fCM = 50 Hz and 60 Hz, LED1 and LED2 with RSERIES = 500 kΩ, RF = 500 kΩ 75 dB fCM = 50 Hz and 60 Hz, LED1-AMB and LED2-AMB with RSERIES = 500 kΩ, RF = 500 kΩ 95 dB PSRRLED PSRR, transmit LED driver With respect to ripple on LED_DRV_SUP 75 dB PSRRTx PSRR, transmit control With respect to ripple on TX_CTRL_SUP 60 dB PSRRRx PSRR, receiver With respect to ripple on RX_ANA_SUP and RX_DIG_SUP 60 dB Total integrated noise current, inputreferred (receiver with transmitter loop back, 0.1-Hz to 20-Hz bandwidth) RF = 100 kΩ, PRF = 600 Hz, duty cycle = 5% 25 pARMS RF = 500 kΩ, PRF = 600 Hz, duty cycle = 5% 6 pARMS RF = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 25% 3.2 pARMS RF = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 5% 5.3 pARMS CMRR Common-mode rejection ratio RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION Total integrated noise current, input referred (receiver alone) over 0.1-Hz to 20-Hz bandwidth I-V TRANSIMPEDANCE AMPLIFIER G RF = 10 kΩ to 1 MΩ See the Receiver Channel section for details Feedback resistance RF 10k, 25k, 50k, 100k, 250k, 500k, and 1M Feedback resistor tolerance RF Feedback capacitance CF Feedback capacitor tolerance CF Gain Gain accuracy V/µA ±7% Ω ±20% 5, 10, 25, 50, 100, and 250 pF ±20% Full-scale differential output voltage Common-mode voltage on input pins Set internally External differential input capacitance Includes equivalent capacitance of photodiode, cables, EMI filter, and so forth 10 Shield output voltage, VCM With a 1-kΩ series resistor and a 10-nF decoupling capacitor to ground 0.8 1 V 0.9 V 0.9 1000 pF 1 V Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 7 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Electrical Characteristics (continued) Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled, detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V, and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2 amplifier disabled, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AMBIENT CANCELLATION STAGE Gain 0, 3.5, 6, 9.5, and 12 Current DAC range 0 Current DAC step size dB 10 µA 1 µA LOW-PASS FILTER Low-pass corner frequency Pass-band attenuation, 2 Hz to 10 Hz Filter settling time 3-dB attenuation 500 Hz Duty cycle = 25% 0.004 dB Duty cycle = 10% 0.041 dB 28 ms After diagnostics mode ANALOG-TO-DIGITAL CONVERTER Resolution Sample rate 22 See the ADC Operation and Averaging Module section 4 × PRF ADC full-scale voltage ADC conversion time ±1.2 See the ADC Operation and Averaging Module section V PRF / 4 ADC reset time (1) Bits SPS 2 µs tCLK TRANSMITTER Selectable, 0 to 100 (see the LEDCNTRL: LED Control Register for details) Output current range LED current DAC error ±10% Output current resolution Transmitter noise dynamic range, over 0.1-Hz to 20-Hz bandwidth, TX_REF set to 0.5 V 8 Bits At 25-mA output current 110 dB At 50-mA output current 110 dB 50 µs LED_ON = 0 1 µA LED_ON = 1 50 µA Minimum sample time of LED1 and LED2 pulses LED current DAC leakage current mA LED current DAC linearity Percent of full-scale current 0.50 % Output current settling time (with resistive load) From zero current to 50 mA 7 µs From 50 mA to zero current 7 µs 16 ms Open fault resistance > 100 kΩ Short fault resistance < 10 kΩ DIAGNOSTICS Duration of diagnostics state machine Start of diagnostics after the DIAG_EN register bit is set. End of diagnostic is indicated by DIAG_END going high. INTERNAL OSCILLATOR fCLKOUT CLKOUT frequency With an 8-MHz crystal connected to the XIN, XOUT pins CLKOUT duty cycle Crystal oscillator start-up time (1) 8 4 MHz 50% With an 8-MHz crystal connected to the XIN, XOUT pins 200 µs A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28 in Figure 48. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Electrical Characteristics (continued) Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled, detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V, and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2 amplifier disabled, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL CLOCK Maximum allowable external clock jitter External clock input frequency (2) For SPO2 applications 50 For optical heart rate only ps 1000 ±2% 4 8 ps 60 MHz Voltage input high (VIH) 0.75 × RX_DIG_SUP V Voltage input low (VIL) 0.25 × RX_DIG_SUP V External clock input voltage TIMING Wake-up time from complete power-down 1000 ms Wake-up time from Rx power-down 100 µs Wake-up time from Tx power-down 1000 ms tRESET Active low RESET pulse duration 1 ms tDIAGEND DIAG_END pulse duration at the completion of diagnostics 4 CLKOUT cycles tADCRDY ADC_RDY pulse duration 1 CLKOUT cycle DIGITAL SIGNAL CHARACTERISTICS VIH Logic high input voltage AFE_PDN, SCLK, SPISIMO, SPISTE, RESET 0.8 DVDD > 1.3 DVDD + 0.1 V VIL Logic low input voltage AFE_PDN, SCLK, SPISIMO, SPISTE, RESET –0.1 < 0.4 0.2 DVDD V IIN Logic input current 0 V < VDigitalInput < DVDD –10 10 µA 0.9 DVDD > (RX_DIG_SUP – 0.2 V) V 0.1 DVDD V VOH Logic high output voltage DIAG_END, SPISOMI, ADC_RDY, CLKOUT VOL Logic low output voltage DIAG_END, SPISOMI, ADC_RDY, CLKOUT < 0.4 SUPPLY CURRENT RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 disabled 0.6 mA RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 enabled 0.7 mA RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 disabled, external clock mode 0.49 mA Receiver digital supply current RX_DIG_SUP = 3.0 V 0.15 mA LED driver supply current With zero LED current setting 30 µA 15 µA Receiver current only (RX_ANA_SUP) 3 µA Receiver current only (RX_DIG_SUP) 3 µA Transmitter current only (LED_DRV_SUP) 1 µA Transmitter current only (TX_CTRL_SUP) 1 µA Receiver current only (RX_ANA_SUP) 200 µA Receiver current only (RX_DIG_SUP) 150 µA Transmitter current only (LED_DRV_SUP) 2 µA Transmitter current only (TX_CTRL_SUP) 2 µA Receiver analog supply current Transmitter control supply current Complete power-down (using the AFE_PDN pin) Power-down Rx alone Power-down Tx alone (2) Refer to the CLKDIV[2:0] register bits for a detailed list of input clock frequencies that are supported. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 9 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Electrical Characteristics (continued) Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled, detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V, and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2 amplifier disabled, and fCLK = 8 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER DISSIPATION LED_DRV_SUP Power-down with the AFE_PDN pin 1 µA 1 µA RX_ANA_SUP 5 µA RX_DIG_SUP 0.1 µA 1 µA TX_CTRL_SUP 1 µA RX_ANA_SUP 15 µA RX_DIG_SUP 20 µA 30 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 200 µA RX_DIG_SUP 150 µA 2 µA 2 µA RX_ANA_SUP 600 µA RX_DIG_SUP 150 µA 30 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 600 µA RX_DIG_SUP 150 µA 30 µA TX_CTRL_SUP 15 µA RX_ANA_SUP 700 µA RX_DIG_SUP 150 µA 7 µA LED_DRV_SUP Power-down with the PDNAFE register bit LED_DRV_SUP Power-down Rx LED_DRV_SUP Power-down Tx LED_DRV_SUP With stage 2 mode enabled and 8-MHz clock running LED_DRV_SUP Dynamic powerdown mode enabled Does not include LED current. Does not include LED current. Does not include LED current. TX_CTRL_SUP LED_DRV_SUP After reset, with 8MHz clock running Does not include LED current. TX_CTRL_SUP TX_CTRL_SUP RX_ANA_SUP Does not include LED current. Does not include LED current. Does not include LED current. PRF = 100 Hz, PDN_CYCLE duration = 8 ms RX_DIG_SUP 10 Submit Documentation Feedback 5 µA 205 µA 150 µA Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 7.6 Timing Requirements PARAMETER tCLK Clock frequency on the XIN pin tSCLK Serial shift clock period tSTECLK MIN TYP MAX UNIT 8 MHz 62.5 ns STE low to SCLK rising edge, setup time 10 ns tCLKSTEH,L SCLK transition to SPI STE high or low 10 ns tSIMOSU SIMO data to SCLK rising edge, setup time 10 ns tSIMOHD Valid SIMO data after SCLK rising edge, hold time 10 ns tSOMIPD SCLK falling edge to valid SOMI, setup time 17 ns tSOMIHD SCLK rising edge to invalid data, hold time 0.5 tSCLK tCLK XIN tSTECLK SPISTE tSPICLK tCLKSTEH 31 SCLK 7 23 0 tCLKSTEL tSIMOHD tSIMOSU SPISIMO A7 A6 A1 A0 tSOMIHD tSOMIPD tSOMIPD D23 SPISOMI D22 D17 D16 D7 D6 D1 D0 }v[, can be high or low. (1) The SPI_READ register bit must be enabled before attempting a register read. (2) Specify the register address whose contents must be read back on A[7:0]. (3) The AFE outputs the contents of the specified register on the SPISOMI pin. Figure 1. Serial Interface Timing Diagram, Read Operation(1)(2)(3) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 11 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com tSTECLK SPISTE 31 SCLK 23 0 tSIMOHD tSIMOSU A7 SPISIMO A6 A1 A0 D23 D22 D1 D0 Figure 2. Serial Interface Timing Diagram, Write Operation 7.7 Timing Requirements: Supply Ramp and Power-Down PARAMETER VALUE t1 Time between Rx and Tx supplies ramping up Keep as small as possible (for example, ±10 ms) t2 Time between both supplies stabilizing and high-going RESET edge > 100 ms t3 RESET pulse duration > 0.5 ms t4 Time between RESET and SPI commands > 1 µs t5 Time between SPI commands and the ADC_RESET which corresponds to valid data > 3 ms of cumulative sampling time in each phase (1) (2) (3) t6 Time between RESET pulse and high-accuracy data coming out of the signal chain > 1 s (3) t7 Time from AFE_PDN high-going edge and RESET pulse (4) > 100 ms t8 Time from AFE_PDN high-going edge (or PDN_AFE bit reset) to highaccuracy data coming out of the signal chain > 1 s (3) (1) (2) (3) (4) 12 This time is required for each of the four switched RC filters to fully settle to the new settings. The same time is applicable whenever there is a change to any of the signal chain controls (for example, LED current setting, TIA gain, and so forth). If the SPI commands involve a change in the TX_REF value from its default, then there is additional wait time of approximately 1 s (for a 2.2-µF decoupling capacitor on the TX_REF pin). Dependent on the value of the capacitors on the BG and TX_REF pins. The 1-s wait time is necessary when the capacitors are 2.2 µF and scale down proportionate to the capacitor value. A very low capacitor (for example, 0.1 µF) on these pins causes the transmitter dynamic range to reduce to approximately 100 dB. After an active power-down from AFE_PDN, the device should be reset using a low-going RESET pulse. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 RX Supplies (RX_ANA_SUP, RX_DIG_SUP) t1 TX Supplies (TX_CTRL_SUP, LED_DRV_SUP) t2 t6 RESET t3 t4 t4 t5 t5 SPI Interface t7 t3 ~ ~ ~ ~ ADC_RDY t6 t8 AFE_PDN Figure 3. Supply Ramp and Hardware Power-Down Timing RX Supplies (RX_ANA_SUP, RX_DIG_SUP) t1 TX Supplies (TX_CTRL_SUP, LED_DRV_SUP) t2 PDN_AFE Bit Set RESET t3 t4 t5 t8 t6 ~ ~ ADC_RDY ~ ~ ~ ~ SPI Interface PDN_AFE Bit Reset AFE_PDN Figure 4. Supply Ramp and Software Power-Down Timing Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 13 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 7.8 Typical Characteristics At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted. 600 50 500 40 400 Transmitter Currents (uA) Receiver Currents (uA) I(LED_DRV_SUP) I(RX_DIG_SUP) I(RX_ANA_SUP) 300 200 100 I(TX_CTRL_SUP) 30 20 10 0 2 2.2 2.4 2.6 2.8 3 3.2 3.4 Receiver Supply Voltage (V) 3.6 2.6 3 3.4 3.8 4.2 4.6 5 Transmitter Supply Voltage (V) C001 C002 LED current = 0 mA Figure 5. Receiver Currents vs Receiver Supply Voltage Figure 6. Transmitter Currents vs Transmitter Supply Voltage 1000 600 Receiver Current (uA) 700 Receiver Current (uA) 1200 800 Clock Division Ratio = 1 Clock Division Ratio = 2 Clock Division Ratio = 4 Clock Division Ratio = 6 Clock Division Ratio = 8 Clock Division Ratio = 12 600 400 500 400 300 200 200 0 10 20 30 40 50 60 External Clock Frequency (MHz) 50 PRF = 150 Hz Active window = 500 µs 700 5 600 ±5 500 400 300 650 850 1050 1250 C004 LED pulse = 100 µs All four DYNAMIC bits set to 1 Figure 8. Receiver Current vs PRF in Dynamic Power-Down Mode Attanuation ( dB) Receiver Current (uA) 450 PRF (Hz) Figure 7. Receiver Currents (Analog and Digital) vs Clock Divider Ratio ±15 5% Duty cycle ±25 25% Duty cycle ±35 200 ±45 0 1 2 3 4 5 6 PDN_CYCLE Width (ms) PRF = 100 Hz 7 8 9 1 C005 10 100 Frequency (Hz) in Log Scale 1000 C030 LED pulse = 100 µs All four DYNAMIC bits set to 1 Figure 9. Receiver Current (Analog and Digital) vs Dynamic Power-Down Duty Cycle 14 250 C003 Submit Documentation Feedback Figure 10. Filter Response vs Duty cycle Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Typical Characteristics (continued) At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted. 50 Output voltage = 0 %FS Input-Referred Noise Current (pArms) over Nyquist Bandwidth SNR (dBFS) over Nyquist Bandwidth 106 Output voltage = 10 %FS 104 Output voltage = 25 %FS Output voltage = 50 %FS 102 Output voltage = 75 %FS 100 98 0 5 10 15 20 Duty Cycle (%) Output voltage = 25 %FS Output voltage = 50 %FS 35 Output voltage = 75 %FS 30 25 20 15 0 25 5 10 15 20 Duty Cycle (%) C007 500-Hz PRF 25 C006 500-Hz PRF Figure 11. SNR over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback) Figure 12. Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback) 100000 Input-Referred Noise Current (pArms) over Nyquist Bandwidth in Log Scale 108 SNR (dBFS) over Nyqusit Bandwidth Output voltage = 10 %FS 40 10 96 RF = 10 k RF = 25 k RF = 50 k RF = 100 k RF = 250 k RF = 500 k RF = 1000 k 106 104 102 100 RF = 10 k RF = 25 k RF = 50 k RF = 100 k RF = 250 k RF = 500 k RF = 1000 k 10000 1000 100 10 1 98 0 5 10 15 20 Duty Cycle (%) 0 25 5 10 15 20 Duty Cycle (%) C008 Figure 13. Receiver SNR over Nyquist Bandwidth vs Duty Cycle (Different Gain Settings) 25 C011 Figure 14. Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different Gain Settings) 100000 112 RF = 10 k RF = 25 k RF = 50 k RF = 100 k RF = 250 k RF = 500 k RF = 1000 k 110 108 input-Referred Noise Current (pArms) in 20-Hz Bandwidth in Log Scale SNR (dBFS) in 20-Hz Bandwidth Output voltage = 0 %FS 45 106 104 RF = 10 k RF = 25 k RF = 50 k RF = 100 k RF = 250 k RF = 500 k RF = 1000 k 10000 1000 100 10 1 102 0 5 10 15 Duty Cycle (%) 20 25 0 Figure 15. Receiver SNR in 20-Hz BW vs Duty Cycle (Different Gain Settings) 5 10 15 20 Duty Cycle (%) C009 25 C010 Figure 16. Receiver Input-Referred Noise Current in 20-Hz BW vs Duty Cycle (Different Gain Settings) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 15 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Typical Characteristics (continued) At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted. 40 input-Referred Noise Current (pArms) over Nyquist Bandwidth SNR (dBFS) over Nyquist Bandwidth 102 98 94 ADC Averaging = 1 ADC Averaging = 2 ADC Averaging = 4 90 ADC Averaging = 8 ADC Averaging = 16 86 5 10 15 20 0 5 10 15 20 Duty Cycle (%) C013 Figure 17. Receiver SNR over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging) 25 C012 Figure 18. Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging) 30 Input-Referred Noise Current (pArms) in 20-Hz Bandwidth 116 SNR (dBFS) in 20-Hz Bandwidth ADC Averaging = 1 ADC Averaging = 2 ADC Averaging = 4 ADC Averaging = 8 ADC Averaging = 16 10 25 Duty Cycle (%) 112 108 104 PRF = 62.5 Hz PRF = 100 Hz PRF = 500 Hz PRF = 1000 Hz PRF = 2000 Hz 100 96 92 PRF = 62.5 Hz PRF = 100 Hz PRF = 500 Hz PRF = 1000 Hz PRF = 2000 Hz 25 20 15 10 5 0 0 5 10 15 20 25 Duty Cycle (%) 0 5 10 15 20 Duty Cycle (%) C015 Figure 19. Receiver SNR in 20-Hz BW vs Duty Cycle (Different PRFs) 25 C014 Figure 20. Receiver Input Referred Noise in 20-Hz BW vs Duty Cycle (Different PRFs) 25 Input-Referred Noise Current (pArms) in 20-Hz Bandwidth 112 SNR (dBFS) in 20-Hz Bandwidth 20 0 0 108 104 100 20 15 10 5 0 96 0 250 500 750 PRF (Hz) Active window = 500 µs 1000 1250 0 250 500 LED pulse = 100 µs All four DYNAMIC bits set to 1 750 PRF (Hz) C017 Figure 21. Receiver SNR in 20-Hz BW in Dynamic Power-Down Mode vs PRF 16 30 Active window = 500 µs 1000 1250 C016 LED pulse = 100 µs All four DYNAMIC bits set to 1 Figure 22. Receiver Input-Referred Noise in 20-Hz BW in Dynamic Power-Down Mode vs PRF Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Typical Characteristics (continued) At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted. 30 Input-Referred Noise Current (pArms) over Nyquist Bandwidth SNR (dBFS) over Nyquist Bandwidth 106 104 102 100 98 96 2 4 6 8 18 14 10 Dynamic Powerdown Cycle Width (ms) PRF = 100 Hz 0 2 4 6 8 10 Dynamic Powerdown Cycle width (ms) C019 LED pulse = 100 µs All four DYNAMIC bits set to 1 Figure 23. Receiver SNR over Nyquist Bandwidth vs Dynamic Power-Down Duty Cycle PRF = 100 Hz C018 LED pulse = 100 µs All four DYNAMIC bits set to 1 Figure 24. Receiver Input-Referred Noise over Nyquist Bandwidth vs Dynamic Power-Down Duty Cycle 30 Input-Referred Noise Current (pArms) in 20-Hz Bandwidth 106 SNR (dBFS) in 20-Hz Bandwidth 22 10 0 104 102 100 RF = 250 k 98 RF = 500 k 26 22 RF = 250 k RF = 500 k 18 14 10 96 ±20 0 ±10 10 20 30 40 50 60 Temperature (deg C) LED pulse = 100 µs 70 ±20 0 ±10 10 20 30 40 50 60 Temperature (deg C) C021 Pleth current = 1 µA Figure 25. SNR in 20-Hz Bandwidth vs Temperature (Tx-Rx Loopback) LED pulse = 100 µs 70 C020 Pleth current = 1 µA Figure 26. Input-Referred Noise Current in 20-Hz BW vs Temperature (TX-Rx Loopback) 106 20 Input-Referred Noise Current (pArms) in 20-Hz Bandwidth SNR (dBFS) in 20-Hz Bandwidth 26 105 104 103 102 101 100 Stg2Gain = 1 Stg2Gain = 1.5 Stg2Gain = 2 Stg2Gain = 3 Stg2Gain = 4 99 98 97 96 Stg2Gain = 1 Stg2Gain = 1.5 Stg2Gain = 2 Stg2Gain = 3 Stg2Gain = 4 16 12 8 4 0 0 5 10 15 Duty Cycle (%) 20 25 0 Stage 2 enabled 5 10 15 Duty Cycle (%) C023 20 25 C022 Stage 2 enabled Figure 27. Receiver SNR over Nyquist Bandwidth vs Duty Cycle (Different Stage 2 Gain Settings) Figure 28. Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different Stage 2 Gain Settings) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 17 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Typical Characteristics (continued) At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted. 100 56 80 LED Current Step Error (uA) Input-Referred Noise Current (pArms) in 20-Hz Bandwidth 60 52 48 44 40 36 32 28 60 40 20 0 24 20 ±20 3 4 5 6 7 Internal Clock Frequency (MHz) RF = 250 kΩ PRF = 100 Hz 0 ADC averaging = 1 150 200 250 300 C025 TX_REF = 0.25 V Figure 30. Transmitter DAC Current Step Error 25 Input-Referred Noise Current (pArms) in 20-Hz Bandwidth 116 SNR (dBFS) in 20-Hz Bandwidth 100 DAC Current Setting Code Figure 29. Receiver Input-Referred Noise Current vs Internal Clock Frequency 112 108 TX_REF = 0.25 V 104 TX_REF = 0.5 V 100 TX_REF = 0.75 V TX_REF = 1 V 96 TX_REF = 0.25 V TX_REF = 0.5 V 20 TX_REF = 0.75 V TX_REF = 1 V 15 10 5 0 0 5 10 15 20 25 Duty Cycle (%) 0 15 20 25 C028 Figure 32. Input Referred Noise Current in 20-Hz BW vs Duty Cycle (TX_REF Voltage with Tx-Rx Loopback) 30 50 25 Number of Occurances 60 40 30 Actual current Expected current - 2 % 10 10 Duty Cycle (%) PRF = 500 Hz DAC current is set such that ADC output is 50 %FS Figure 31. SNR in 20-Hz BW vs Duty Cycle (TX_REF Voltage with Tx-Rx Loopback) 20 5 C027 PRF = 500 Hz DAC current is set such that ADC output is 50 %FS LED Current (mA) 50 C029 20 15 10 5 Expected current + 2 % 0 0 0 50 100 150 200 250 DAC Current Setting Code 45 46 47 LED current = 48 mA Figure 33. Transmitter Current linearity 48 49 LED Current (mA) C024 TX_REF = 0.25 V 18 44 300 50 51 52 C031 100 devices on tester Figure 34. Transmitter Current Across Devices Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Typical Characteristics (continued) At PRF = 100 Hz, 25% duty cycle, RF = 500 kΩ, CF is adjusted to keep TIA time constant at 1/10th of sampling duration, All supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector CIN = 50 pF, TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless otherwise noted. 100 DAC setting = 50 codes LED Current (mA) 80 DAC setting = 75 codes DAC setting = 100 codes 60 40 20 0 0.25 0.5 0.75 TX_REF (V) 1 C026 Figure 35. Transmitter Current vs TX_REF Voltage (Multiple DAC Settings) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 19 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8 Detailed Description 8.1 Overview The AFE4403 is a complete analog front-end (AFE) solution targeted for pulse oximeter applications. The device consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also integrated that functions from an external crystal. The device communicates to an external microcontroller or host processor using an SPI interface. The Functional Block Diagram section provides a detailed block diagram for the AFE4403. The blocks are described in more detail in the following sections. BG DNC DNC RX_DIG_SUP RX_ANA_SUP RX_ANA_SUP LED_DRV_SUP LED_DRV_SUP TX_CTRL_SUP 8.2 Functional Block Diagram Device CF Reference +- 1.2V RF + INP + + Filter Stage 2 Gain TIA CPO 4G Buffer ADC INN Digital Filter SPISTE SPI RF SPISIMO SPISOMI SCLK Control CF Photodiode VCM Timing Connector LED_DRV_SUP c TX3 TXN LED Driver AFE_PDN LED Current Control DAC TXP ADC_RDY RESET % DNC(1) DNC(1) 20 Diagonostic Signals Submit Documentation Feedback Diagnostics DIAG_END VSS XOUT XIN CLKOUT RX_DIG_GND RX_DIG_GND RX_ANA_GND RX_ANA_GND RX_ANA_GND LED_DRV_GND LED_DRV_GND c LED_DRV_GND OSC TX_REF DNC (1) Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.3 Feature Description 8.3.1 Receiver Channel This section describes the functionality of the receiver channel. 8.3.1.1 Receiver Front-End The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier (TIA) that converts the input photodiode current into an appropriate voltage, as shown in Figure 36. The feedback resistor of the amplifier (RF) is programmable to support a wide range of photodiode currents. Available RF values include: 1 MΩ, 500 kΩ, 250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ. The device is ideally suited as a front-end for a PPG (photoplethysmography) application. In such an application, the light from the LED is reflected (or transmitted) from (or through) the various components inside the body (such as blood, tissue, and so forth) and are received by the photodiode. The signal received by the photodiode has three distinct components: 1. A pulsatile or ac component that arises as a result of the changes in blood volume through the arteries. 2. A constant dc signal that is reflected or transmitted from the time invariant components in the path of light. This constant dc component is referred to as the pleth signal. 3. Ambient light entering the photodiode. The ac component is usually a small fraction of the pleth component, with the ratio referred to as the perfusion index (PI). Thus, the allowed signal chain gain is usually determined by the amplitude of the dc component. Rx SLED2 CONVLED2 LED2 CF RF RG ADC + CPD TIA +Stage 2 Amb SLED2_amb CONVLED2_amb Gain ûADC Buffer SLED1 ADC Output Rate PRF Sa/sec + CONVLED1 LED1 RG RF CF ADC Convert Ambient DAC I-V Amplifier Amb cancellation DAC Amb SLED1_amb ADC Clock CONVLED1_amb Filter Buffer ADC Ambient-cancellation current can be set digitally using SPI interface. Figure 36. Receiver Front-End The RF amplifier and the feedback capacitor (CF) form a low-pass filter for the input signal current. Always ensure that the low-pass filter RC time constant has sufficiently high bandwidth (as shown by Equation 1) because the input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available CF values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used. Rx Sample Time R F ´ CF £ 10 (1) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 21 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Feature Description (continued) The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and 12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage allows for more of the available ADC dynamic range to be used. The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on, the amplifier output is filtered and sampled on capacitor CLED2. Similarly, the LED1 signal is sampled on the CLED1 capacitor when LED1 is on. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to estimate the ambient signal on capacitors CLED2_amb and CLED1_amb. The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx sample time is used for all dynamic range calculations; the minimum time recommended is 50 µs. While the AFE4403 can support pulse widths lower than 50 us, having too low a pulse width could result in a degraded signal and noise from the photodiode. A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions are meant to be staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so on. Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values. The model of the photodiode and the connection to the TIA is shown in Figure 37. CF RF Sensor Model + Iin VTIA- - ADC CIN - VTIA+ + CF RF Figure 37. TIA Block Diagram Iin is the signal current generated by the photodiode in response to the incident light. Cin is the zero-bias capacitance of the photodiode. The current-to-voltage gain in the TIA is given by Equation 2: VTIA (diff) = VTIA+ – VTIA– = 2 × Iin × RF 22 (2) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Feature Description (continued) For example, for a photodiode current of Iin = 1 µA and a TIA gain setting of RF = 100 kΩ, the differential output of the TIA is equal to 200 mV. The TIA has an operating range of ±1 V, and the ADC has an input full-scale range of ±1.2 V (the extra margin is to prevent the ADC from saturating while operating the TIA at the fullest output range). Furthermore, because the PPG signal is one-sided, only one half of the full-scale is used. TI recommends operating the device at a dc level that is not more than 50% to 60% of the ADC full-scale. The margin allows for sudden changes in the signal level that might saturate the signal chain if operating too close to full-scale. Signal levels are shown in Figure 38: +1.2 V ADC max (Differential) +1 V TIA max (Differential) +0.6 V Ideal Operating Point 0V TIA min (Differential) -1 V ADC min (Differential) -1.2 V Figure 38. Signal Levels in TIA and ADC On startup, a gain calibration algorithm running on the microcontroller unit (MCU) can be used to monitor the dc level and adjusts the LED current and TIA gain to get close to the target dc level. In addition to a target dc level, a high and low threshold (for example 80% and 20% of full-scale) can be determined that can cause the algorithm to switch to a different TIA gain or LED current setting when the signal amplitude changes beyond these thresholds. In heart rate monitoring (HRM) applications demanding small-form factors, the sensor size can be so small (and the signal currents so low) that they do not occupy even 50% of full-scale even with the highest TIA gain setting of 1 MΩ, which is the case for signal currents that are less than 300 nA. As such, experimentation with various use cases is essential in order to determine the optimal target value, as well as high and low thresholds. Also, by enabling the stage 2 and introducing additional gain (up to 12 dB), a few extra decibels of SNR can be achieved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 23 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Feature Description (continued) 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block The receiver provides digital samples corresponding to ambient duration. The host processor (external to the AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then set the value of the ambient cancellation DAC using the SPI, as shown in Figure 39. Device Host Processor LED2 Data ADC Output Rate PRF Samples per Second Ambient (LED2) Data Front End (LED2 ± Ambient) Data SPI Interface ADC Rx Digital SPI Block LED1 Data Ambient Estimation Block Ambient information is available in the host processor. The processor can: * Read ambient data Ambient (LED1) Data * Estimate ambient value to be cancelled * Set the value to be used by the ambient cancellation DAC using the SPI of AFE (LED1 ± Ambient) Data Digital Control for Ambient-Cancellation DAC Figure 39. Ambient Cancellation Loop (Closed by the Host Processor) 24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Feature Description (continued) Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth component of the received signal; see Figure 40. The amplifier gain is programmable to 0 dB, 3.5 dB, 6 dB, 9.5 dB, and 12 dB. ICANCEL Cf Rg Rf IPLETH + IAMB Ri Rx VDIFF Ri Rf Rg ICANCEL Cf Value of ICANCEL set using the SPI interface. Figure 40. Front-End (I-V Amplifier and Cancellation Stage) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 25 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Feature Description (continued) The differential output of the second stage is VDIFF, as given by Equation 3: RF RF + IAMB ´ - ICANCEL ´ RG VDIFF = 2 ´ IPLETH ´ RI RI where: • • • • RI = 100 kΩ, IPLETH = photodiode current pleth component, IAMB = photodiode current ambient component, and ICANCEL = the cancellation current DAC value (as estimated by the host processor). (3) RG values with various gain settings are listed in Table 1. Table 1. RG Values GAIN RG(kΩ) 0 (x1) 100 3.5 (x1.5) 150 6 (x2) 200 9.5 (x3) 300 12 (x4) 400 8.3.1.3 Receiver Control Signals LED2 sample phase (SLED2 or SR): When this signal is high, the amplifier output corresponds to the LED2 ontime. The amplifier output is filtered and sampled into capacitor CLED2. To avoid settling effects resulting from the LED or cable, program SLED2 to start after the LED turns on. This settling delay is programmable. Ambient sample phase (SLED2_amb or SR_amb): When this signal is high, the amplifier output corresponds to the LED2 off-time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and sampled into capacitor CLED2_amb. LED1 sample phase (SLED1 or SIR): When this signal is high, the amplifier output corresponds to the LED1 ontime. The amplifier output is filtered and sampled into capacitor CLED1. To avoid settling effects resulting from the LED or cable, program SLED1 to start after the LED turns on. This settling delay is programmable. Ambient sample phase (SLED1_amb or SIR_amb): When this signal is high, the amplifier output corresponds to the LED1 off-time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and sampled into capacitor CLED1_amb. LED2 convert phase (CONVLED2 or CONVR): When this signal is high, the voltage sampled on CLED2 is buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample. Ambient convert phases (CONVLED2_amb or CONVR_amb, CONVLED1_ambor CONVIR_amb): When this signal is high, the voltage sampled on CLED2_amb (or CLED1_amb) is buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code corresponding to the ambient sample. LED1 convert phase (CONVLED1 or CONVIR): When this signal is high, the voltage sampled on CLED1 is buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample. 8.3.1.4 Receiver Timing See Figure 41 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and the ADC conversion times for each channel. Figure 41 shows the timing for a case where each phase occupies 25% of the pulse repetition period. However, this percentage is not a requirement. In cases where the device is operated with low pulse repetition frequency (PRF) or low LED pulse durations, the active portion of the pulse repetition period can be reduced. Using the dynamic power-down feature, the overall power consumption can be significantly reduced. 26 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Red LED ON signal xxx xxx xxxxxxxxxxxx xxx xxx TLED LED ON time <= 0.25T IR LED ON signal N+1 Plethysmograph signal N+2 Photo-diode current Or I-V output pulses N N N+1 Ambient level (dark level) Rx sample time = TLED ± settle time SR, Sample Red SR_amb, Sample Ambient (red phase) SIR, Sample IR SIR_amb, Sample Ambient (IR phase) CONVIR_amb, Convert ambient sample (IR phase) xx xxx xxxx xxxxx xxxxx xxxxx xxx xxx xx xx xx xx CONVR, Convert red sample CONVR_amb, Convert ambient sample (red phase) CONVIR, Convert IR sample 1.0T Convert Ambient Sample N+1 Convert IR Sample N+1 Convert Ambient Sample N+1 Convert Red Sample N+1 0.75T Convert IR Sample N 0.50T Pulse repetition period T = 1/PRF Convert Ambient Sample N xx xx xx Convert Ambient Sample N Convert Red Sample N Convert Ambient Sample N-1 0T 0.25T ADC Conversion TCONV Convert Red Sample N-1 Sample phase ± input current is converted to an analog voltage. Sample phase width is variable from 0 to 25% duty cycle Convert phase ± sampled analog voltage is converted to a digital code NOTE: Relationship to the AFE4403 EVM is: LED1 = IR and LED2 = RED. Figure 41. Rx Timing Diagram Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 27 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8.3.2 Clocking and Timing Signal Generation The crystal oscillator generates a master clock signal using an external crystal. In the default mode, a divide-by-2 block converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller. The clocking functionality is shown in Figure 42. Timer Module Divideby-2 ADC Diagnostics Module Oscillator XIN XOUT CLKOUT 4 MHz 8-MHz Crystal Figure 42. AFE Clocking 28 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 To enable flexible clocking, the AFE4403 has a clock divider with programmable division ratios. While the default division ratio is divide-by-2, the clock divider can be programmed to select between ratios of 1, 2, 4, 6, 8, or 12. The division ratio should be selected based on the external clock input frequency such that the divided clock has a frequency close to 4 MHz. For this reason, CLKOUT is referred as a 4-MHz clock in this document. When operating with an external clock input, the divider is reset based on the RESET rising edge. Figure 43 shows the case where the divider ratio is set to divide-by-2. Tres_setup CLK input (on XIN) RESET CLKOUT Figure 43. Clock Divider Reset The device supports both external clock mode as well as an internal clock mode with external crystal. In the external clock mode, an external clock is input on the XIN pin and the device internally generates the internal clock (used by the timing engine and the ADC) by a programmable division ratio. After division, the internal clock should be within a range of 4 MHz to 6 MHz. The exact frequency of this divided clock is one of the pieces of information required to establish the heart rate being measured from the pulse data. In internal clock mode, an external crystal (connected between XIN and XOUT) is used to generate the clock. To generate sustained oscillations, the oscillator within the AFE provides negative resistance to cancel out the ESR of the crystal. A good rule of thumb is to limit the ESR of the crystal to less than a third of the negative resistance achievable by the oscillator. Figure 44 shows the connection of Crystal to AFE4403. OSCILLATOR XIN XOUT C2 C1 8 MHz crystal (Csh, ESR) Figure 44. Connection of Crystal to AFE4403 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 29 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com In Figure 44 the crystal is characterized by a capacitance, Csh (shunt capacitance of the crystal) and an equivalent series resistance (ESR). C1 and C2 are external capacitors added at the XIN and XOUT pins. The negative resistance achievable from the internal oscillator is given by Equation 4: R = –1 / (2 × ω × Csh × [1 + Csh / CL]) where • • • • CL = (C1 × C2) / (C1 + C2), ω is the frequency of oscillation in rads, Csh is the shunt capacitor of the crystal, and C1, C2 are the capacitors to ground from the XIN, XOUT pins. A value of approximately 15 pF is recommended for C1, C2. (4) For example, with Csh = 8 pF, C1 = C2 = 15 pF, and a frequency of 8 MHz, the result is Equation 5: R = –600 Ω (5) Thus, the crystal ESR is limited to less than approximately 200 Ω. TI highly recommends that a single clock source be used to generate the clock required by the AFE as well as the clock needed by the microcontroller (MCU). If an independent clock source is used by the MCU, then any energy coupling into the AFE supply or ground or input pins can cause aliased spurious tones close to the heart rate being measured. To enable operation with the single clock source between the AFE and the MCU, two options are possible: 1. AFE clock as master: The AFE uses a crystal to generate its clock. CLKOUT from the AFE is used as the input clock for the MCU. 2. MCU clock as master: The AFE operates with an external clock provided by the MCU. Note that the switching of CLKOUT consumes power. Thus, if CLKOUT is not used, it can be shut off using the CLKOUT_TRI bit. 8.3.3 Timer Module See Figure 45 for a timing diagram detailing the various timing edges that are programmable using the timer module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit counter (running off of the 4-MHz clock) to set the time-base. All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to 0. 30 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 LED2(Red LED) ON signal tLED LED On-Time d 0.25 T LED1(IR LED) ON signal Rx Sample Time = tLED ± Settling Time SLED2_amb, Sample Ambient (LED2(Red) phase) SLED1, Sample LED1(IR) SLED1_amb, Sample Ambient (LED1(IR) phase) SLED2, Sample LED2(Red) CONVLED2, Convert LED2(Red) sample CONVLED2_amb, Convert ambient sample (LED2(Red) phase) CONVLED1, Convert LED1(IR) sample CONVLED1_amb, Convert ambient sample (LED1(IR) phase) ADC Conversion ADC Reset 1.0 T 0.75 T 0.50 T 0.25 T 0T ADC_RDY Pin Pulse Repetition Period (PRP) T = 1 / PRF NOTE: Programmable edges are shown in blue and red. Figure 45. AFE Control Signals Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 31 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com For the timing signals in Figure 41, the start and stop edge positions are programmable with respect to the PRF period. Each signal uses a separate timer compare module that compares the counter value with preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI interface. After the counter value has exceeded the stop reference value, the output signal is set. When the counter value equals the stop reference value, the output signal is reset. Figure 46 shows a diagram of the timer compare register. With a 4-MHz clock, the edge placement resolution is 0.25 µs. Set Output Signal Reset START STOP Start Reference Register Counter Input Stop Reference Register Enable Timer Compare Register Figure 46. Compare Register Enable Reset The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four sets of start and stop registers to control the ADC conversion signal, as shown in Figure 47. Reset CLKIN 16-Bit Counter Reset Counter Enable RED LED S Start R Stop Timer Compare 16-Bit Register 1 En IR LED SR Sample RED SIR Sample IR SR_amb, Sample Ambient (red phase) SIR_amb, Sample Ambient (IR phase) S Start R Stop S Start R Stop S Start R Stop S Start R Stop S Start R Stop Timer Compare 16-Bit Register 2 Timer Compare 16-Bit Register 3 Timer Compare 16-Bit Register 4 Timer Compare 16-Bit Register 5 Timer Compare 16-Bit Register 6 En En En En En En En PRF Pulse Timer Compare 16-Bit PRF Register En En Timer Compare 16-Bit Register 7 Start S Stop R Timer Compare 16-Bit Register 8 Start S Stop R Timer Compare 16-Bit Register 9 Start S Stop R Timer Compare 16-Bit Register 10 Start S Stop R CONVR, Convert RED Sample CONVIR, Convert IR Sample CONVIR_amb, Convert Ambient Sample (IR Phase) CONVR_amb, Convert Ambient Sample (RED Phase) START-A STOP-A En START-B STOP-B Timer Compare 16-Bit Register 11 START-C STOP-D En ADC Conversion START-D STOP-D Timer Module Figure 47. Timer Module 8.3.3.1 Using the Timer Module The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles. These timing instants and the corresponding registers are listed in Table 2. 32 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Note that the device does not restrict the values in these registers; thus, the start and end edges can be positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration of one clock cycle. The following steps describe the timer sequencing configuration: 1. With respect to the start of the PRP period (indicated by timing instant t0 in Figure 48), the following sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1 ambient. 2. Also, starting from t0, the sequence of sampling instants must be staggered with respect to the respective conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2. 3. Finally, align the edges for the two LED pulses with the respective sampling instants. Table 2. Clock Edge Mapping to SPI Registers TIME INSTANT (See Figure 48 and Figure 49) (1) (1) (2) (3) DESCRIPTION CORRESPONDING REGISTER ADDRESS AND REGISTER BITS EXAMPLE (2) (Decimal) t0 Start of pulse repetition period No register control — t1 Start of sample LED2 pulse LED2STC[15:0], register 01h 6050 t2 End of sample LED2 pulse LED2ENDC[15:0], register 02h 7998 t3 Start of LED2 pulse LED2LEDSTC[15:0], register 03h 6000 t4 End of LED2 pulse LED2LEDENDC[15:0], register 04h 7999 t5 Start of sample LED2 ambient pulse ALED2STC[15:0], register 05h t6 End of sample LED2 ambient pulse ALED2ENDC[15:0], register 06h 1998 t7 Start of sample LED1 pulse LED1STC[15:0], register 07h 2050 t8 End of sample LED1 pulse LED1ENDC[15:0], register 08h 3998 t9 Start of LED1 pulse LED1LEDSTC[15:0], register 09h 2000 t10 End of LED1 pulse LED1LEDENDC[15:0], register 0Ah 3999 t11 Start of sample LED1 ambient pulse ALED1STC[15:0], register 0Bh 4050 t12 End of sample LED1 ambient pulse ALED1ENDC[15:0], register 0Ch 5998 t13 Start of convert LED2 pulse LED2CONVST[15:0], register 0Dh Must start one AFE clock cycle after the ADC reset pulse ends. t14 End of convert LED2 pulse LED2CONVEND[15:0], register 0Eh 1999 t15 Start of convert LED2 ambient pulse ALED2CONVST[15:0], register 0Fh Must start one AFE clock cycle after the ADC reset pulse ends. 2004 t16 End of convert LED2 ambient pulse ALED2CONVEND[15:0], register 10h 3999 t17 Start of convert LED1 pulse LED1CONVST[15:0], register 11h Must start one AFE clock cycle after the ADC reset pulse ends. 4004 t18 End of convert LED1 pulse LED1CONVEND[15:0], register 12h 5999 t19 Start of convert LED1 ambient pulse ALED1CONVST[15:0], register 13h Must start one AFE clock cycle after the ADC reset pulse ends. 6004 t20 End of convert LED1 ambient pulse ALED1CONVEND[15:0], register 14h 7999 t21 Start of first ADC conversion reset pulse ADCRSTSTCT0[15:0], register 15h t22 End of first ADC conversion reset pulse (3) ADCRSTENDCT0[15:0], register 16h t23 Start of second ADC conversion reset pulse ADCRSTSTCT1[15:0], register 17h 2000 t24 End of second ADC conversion reset pulse (3) ADCRSTENDCT1[15:0], register 18h 2003 t25 Start of third ADC conversion reset pulse ADCRSTSTCT2[15:0], register 19h 4000 t26 End of third ADC conversion reset pulse (3) ADCRSTENDCT2[15:0], register 1Ah 4003 t27 Start of fourth ADC conversion reset pulse ADCRSTSTCT3[15:0], register 1Bh 6000 t28 End of fourth ADC conversion reset pulse (3) ADCRSTENDCT3[15:0], register 1Ch 6003 t29 End of pulse repetition period PRPCOUNT[15:0], register 1Dh 7999 50 4 0 3 Any pulse can be set to zero width by making its start value higher than the end value. Values are based off of a pulse repetition frequency (PRF) = 500 Hz and duty cycle = 25%. See Figure 49, note 2 for the effect of the ADC reset time crosstalk. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 33 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com LED2 (RED LED) On Signal t3 LED1 (IR LED) On Signal SLED2_amb, Sample Ambient LED2 (RED) Phase t9 t10 t6 t5 SLED1, Sample LED1 (IR) t7 t8 SLED1_amb, Sample Ambient LED1 (IR) Phase t11 t12 SLED2, Sample LED2 (RED) CONVLED2, Convert LED2 (RED) Sample t4 t1 t2 t14 t13 CONVLED2_amb, Convert Ambient Sample LED2 (RED) Phase t15 t16 CONVLED1, Convert LED1 (IR) Sample t17 t18 CONVLED1_amb, Convert Ambient Sample LED1 (IR) Phase t19 t20 ADC Conversion ADC Reset t23 t21 t22 t0 t27 t25 t24 t26 t28 Pulse Repetition Period (PRP), One Cycle t29 (1) RED = LED2, IR = LED1. (2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28. Figure 48. Programmable Clock Edges(1)(2) 34 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 CONVLED2, Convert LED2 (RED) Sample t14 t13 CONVLED2_amb, Convert Ambient Sample LED2 (RED) Phase t16 t15 CONVLED1, Convert LED1 (IR) Sample t18 t17 CONVLED1_amb, Convert Ambient Sample LED1 (IR) Phase t20 t19 ADC Conversion Two 4-MHz Clock Cycles t21 t23 t22 ADC Reset t0 t25 t24 t27 t28 t26 Pulse Repetition Period (PRP), One Cycle t29 (1) RED = LED2, IR = LED1. (2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t22, t24, t26, and t28. Figure 49. Relationship Between the ADC Reset and ADC Conversion Signals(1)(2) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 35 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8.3.4 Receiver Subsystem Power Path The block diagram in Figure 50 shows the AFE4403 Rx subsystem power routing. Internal LDOs running off RX_ANA_SUP and RX_DIG_SUP generate the 1.8-V supplies required to drive the internal blocks. The two receive supplies could be shorted to a single supply on the board. 1.8 V RX_ANA_SUP RX_ANA_SUP to 1.8-V Regulator Rx Analog Modules RX_DIG_SUP RX_DIG_SUP to 1.8-V Regulator 1.8 V Rx I/O Block Rx Digital I/O Pins Device Figure 50. Receive Subsystem Power Routing 8.3.5 Transmit Section The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. The RED and IR LED reference currents can be independently set. The current source (ILED) locally regulates and ensures that the actual LED current tracks the specified reference. The transmitter section uses an internal 0.25-V reference voltage for operation. This reference voltage is available on the TX_REF pin and must be decoupled to ground with a 2.2-μF capacitor. The TX_REF voltage is derived from the TX_CTRL_SUP. The TX_REF voltage can be programmed from 0.25 V to 1 V. A lower TX_REF voltage allows a lower voltage to be supported on LED_DRV_SUP. However, the transmitter dynamic range falls in proportion to the voltage on TX_REF. Thus, a TX_REF setting of 0.5 V gives a 6-dB lower transmitter dynamic range as compared to a 1-V setting on TX_REF, and a 6-dB higher transmitter dynamic range as compared to a 0.25-V setting on TX_REF. Note that reducing the value of the band-gap reference capacitor on the BG pin reduces the time required for the device to wake-up and settle. However, this reduction in time is a trade-off between wake-up time and noise performance.For example, reducing the value of the capacitors on the BG and TX_REF pins from 2.2 uF to 0.1 uF reduces the wake-up time (from complete power-down) from 1000 ms to 100 ms, but results in a few decibels of degradation in the transmitter dynamic range. The minimum LED_DRV_SUP voltage required for operation depends on: • Voltage drop across the LED (VLED), • Voltage drop across the external cable, connector, and any other component in series with the LED (VCABLE), and • Transmitter reference voltage. See the Recommended Operating Conditions table for further details. Two LED driver schemes are supported: • An H-bridge drive for a two-terminal back-to-back LED package; see Figure 51. • A push-pull drive for a three-terminal LED package; see Figure 52. 36 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 LED_DRV_SUP TX_CTRL_SUP External Supply Tx CBULK H-Bridge LED2_ON H-Bridge Driver LED1_ON LED2_ON or LED1_ON LED2 Current Reference ILED LED Current Control 8-Bit Resolution LED1 Current Reference Register LED2 Current Reference Register LED1 Current Reference Figure 51. Transmit: H-Bridge Drive Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 37 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com TX_CTRL_SUP External Supply LED_DRV_SUP CBULK Tx LED2_ON H-Bridge Driver LED1_ON LED2_ON or LED1_ON LED2 Current Reference ILED LED Current Control 8-Bit Resolution LED1 Current Reference Register RED Current Reference Register IR Current Reference Figure 52. Transmit: Push-Pull LED Drive for Common Anode LED Configuration 38 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.3.5.1 Third LED Support A third LED can be optionally connected on the TX3 pin, as shown in Figure 53. An example application involving a third LED is where the Red and IR LEDs are connected on the TXP, TXN pins for pulse oximeter applications and a third LED (for example a Green LED) is connected on the TX3 pin for a heart rate monitoring application. The third LED can be connected only in common anode configuration. By programming the TX3_MODE register bit, the timing engine controls on TXP can be transferred to the TX3 pin. In this mode, the register bits that indicate the diagnostic results on the TXP pin now indicate the diagnostic results on the TX3 pin. The selection between using TX3 versus using TXP, TXN is intended as a static mode selection as opposed to a dynamic switching selection. A typical time delay of approximately 20 ms is required for the receive channel to settle after a change to the TX3_MODE setting. During this transition time, the receive signal chain should be active so that the filters are able to settle to the new signal level from the third LED. Figure 53. Multiplexing Third LED Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 39 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8.3.5.2 Transmitter Power Path The block diagram in Figure 54 shows the AFE4403 Tx subsystem power routing. TX_CTRL_SUP Tx Reference and Control LED_DRV_SUP LED Current Control DAC Tx LED Bridge Device Figure 54. Transmit Subsystem Power Routing 8.3.5.3 LED Power Reduction During Periods of Inactivity The diagram in Figure 55 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore, the TIMEREN bit in the CONTROL1 register should be disabled by setting the value to 0. Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 55) inherent to the timer function. The dimmed appearance does not effect the ambient light level measurement because during the ambient cycle, LED_ON is turned off for the duration of the ambient measurement. 1 PA 50 PA 0 mA to 50 mA (See the LEDRANGE bits in the LEDCNTRL register.) LED_ON Figure 55. LED Bias Current 40 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.3.5.4 LED Configurations Multiple LED configurations are possible with the AFE4403. Case 1: Red, IR LEDs in the common anode configuration for SPO2 and a Green LED for the HRM. Figure 56 shows the common anode configuration for this case. Figure 57 shows the configuration for HRM mode. LED_DRV_SUP OFF TX3 Max 100mA RED Max 100mA IR TXM TXP LED1 Controls LED2 Controls LED_DRV_GND Figure 56. SPO2 Application, Common Anode Configuration HRM mode: Set TX3_MODE = 1. LED_DRV_SUP Max 50mA OFF TX3 RED TXP LED2 Controls IR TXM LED1 Controls To disable the IR LED, set LED1 FRQWUROVWRµ0¶. LED_DRV_GND Figure 57. HRM Application Using the Third LED (Optional use of the IR LED) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 41 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Case 2: Red, IR LEDs in an H-bridge configuration for SPO2 and a Green LED for the HRM. The H-bridge configuration for this case is shown in Figure 58. Figure 59 shows the configuration for HRM mode. SPO2 mode: Set TX3_MODE = 0. LED_DRV_SUP LED2 Controls LED1 Controls LED_DRV_SUP IR Max 100mA OFF TXP TXM Max 100mA TX3 RED LED2 Controls LED1 Controls LED_DRV_GND Figure 58. SPO2 Application, H-Bridge Configuration HRM mode: Set TX3_MODE = 1. LED_DRV_SUP LED_DRV_SUP LED1 Controls IR Max 50mA TXM TXP TX3 OFF LED2 Controls RED LED1 Controls To disable the IR LED, set LED1 FRQWUROVWRµ0¶. LED_DRV_GND LED_DRV_GND Figure 59. HRM Application Using the Third LED 42 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Case 3: Driving two LEDs simultaneously for HRM. Some sensor modules have two LEDs on either side of the photodiode to make the illumination more uniform. The two LEDs can be connected in parallel, as shown in Figure 60. The connection shown in Figure 60 results in an equal split of the current between the two LEDs if their forward voltages are exactly matched. High mismatch in the forward voltages of the two LEDs can cause one of them to consume the majority of the current. LED_DRV_SUP TX3 TXP TXM Max 100mA LED2 Controls LED1 Controls LED_DRV_GND Figure 60. Using Two Parallel LEDs for an HRM Application Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 43 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Case 4: Driving two LEDs separated in time for HRM. The two LEDs can also be driven as shown in Figure 61. While this mode of driving the two LEDs does not drive them simultaneously, there are two advantages in this case. First, the full current is available for driving each LED. Secondly, the mismatch in the forward voltages between the two LEDs does not play a role. LED_DRV_SUP TX3 TXM TXP Max 100mA Max 100mA TX3 LED2 Controls LED1 Controls LED_DRV_GND Figure 61. Using Two Parallel LEDs for an HRM Application with Separation in Timing 44 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.4 Device Functional Modes 8.4.1 ADC Operation and Averaging Module After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 49). Each ADC conversion takes 50 µs. The ADC operates with averaging. The averaging module averages multiple ADC samples and reduces noise to improve dynamic range. Figure 62 shows a diagram of the averaging module. The ADC output is a 22-bit code that is obtained by discarding the two MSBs of the 24-bit registers (for example the register with address 2Ah), as shown in Figure 63. Rx Digital ADC Reset ADC 22-Bits ADC Output Rate PRF Samples per Second ADC Register 42 LED2 Data Register 43 LED2_Ambient Data Register 44 LED1 Data Register 45 LED1_Ambient Data LED2 Data Ambient (LED2) Data Averager LED1 Data ADC Reset ADC Convert Ambient (LED1) Data ADC Clock Figure 62. Averaging Module Figure 63. 22-Bit Word 23 22 21 20 10 9 8 19 17 16 15 22-Bit ADC Code, MSB to LSB 7 6 5 4 3 22-Bit ADC Code, MSB to LSB Ignore 11 18 14 13 12 2 1 0 Table 3 shows the mapping of the input voltage to the ADC to its output code. Table 3. ADC Input Voltage Mapping DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT 22-BIT ADC OUTPUT CODE –1.2 V 1000000000000000000000 (–1.2 / 221) V 1111111111111111111111 0 0000000000000000000000 (1.2 / 221) V 0000000000000000000001 1.2 V 0111111111111111111111 The data format is binary twos complement format, MSB-first. Because the TIA has a full-scale range of ±1 V, TI recommends that the input to the ADC does not exceed ±1 V, which is approximately 80% of its full-scale. In cases where having the processor read the data as a 24-bit word instead of a 22-bit word is more convenient, the entire register can be mapped to the input level as shown in Figure 64. Figure 64. 24-Bit Word 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 24-Bit ADC Code, MSB to LSB 8 7 6 5 4 3 2 1 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 0 45 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Table 4 shows the mapping of the input voltage to the ADC to its output code when the entire 24-bit word is considered. Table 4. Input Voltage Mapping DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT 24-BIT ADC OUTPUT CODE –1.2 V 111000000000000000000000 (–1.2 / 221) V 111111111111111111111111 0 000000000000000000000000 (1.2 / 221) V 000000000000000000000001 1.2 V 000111111111111111111111 Now the data can be considered as a 24-bit data in binary twos complement format, MSB-first. The advantage of using the entire 24-bit word is that the ADC output is correct, even when the input is over the normal operating range. 8.4.1.1 Operation Without Averaging In this mode, the ADC outputs a digital sample one time for every 50 µs. Consider a case where the ADC_RDY signals are positioned at 25%, 50%, 75%, and 100% points in the pulse repetition period. At the next rising edge of the ADC reset signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 65): • At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah. • At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh. • At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch. • At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh. At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out. 8.4.1.2 Operation With Averaging In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of the ADC reset signal, the average value (22-bit) is written into the output registers sequentially, as follows (see Figure 66): • At the 25% reset signal, the averaged 22-bit word is written to register 2Ah. • At the 50% reset signal, the averaged 22-bit word is written to register 2Bh. • At the 75% reset signal, the averaged 22-bit word is written to register 2Ch. • At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh. At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out. The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]). The user must specify the correct value for the number of averages, as described in Equation 6: 0.25 ´ Pulse Repetition Period NUMAV[7:0] + 1 = -1 50 ms (6) Note that the 50-µs factor corresponds to a case where the internal clock of the AFE (after division) is exactly equal to 4 MHz. The factor scales linearly with the clock period being used. When the number of averages is 0, the averaging is disabled and only one ADC sample is written to the result registers. Note that the number of average conversions is limited by 25% of the PRF. For example, eight samples can be averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz. 46 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 ADC Conversion ADC Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ADC Reset 25% 0% ADC Data 1 are written into register 42. ADC Data 5 are written into register 43. 0% 75% 50% ADC Data 9 are written into register 44. ADC Data 13 are written into register 45. Register 42 register 43 are written into register 46. Register 44 register 45 are written into register 47. ADC_RDY Pin 0T Pulse Repetition Period (PRP) T = 1 / PRF 1.0 T Figure 65. ADC Data Without Averaging (When Number of Averages = 0) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 47 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com ADC Conversion ADC Data 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ADC Reset 25% 0% Average of ADC data 1 to 3 are written into register 42. Average of ADC data 5 to 7 are written into register 43. 0% 75% 50% Average of ADC data 9 to 11 are written into register 44. Average of ADC data 13 to 15 are written into register 45. Register 42 register 43 are written into register 46. Register 44 register 45 are written into register 47. ADC_RDY Pin Pulse Repetition Period T = 1 / PRF 0T 1.0 T NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2. Figure 66. ADC Data with Averaging Enabled 48 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.4.1.3 Dynamic Power-Down Mode When operated at low PRF, a dynamic power-down mode can be optionally enabled to shut off blocks during a portion of each period. This operation is illustrated in Figure 67. The dynamic power-down signal (called PDN_CYCLE) can be internally generated using the timing controller. PDN_CYCLE can be used to shut off power to internal blocks during the unused section within each pulse repetition period. Pulse repetition period Sample LED2 Sample Ambient 2 Sample LED1 Sample Ambient 1 Convert LED2 Convert Ambient 2 Convert LED1 Convert Ambient 1 PDN_CYCLE t1 t2 Figure 67. Dynamic Power-Down Mode Timing t1 and t2 denote the timing margin between the active portion of the period and the dynamic power-down signal. TI recommends setting t1 > 50 µs and t2 > 200 µs in order to ensure sufficient time for the shutdown blocks to recover from power-down. By choosing the blocks that are shut down during dynamic power-down, a power savings of anywhere between 35% to 70% power can be achieved when the PDN_CYCLE phase is active. The sequence of the convert phases within a pulse repetition period should be as follows: LED2 (Red) → Ambient 2 → LED1 (IR) → Ambient 1. The sample phases must precede the corresponding convert phase. Also note that the ADC_RDY signal comes at the beginning of the pulse repetition period. Thus, the contents of the registers must be read before the completion of the first conversion phase in the pulse repetition period. These contents correspond to the samples of the four phases from the previous pulse repetition period. The DYNAMIC1, DYNAMIC2, DYNAMIC3, and DYNAMIC4 bits determine which blocks are powered down during the dynamic power-down state (when PDN_CYCLE is high). For maximum power saving, all four bits can be set to 1. TI recommends setting t1 to greater than 100 µs and t2 to greater than 200 µs to ensure that the blocks recover from power-down in time for the next cycle. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 49 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com The bit corresponding to the TIA power-down (DYNAMIC3) needs a bit more consideration. When the TIA is powered down, the TIA no longer maintains the bias across the photodiode output. This loss of bias can cause the photodiode output voltage to drift from the normal value. The recovery time constant associated with the photodiode returning to a proper bias condition (when the TIA is powered back on) is approximately equal to 2 × CPD × RF, where CPD is the effective differential capacitance of the photodiode and RF is the TIA gain setting. This consideration might result in a different choice for the value of t2. 8.4.2 Diagnostics The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current profile feedback, and cable on or off detection. 8.4.2.1 Photodiode-Side Fault Detection Figure 68 shows the diagnostic for the photodiode-side fault detection. Internal TX_CTRL_SUP 10 k 10 k 1k Cable Rx On/Off INN To Rx Front-End INP Rx On/Off LED Wires 100 PA PD Wires 100 PA GND Wires Legend for Cable Figure 68. Photodiode Diagnostic 50 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.4.2.2 Transmitter-Side Fault Detection Figure 69 shows the diagnostic for the transmitter-side fault detection. Internal TX_CTRL_SUP SW1 Cable SW3 10 k 10 k TXP D C SW2 SW4 TXN LED Wires 100 PA PD Wires 100 PA GND Wires LED DAC Legend for Cable Figure 69. Transmitter Diagnostic Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 51 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8.4.2.3 Diagnostics Module The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are latched in 11 separate flags. The status of all flags can also be read using the SPI interface. Table 5 details each fault and flag used. Note that the diagnostics module requires all AFE blocks to be enabled in order to function reliably. Table 5. Fault and Flag Diagnostics (1) MODULE SEQ. FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 FLAG8 FLAG9 FLAG10 FLAG11 — — No fault 0 0 0 0 0 0 0 0 0 0 0 1 Rx INP cable shorted to LED cable 1 2 Rx INN cable shorted to LED cable 3 Rx INP cable shorted to GND cable 4 Rx INN cable shorted to GND cable 5 PD open or shorted 1 1 6 Tx OUTM line shorted to GND cable 7 Tx OUTP line shorted to GND cable 8 LED open or shorted 1 1 9 LED open or shorted PD LED (1) 52 FAULT 1 1 1 1 1 1 Resistances below 10 kΩ are considered to be shorted. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 70 shows the timing for the diagnostic function. DIAG_EN Register Bit = 1 Diagnostic State Machine Diagnostic State Machine Diagnostic Ends Diagnostic Starts DIAG_END Pin tDIAG tWIDTH = Four 4-MHz Clock Cycles Figure 70. Diagnostic Timing Diagram By default, the diagnostic function takes tDIAG = 16 ms to complete. After the diagnostics function completes, the AFE4403 filter must be allowed time to settle. See the Electrical Characteristics for the filter settling time. 8.5 Programming 8.5.1 Serial Programming Interface The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data output), SPISIMO (serial interface data input), and SPISTE (serial interface enable). The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts out data from the device. SCLK features a Schmitt-triggered input and clocks data out on the SPISOMI. Data are clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low. The SPI serial out master in (SPISOMI) pin is used with SCLK to clock out the AFE4403 data. The SPI serial in master out (SPISIMO) pin is used with SCLK to clock in data to the AFE4403. The SPI serial interface enable (SPISTE) pin enables the serial interface to clock data on the SPISIMO pin in to the device. 8.5.2 Reading and Writing Data The device has a set of internal registers that can be accessed by the serial programming interface formed by the SPISTE, SCLK, SPISIMO, and SPISOMI pins. 8.5.2.1 Writing Data The SPI_READ register bit must be first set to 0 before writing to a register. When SPISTE is low: • Serially shifting bits into the device is enabled. • Serial data (on the SPISIMO pin) are latched at every SCLK rising edge. • The serial data are loaded into the register at every 32nd SCLK rising edge. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 53 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Programming (continued) In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and the remaining 24 bits form the register data. Figure 71 shows an SPI timing diagram for a single write operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section. SPISTE SPISIMO A7 A6 A1 A0 D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SCLK 'RQ¶WFDUH, can be high or low. Figure 71. AFE SPI Write Timing Diagram 54 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Programming (continued) 8.5.2.2 Reading Data The SPI_READ register bit must be first set to 1 before reading from a register. The AFE4403 includes a mode where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. Figure 72 shows an SPI timing diagram for a single read operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section. SPISTE SPISIMO A7 A6 A1 A0 SPISOMI D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SCLK 'RQ¶WFDUH, can be high or low. (1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE. (2) Specify the register address of the content that must be readback on bits A[7:0]. (3) The AFE outputs the contents of the specified register on the SPISOMI pin. Figure 72. AFE SPI Read Timing Diagram Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 55 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8.5.2.3 Multiple Data Reads and Writes The device includes functionality where multiple read and write operations can be performed during a single SPISTE event. To enable this functionality, the first eight bits determine the register address to be written and the remaining 24 bits determine the register data. Perform two writes with the SPI read bit enabled during the second write operation in order to prepare for the read operation, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. This functionality is described in the Writing Data and Reading Data sections. Figure 73 shows a timing diagram for the SPI multiple read and write operations. SPISTE SPISIMO Second Write(1, 2) First Write Operation A7 A0 D23 D16 D15 D8 D7 D0 A7 A0 D23 D16 D15 Read(3, 4) D8 D7 D0 A7 A0 D23 D16 D15 D8 D7 D0 SPISOMI SCLK 'RQ¶WFDUH, can be high or low (1) The SPI read register bit must be enabled before attempting a serial readout from the AFE. (2) The second write operation must be configured for register 0 with data 000001h. (3) Specify the register address whose contents must be read back on A[7:0]. (4) The AFE outputs the contents of the specified register on the SPISOMI pin. Figure 73. Serial Multiple Read and Write Operations 56 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.5.2.4 Register Initialization After power-up, the internal registers must be initialized to the default values. This initialization can be done in one of two ways: • Through a hardware reset by applying a low-going pulse on the RESET pin, or • By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This setting initializes the internal registers to the default values and then self-resets to 0. In this case, the RESET pin is kept high (inactive). 8.5.2.5 AFE SPI Interface Design Considerations Note that when the AFE4403 is deselected, the SPISOMI, CLKOUT, ADC_RDY, and DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account when connecting multiple devices to the SPI port and for power-management considerations. In order to avoid loading the SPI bus when multiple devices are connected, the SOMI_TRI register bit must be to 1 whenever the AFE SPI is inactive. The DIGOUT_TRISTATE register bit must be set to 1 to tri-state the ADC_RDY and DIAG_END pins. The CLKOUT_TRI register bit must be set to 1 to put the CLKOUT buffer in tri-state mode. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 57 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 8.6 Register Maps 8.6.1 AFE Register Map The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 6. These registers can be accessed using the AFE SPI interface. Table 6. AFE Register Map Dec 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CONTROL0 W 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIAG_EN TIM_COUNT_RST SPI_READ REGISTER DATA Hex SW_RST ADDRESS REGISTER CONTROL (1) NAME LED2STC R/W 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0] LED2ENDC R/W 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0] LED2LEDSTC R/W 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0] LED2LEDENDC R/W 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0] ALED2STC R/W 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0] ALED2ENDC R/W 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0] LED1STC R/W 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0] LED1ENDC R/W 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0] LED1LEDSTC R/W 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0] LED1LEDENDC R/W 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0] ALED1STC R/W 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0] ALED1ENDC R/W 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0] LED2CONVST R/W 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0] LED2CONVEND R/W 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0] ALED2CONVST R/W 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0] ALED2CONVEND R/W 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0] LED1CONVST R/W 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0] LED1CONVEND R/W 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0] ALED1CONVST R/W 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0] ALED1CONVEND R/W 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0] ADCRSTSTCT0 R/W 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0] ADCRSTENDCT0 R/W 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0] ADCRSTSTCT1 R/W 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0] ADCRSTENDCT1 R/W 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0] ADCRSTSTCT2 R/W 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0] ADCRSTENDCT2 R/W 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0] (1) 58 R = read only, R/W = read or write, N/A = not available, and W = write only. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Table 6. AFE Register Map (continued) Dec 23 22 21 20 19 18 17 16 ADCRSTSTCT3 R/W 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0] ADCRSTENDCT3 R/W 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0] PRPCOUNT R/W 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0] CONTROL1 R/W 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEREN SPARE1 N/A 1F 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIAGAIN R/W 20 32 0 0 0 0 0 0 0 0 ENSEPGAN STAGE2EN1 0 0 0 STG2GAIN1[2:0] CF_LED1[4:0] RF_LED1[2:0] TIA_AMB_GAIN R/W 21 33 0 0 0 0 FLTRCNRSEL STAGE2EN REGISTER DATA Hex 0 0 0 STG2GAIN2[2:0] CF_LED[4:0] RF_LED[2:0] LEDCNTRL R/W 22 34 0 0 0 0 0 0 CONTROL2 R/W 23 35 0 0 0 DYNAMIC1 ADDRESS REGISTER CONTROL (1) 0 SPARE2 N/A 24 36 0 0 0 0 0 SPARE3 N/A 25 37 0 0 0 0 0 0 SPARE4 N/A 26 38 0 0 0 0 0 RESERVED1 N/A 27 39 X X X X RESERVED2 N/A 28 40 X X X ALARM R/W 29 41 0 0 0 LED2VAL R 2A 42 LED2VAL[23:0] ALED2VAL R 2B 43 ALED2VAL[23:0] LED1VAL R 2C 44 LED1VAL[23:0] ALED1VAL R 2D 45 ALED1VAL[23:0] LED2-ALED2VAL R 2E 46 LED2-ALED2VAL[23:0] LED1-ALED1VAL R 2F 47 LED1-ALED1VAL[23:0] 14 13 12 LED_RANGE[1:0] AMBDAC[3:0] 15 11 10 9 8 7 6 5 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X 0 0 0 0 0 0 0 0 X X X X X X 0 0 0 0 0 0 0 0 PDNAFE 0 0 0 PDNRX 0 0 0 PDNTX 0 0 0 0 0 DYNAMIC4 0 0 0 0 0 DYNAMIC3 DIGOUT_TRISTATE 0 0 0 1 EN_SLOW_DIAG TXBRGMOD 0 0 0 2 XTALDIS DYNAMIC2 0 TX_REF0 0 0 3 LED2[7:0] 0 0 4 NUMAV[7:0] LED1[7:0] TX_REF1 NAME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 59 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Table 6. AFE Register Map (continued) 17 16 15 14 13 12 11 10 9 8 7 6 5 DIAG R 30 48 0 0 0 0 0 0 0 0 0 0 0 LED_ALM LED2OPEN LED1OPEN LEDSC OUTNSHGND OUTPSHGND PDOC CONTROL3 R/W 31 49 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDNCYCLESTC R/W 32 50 0 0 0 0 0 0 0 0 PDNCYCLESTC[15:0] PDNCYCLEENDC R/W 33 51 0 0 0 0 0 0 0 0 PDNCYCLEENDC[15:0] 60 Submit Documentation Feedback 4 3 2 1 0 INPSCLED 18 INNSCLED 19 INPSCGND 20 INNSCGND 21 CLKOUT_TRI 22 PDSC 23 NAME SOMI_TRI Dec PD_ALM REGISTER DATA Hex TX3_MODE ADDRESS REGISTER CONTROL (1) CLKDIV[2:0] Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 8.6.2 AFE Register Description Figure 74. CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 0 6 17 0 5 16 0 4 0 0 0 0 0 0 0 0 15 0 3 14 0 2 SW_RST DIAG_EN 13 0 1 TIM_ COUNT_ RST 12 0 0 SPI_ READ This register is write-only. CONTROL0 is used for AFE software and count timer reset, diagnostics enable, and SPI read functions. Bits 23:4 Must be 0 Bit 3 SW_RST: Software reset 0 = No action (default after reset) 1 = Software reset applied; resets all internal registers to the default values and self-clears to 0 Bit 2 DIAG_EN: Diagnostic enable 0 = No action (default after reset) 1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set. At the end of the sequence, all fault status are stored in the DIAG: Diagnostics Flag Register. Afterwards, the DIAG_EN register bit self-clears to 0. Note that the diagnostics enable bit is automatically reset after the diagnostics completes (16 ms). During the diagnostics mode, ADC data are invalid because of the toggling diagnostics switches. Bit 1 TIM_CNT_RST: Timer counter reset 0 = Disables timer counter reset, required for normal timer operation (default after reset) 1 = Timer counters are in reset state Bit 0 SPI READ: SPI read 0 = SPI read is disabled (default after reset) 1 = SPI read is enabled Figure 75. LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED2STC[15:0] 16 0 4 15 3 14 13 LED2STC[15:0] 2 1 12 0 This register sets the start timing value for the LED2 signal sample. Bits 23:16 Must be 0 Bits 15:0 LED2STC[15:0]: Sample LED2 start count The contents of this register can be used to position the start of the sample LED2 signal with respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 61 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 76. LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED2ENDC[15:0] 16 0 4 15 3 14 13 LED2ENDC[15:0] 2 1 12 0 This register sets the end timing value for the LED2 signal sample. Bits 23:16 Must be 0 Bits 15:0 LED2ENDC[15:0]: Sample LED2 end count The contents of this register can be used to position the end of the sample LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 77. LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED2LEDSTC[15:0] 16 0 4 15 3 14 13 LED2LEDSTC[15:0] 2 1 12 0 This register sets the start timing value for when the LED2 signal turns on. Bits 23:16 Must be 0 Bits 15:0 LED2LEDSTC[15:0]: LED2 start count The contents of this register can be used to position the start of the LED2 with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 78. LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED2LEDENDC[15:0] 16 0 4 15 3 14 13 LED2LEDENDC[15:0] 2 1 12 0 This register sets the end timing value for when the LED2 signal turns off. Bits 23:16 Must be 0 Bits 15:0 LED2LEDENDC[15:0]: LED2 end count The contents of this register can be used to position the end of the LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 62 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 79. ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED2STC[15:0] 16 0 4 15 3 14 13 ALED2STC[15:0] 2 1 12 0 This register sets the start timing value for the ambient LED2 signal sample. Bits 23:16 Must be 0 Bits 15:0 ALED2STC[15:0]: Sample ambient LED2 start count The contents of this register can be used to position the start of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 80. ALED2ENDC: Sample Ambient LED2 End Count Register (Address = 06h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED2ENDC[15:0] 16 0 4 15 3 14 13 ALED2ENDC[15:0] 2 1 12 0 This register sets the end timing value for the ambient LED2 signal sample. Bits 23:16 Must be 0 Bits 15:0 ALED2ENDC[15:0]: Sample ambient LED2 end count The contents of this register can be used to position the end of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 81. LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED1STC[15:0] 16 0 4 15 3 14 13 LED1STC[15:0] 2 1 12 0 This register sets the start timing value for the LED1 signal sample. Bits 23:17 Must be 0 Bits 16:0 LED1STC[15:0]: Sample LED1 start count The contents of this register can be used to position the start of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 63 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 82. LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED1ENDC[15:0] 16 0 4 15 3 14 13 LED1ENDC[15:0] 2 1 12 0 This register sets the end timing value for the LED1 signal sample. Bits 23:17 Must be 0 Bits 16:0 LED1ENDC[15:0]: Sample LED1 end count The contents of this register can be used to position the end of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 83. LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED1LEDSTC[15:0] 16 0 4 15 3 14 13 LED1LEDSTC[15:0] 2 1 12 0 This register sets the start timing value for when the LED1 signal turns on. Bits 23:16 Must be 0 Bits 15:0 LED1LEDSTC[15:0]: LED1 start count The contents of this register can be used to position the start of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 84. LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED1LEDENDC[15:0] 16 0 4 15 3 14 13 LED1LEDENDC[15:0] 2 1 12 0 This register sets the end timing value for when the LED1 signal turns off. Bits 23:16 Must be 0 Bits 15:0 LED1LEDENDC[15:0]: LED1 end count The contents of this register can be used to position the end of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 64 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 85. ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED1STC[15:0] 16 0 4 15 3 14 13 ALED1STC[15:0] 2 1 12 0 This register sets the start timing value for the ambient LED1 signal sample. Bits 23:16 Must be 0 Bits 15:0 ALED1STC[15:0]: Sample ambient LED1 start count The contents of this register can be used to position the start of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 86. ALED1ENDC: Sample Ambient LED1 End Count Register (Address = 0Ch, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED1ENDC[15:0] 16 0 4 15 3 14 13 ALED1ENDC[15:0] 2 1 12 0 This register sets the end timing value for the ambient LED1 signal sample. Bits 23:16 Must be 0 Bits 15:0 ALED1ENDC[15:0]: Sample ambient LED1 end count The contents of this register can be used to position the end of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 87. LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED2CONVST[15:0] 16 0 4 15 3 14 13 LED2CONVST[15:0] 2 1 12 0 This register sets the start timing value for the LED2 conversion. Bits 23:16 Must be 0 Bits 15:0 LED2CONVST[15:0]: LED2 convert start count The contents of this register can be used to position the start of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 65 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 88. LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED2CONVEND[15:0] 16 0 4 15 3 14 13 LED2CONVEND[15:0] 2 1 12 0 This register sets the end timing value for the LED2 conversion. Bits 23:16 Must be 0 Bits 15:0 LED2CONVEND[15:0]: LED2 convert end count The contents of this register can be used to position the end of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 89. ALED2CONVST: LED2 Ambient Convert Start Count Register (Address = 0Fh, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED2CONVST[15:0] 16 0 4 15 3 14 13 ALED2CONVST[15:0] 2 1 12 0 This register sets the start timing value for the ambient LED2 conversion. Bits 23:16 Must be 0 Bits 15:0 ALED2CONVST[15:0]: LED2 ambient convert start count The contents of this register can be used to position the start of the LED2 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 90. ALED2CONVEND: LED2 Ambient Convert End Count Register (Address = 10h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED2CONVEND[15:0] 16 0 4 15 3 14 13 ALED2CONVEND[15:0] 2 1 12 0 This register sets the end timing value for the ambient LED2 conversion. Bits 23:16 Must be 0 Bits 15:0 ALED2CONVEND[15:0]: LED2 ambient convert end count The contents of this register can be used to position the end of the LED2 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. 66 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 91. LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED1CONVST[15:0] 16 0 4 15 3 14 13 LED1CONVST[15:0] 2 1 12 0 This register sets the start timing value for the LED1 conversion. Bits 23:16 Must be 0 Bits 15:0 LED1CONVST[15:0]: LED1 convert start count The contents of this register can be used to position the start of the LED1 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 92. LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 LED1CONVEND[15:0] 16 0 4 15 3 14 13 LED1CONVEND[15:0] 2 1 12 0 This register sets the end timing value for the LED1 conversion. Bits 23:16 Must be 0 Bits 15:0 LED1CONVEND[15:0]: LED1 convert end count The contents of this register can be used to position the end of the LED1 conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 93. ALED1CONVST: LED1 Ambient Convert Start Count Register (Address = 13h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED1CONVST[15:0] 16 0 4 15 3 14 13 ALED1CONVST[15:0] 2 1 12 0 This register sets the start timing value for the ambient LED1 conversion. Bits 23:16 Must be 0 Bits 15:0 ALED1CONVST[15:0]: LED1 ambient convert start count The contents of this register can be used to position the start of the LED1 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 67 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 94. ALED1CONVEND: LED1 Ambient Convert End Count Register (Address = 14h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ALED1CONVEND[15:0] 16 0 4 15 3 14 13 ALED1CONVEND[15:0] 2 1 12 0 This register sets the end timing value for the ambient LED1 conversion. Bits 23:16 Must be 0 Bits 15:0 ALED1CONVEND[15:0]: LED1 ambient convert end count The contents of this register can be used to position the end of the LED1 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details. Figure 95. ADCRSTSTCT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTSTCT0[15:0] 16 0 4 15 3 14 13 ADCRSTSTCT0[15:0] 2 1 12 0 This register sets the start position of the ADC0 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTSTCT0[15:0]: ADC RESET 0 start count The contents of this register can be used to position the start of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. Figure 96. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTENDCT0[15:0] 16 0 4 15 3 14 13 ADCRSTENDCT0[15:0] 2 1 12 0 This register sets the end position of the ADC0 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTENDCT0[15:0]: ADC RESET 0 end count The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. 68 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 97. ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTSTCT1[15:0] 16 0 4 15 3 14 13 ADCRSTSTCT1[15:0] 2 1 12 0 This register sets the start position of the ADC1 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTSTCT1[15:0]: ADC RESET 1 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. Figure 98. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTENDCT1[15:0] 16 0 4 15 3 14 13 ADCRSTENDCT1[15:0] 2 1 12 0 This register sets the end position of the ADC1 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTENDCT1[15:0]: ADC RESET 1 end count The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details. Figure 99. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTSTCT2[15:0] 16 0 4 15 3 14 13 ADCRSTSTCT2[15:0] 2 1 12 0 This register sets the start position of the ADC2 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTSTCT2[15:0]: ADC RESET 2 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 69 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 100. ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTENDCT2[15:0] 16 0 4 15 3 14 13 ADCRSTENDCT2[15:0] 2 1 12 0 This register sets the end position of the ADC2 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTENDCT2[15:0]: ADC RESET 2 end count The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details. Figure 101. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTSTCT3[15:0] 16 0 4 15 3 14 13 ADCRSTSTCT3[15:0] 2 1 12 0 This register sets the start position of the ADC3 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTSTCT3[15:0]: ADC RESET 3 start count The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details. Figure 102. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 ADCRSTENDCT3[15:0] 16 0 4 15 3 14 13 ADCRSTENDCT3[15:0] 2 1 12 0 This register sets the end position of the ADC3 reset conversion signal. Bits 23:16 Must be 0 Bits 15:0 ADCRSTENDCT3[15:0]: ADC RESET 3 end count The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details. 70 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 103. PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 PRPCOUNT[15:0] 16 0 4 15 3 14 13 PRPCOUNT[15:0] 2 1 12 0 This register sets the device pulse repetition period count. Bits 23:16 Must be 0 Bits 15:0 PRPCOUNT[15:0]: Pulse repetition period count The contents of this register can be used to set the pulse repetition period (in number of clock cycles of the 4-MHz clock). The PRPCOUNT value must be set in the range of 800 to 64000. Values below 800 do not allow sufficient sample time for the four samples; see the Electrical Characteristics table. Figure 104. CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h) 23 0 11 0 22 0 10 0 21 0 9 0 20 0 8 TIMEREN 19 0 7 18 0 6 17 0 5 16 15 0 0 4 3 NUMAV[7:0] 14 0 2 13 0 1 12 0 0 This register configures the clock alarm pin and timer. Bits 23:9 Must be 0 Bit 8 TIMEREN: Timer enable 0 = Timer module is disabled and all internal clocks are off (default after reset) 1 = Timer module is enabled Bits 7:0 NUMAV[7:0]: Number of averages Specify an 8-bit value corresponding to the number of ADC samples to be averaged – 1. For example, to average four ADC samples, set NUMAV[7:0] equal to 3. The maximum number of averages is 16. Any setting of NUMAV[7:0] greater than or equal to a decimal value of 15 results in the number of averages getting set to 16. Figure 105. SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h) 23 0 11 0 22 0 10 0 21 0 9 0 20 0 8 0 19 0 7 0 18 0 6 0 17 0 5 0 16 0 4 0 15 0 3 0 14 0 2 0 13 0 1 0 12 0 0 0 This register is a spare register and is reserved for future use. Bits 23:0 Must be 0 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 71 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 106. TIAGAIN: Transimpedance Amplifier Gain Setting Register (Address = 20h, Reset Value = 0000h) 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 11 0 10 9 STG2GAIN1[2:0] 8 7 6 5 CF_LED1[4:0] 4 15 ENSEP GAIN 3 14 STAGE2 EN1 2 13 12 0 0 1 RF_LED1[2:0] 0 This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values. Bits 23:16 Must be 0 Bit 15 ENSEPGAIN: Enable separate gain mode 0 = The RF, CF values and stage 2 gain settings are the same for both the LED2 and LED1 signals; the values are specified by the bits (RF_LED2, CF_LED2, STAGE2EN2, STG2GAIN2) in the TIA_AMB_GAIN register (default after reset) 1 = The RF, CF values and stage 2 gain settings can be independently set for the LED2 and LED1 signals. The values for LED1 are specified using the bits (RF_LED1, CF_LED1, STAGE2EN1, STG2GAIN1) in the TIAGAIN register, whereas the values for LED2 are specified using the corresponding bits in the TIA_AMB_GAIN register. Bit 14 STAGE2EN1: Enable stage 2 for LED 1 0 = Stage 2 is bypassed (default after reset) 1 = Stage 2 is enabled with the gain value specified by the STG2GAIN1[2:0] bits Bits 13:11 Must be 0 Bits 10:8 STG2GAIN1[2:0]: Program stage 2 gain for LED1 000 = 0 dB, or linear gain of 1 (default after reset) 001 = 3.5 dB, or linear gain of 1.5 010 = 6 dB, or linear gain of 2 011 = 9.5 dB, or linear gain of 3 Bits 7:3 100 101 110 111 = = = = 12 dB, or linear gain of 4 Do not use Do not use Do not use CF_LED1[4:0]: Program CF for LED1 00000 = 5 pF (default after reset) 00001 = 5 pF + 5 pF 00010 = 15 pF + 5 pF 00100 = 25 pF + 5 pF 01000 = 50 pF + 5 pF 10000 = 150 pF + 5 pF Note that any combination of these CF settings is also supported by setting multiple bits to 1. For example, to obtain CF = 100 pF, set bits 7:3 = 01111. Bits 2:0 RF_LED1[2:0]: Program RF for LED1 000 001 010 011 72 = = = = 500 kΩ (default after reset) 250 kΩ 100 kΩ 50 kΩ 100 101 110 111 Submit Documentation Feedback = = = = 25 kΩ 10 kΩ 1 MΩ None Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 107. TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register (Address = 21h, Reset Value = 0000h) 23 22 21 20 0 0 0 0 11 0 10 9 STG2GAIN[2:0] 8 19 18 17 16 15 FLTR CNRSEL 3 AMBDAC[3:0] 7 6 5 CF_LED2[4:0] 4 14 STAGE2 EN2 2 13 12 0 0 1 RF_LED2[2:0] 0 This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner frequency. Bits 23:20 Must be 0 Bits 19:16 AMBDAC[3:0]: Ambient DAC value These bits set the value of the cancellation current. 0000 0001 0010 0011 0100 0101 0110 0111 = = = = = = = = 0 µA (default after reset) 1 µA 2 µA 3 µA 4 µA 5 µA 6 µA 7 µA Bit 15 Must be 0 Bit 14 STAGE2EN2: Stage 2 enable for LED 2 1000 1001 1010 1011 1100 1101 1110 1111 = = = = = = = = 8 µA 9 µA 10 µA Do not Do not Do not Do not Do not use use use use use 0 = Stage 2 is bypassed (default after reset) 1 = Stage 2 is enabled with the gain value specified by the STG2GAIN2[2:0] bits Bits 13:11 Must be 0 Bits 10:8 STG2GAIN2[2:0]: Stage 2 gain setting for LED 2 000 001 010 011 100 101 110 111 Bits 7:3 = = = = = = = = 0 dB, or linear gain of 1 (default after reset) 3.5 dB, or linear gain of 1.5 6 dB, or linear gain of 2 9.5 dB, or linear gain of 3 12 dB, or linear gain of 4 Do not use Do not use Do not use CF_LED[4:0]: Program CF for LEDs 00000 = 5 pF (default after reset) 00001 = 5 pF + 5 pF 00010 = 15 pF + 5 pF 00100 = 25 pF + 5 pF 01000 = 50 pF + 5 pF 10000 = 150 pF + 5 pF Note that any combination of these CF settings is also supported by setting multiple bits to 1. For example, to obtain CF = 100 pF, set D[7:3] = 01111. Bits 2:0 RF_LED[2:0]: Program RF for LEDs 000 001 010 011 = = = = 500 kΩ 250 kΩ 100 kΩ 50 kΩ 100 101 110 111 = = = = 25 kΩ 10 kΩ 1 MΩ None Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 73 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 108. LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h) 23 0 11 22 21 0 0 10 9 LED1[7:0] 20 0 8 19 0 7 18 0 6 17 16 15 LED_RANGE[1:0] 5 4 3 LED2[7:0] 14 13 LED1[7:0] 2 1 12 0 This register sets the LED current range and the LED1 and LED2 drive current. Bits 23:18 Must be 0 Bits 17:16 LED_RANGE[1:0]: LED range These bits program the full-scale LED current range for Tx. Table 7 details the settings. Bits 15:8 LED1[7:0]: Program LED current for LED1 signal Use these register bits to specify the LED current setting for LED1 (default after reset is 00h). The nominal value of the LED current is given by Equation 7, where the full-scale LED current is either 0 mA or 50 mA (as specified by the LED_RANGE[1:0] register bits). Bits 7:0 LED2[7:0]: Program LED current for LED2 signal Use these register bits to specify the LED current setting for LED2 (default after reset is 00h). The nominal value of LED current is given by Equation 8, where the full-scale LED current is either 0 mA or 50 mA (as specified by the LED_RANGE[1:0] register bits). Table 7. Full-Scale LED Current across Tx Reference Voltage Settings (1) LED_RANGE[1: 0] TX_REF = 0.25 V IMAX VHR (2) TX_REF = 1.0 V VHR IMAX VHR IMAX VHR 100 mA 1.1 V Do not use — Do not use — 0.7 V 50 mA 1.0 V 75 mA 1.3 V 100 mA 1.6 V 0.75 V 100 mA 1.1 V Do not use — Do not use — Tx is off — Tx is off — Tx is off — 50 mA 01 25 mA 10 50 mA 11 Tx is off — 0.75 V For a 3-V to 3.6-V supply, use TX_REF = 0.25 or 0.5 V. For a 4.75-V to 5.25-V supply, use TX_REF = 0.75 V or 1.0 V. VHR refers to the headroom voltage (over and above the LED forward voltage and cable voltage drop) needed on the LED_DRV_SUP. The VHR values specified are for the H-bridge configuration. In the common anode configuration, VHR can be lower by 0.25 V. LED1[7:0] 256 LED2[7:0] 256 74 TX_REF = 0.75 V IMAX 00 (default after reset) (1) (2) TX_REF = 0.5 V ´ Full-Scale Current (7) ´ Full-Scale Current (8) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 109. CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h) 23 22 21 0 0 0 11 10 DIGOUT_ TRI STATE 9 TXBRG MOD XTAL DIS 20 DYNAMI C1 8 EN_ SLOW_ DIAG 19 0 18 17 TX_REF1 TX_REF0 16 15 0 0 7 6 5 4 3 0 0 0 DYNAMI C3 DYNAMI C4 14 DYNAMI C2 2 13 12 0 0 1 0 PDNTX PDNRX PDNAFE This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes. Bits 23:21 Must be 0 Bit 20 DYNAMIC1 0 = Transmitter is not powered down during dynamic power-down phase 1 = Transmitter is powered down during dynamic power-down phase Bit 19 Must be 0 Bits 18:17 TX_REF[1:0]: Tx reference voltage These bits set the transmitter reference voltage. This Tx reference voltage is available on the device TX_REF pin. 00 01 10 11 = = = = 0.25-V Tx reference voltage (default value after reset) 0.5-V Tx reference voltage 1.0-V Tx reference voltage 0.75-V Tx reference voltage, D3 Bits 16:15 Must be 0 Bit 14 DYNAMIC2 0 = Part of the ADC is not powered down during dynamic power-down phase 1 = Part of the ADC is powered down during dynamic power-down phase Bit 11 TXBRGMOD: Tx bridge mode 0 = LED driver is configured as an H-bridge (default after reset) 1 = LED driver is configured as a push-pull Bit 10 DIGOUT_TRISTATE: Tri-state bit for the ADC_RDY and DIAG_END pins 0 = ADC_RDY and DIAG_END are not tri-stated 1 = ADC_RDY and DIAG_END are tri-stated Bit 9 XTALDIS: Crystal disable mode 0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and XOUT pins 1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin Bit 8 EN_SLOW_DIAG: Fast diagnostics mode enable 0 = Fast diagnostics mode, 8 ms (default value after reset) 1 = Slow diagnostics mode, 16 ms Bits 7:5 Must be 0 Bit 4 DYNAMIC3 0 = TIA is not powered down during dynamic power-down phase 1 = TIA is powered down during dynamic power-down phase Bit 3 DYNAMIC4 0 = The rest of the ADC is not powered down during dynamic power-down phase 1 = The rest of the ADC is powered down during dynamic power-down phase Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 75 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 Bit 2 www.ti.com PDN_TX: Tx power-down 0 = The Tx is powered up (default after reset) 1 = Only the Tx module is powered down Bit 1 PDN_RX: Rx power-down 0 = The Rx is powered up (default after reset) 1 = Only the Rx module is powered down Bit 0 PDN_AFE: AFE power-down 0 = The AFE is powered up (default after reset) 1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks) Figure 110. SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h) 23 0 11 0 22 0 10 0 21 0 9 0 20 0 8 0 19 0 7 0 18 0 6 0 17 0 5 0 16 0 4 0 15 0 3 0 14 0 2 0 13 0 1 0 12 0 0 0 This register is a spare register and is reserved for future use. Bits 23:0 Must be 0 Figure 111. SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h) 23 0 11 0 22 0 10 0 21 0 9 0 20 0 8 0 19 0 7 0 18 0 6 0 17 0 5 0 16 0 4 0 15 0 3 0 14 0 2 0 13 0 1 0 12 0 0 0 This register is a spare register and is reserved for future use. Bits 23:0 Must be 0 Figure 112. SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h) 23 0 11 0 22 0 10 0 21 0 9 0 20 0 8 0 19 0 7 0 18 0 6 0 17 0 5 0 16 0 4 0 15 0 3 0 14 0 2 0 13 0 1 0 12 0 0 0 13 X 1 X 12 X 0 X This register is a spare register and is reserved for future use. Bits 23:0 Must be 0 Figure 113. RESERVED1: RESERVED1 Register For Factory Use Only (Address = 27h, Reset Value = XXXXh) 23 X (1) 11 X (1) 76 22 X 10 X 21 X 9 X 20 X 8 X 19 X 7 X 18 X 6 X 17 X 5 X 16 X 4 X 15 X 3 X 14 X 2 X X = don't care. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 This register is reserved for factory use. Readback values vary between devices. Figure 114. RESERVED2: RESERVED2 Register For Factory Use Only (Address = 28h, Reset Value = XXXXh) 23 X (1) 11 X (1) 22 X 10 X 21 X 9 X 20 X 8 X 19 X 7 X 18 X 6 X 17 X 5 X 16 X 4 X 15 X 3 X 14 X 2 X 13 X 1 X 12 X 0 X 13 0 1 0 12 0 0 0 X = don't care. This register is reserved for factory use. Readback values vary between devices. Figure 115. ALARM: Alarm Register (Address = 29h, Reset Value = 0000h) 23 0 11 0 22 0 10 0 21 0 9 0 20 0 8 0 19 0 7 0 18 0 6 0 17 0 5 0 16 0 4 0 15 0 3 0 14 0 2 0 This register controls the alarm pin functionality. Bits 23:0 Must be 0 Figure 116. LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h) 23 22 21 20 19 11 10 9 8 7 Bits 23:0 18 17 LED2VAL[23:0] 6 5 LED2VAL[23:0] 16 15 14 13 12 4 3 2 1 0 LED2VAL[23:0]: LED2 digital value This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Figure 117. ALED2VAL: Ambient LED2 Digital Sample Value Register (Address = 2Bh, Reset Value = 0000h) 23 22 21 20 19 11 10 9 8 7 Bits 23:0 18 17 ALED2VAL[23:0] 6 5 ALED2VAL[23:0] 16 15 14 13 12 4 3 2 1 0 ALED2VAL[23:0]: LED2 ambient digital value This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 77 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 118. LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h) 23 22 21 20 19 11 10 9 8 7 Bits 23:0 18 17 LED1VAL[23:0] 6 5 LED1VAL[23:0] 16 15 14 13 12 4 3 2 1 0 LED1VAL[23:0]: LED1 digital value This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Figure 119. ALED1VAL: Ambient LED1 Digital Sample Value Register (Address = 2Dh, Reset Value = 0000h) 23 22 21 20 19 11 10 9 8 7 Bits 23:0 18 17 ALED1VAL[23:0] 6 5 ALED1VAL[23:0] 16 15 14 13 12 4 3 2 1 0 ALED1VAL[23:0]: LED1 ambient digital value This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY signal goes high each time that the contents of this register are updated. The host processor must readout this register before the next sample is converted by the AFE. Figure 120. LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register (Address = 2Eh, Reset Value = 0000h) 23 22 21 20 19 11 10 9 8 7 Bits 23:0 18 17 LED2-ALED2VAL[23:0] 6 5 LED2-ALED2VAL[23:0] 16 15 14 13 12 4 3 2 1 0 LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host processor must readout this register before the next sample is converted by the AFE. Note that this value is inverted when compared to waveforms shown in many publications. Figure 121. LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register (Address = 2Fh, Reset Value = 0000h) 23 22 21 20 19 11 10 9 8 7 Bits 23:0 18 17 LED1-ALED1VAL[23:0] 6 5 LED1-ALED1VAL[23:0] 16 15 14 13 12 4 3 2 1 0 LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted from it. The host processor must readout this register before the next sample is converted by the AFE. Note that this value is inverted when compared to waveforms shown in many publications. 78 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 122. DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h) 23 0 11 LED_ ALM 22 0 10 LED2 OPEN 21 0 9 LED1 OPEN 20 0 8 LEDSC 19 0 7 OUTNSH GND 18 0 6 OUTPSH GND 17 0 5 16 0 4 PDOC PDSC 15 0 3 INNSC GND 14 0 2 INPSC GND 13 0 1 INNSC LED 12 PD_ALM 0 INPSC LED This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin. Bits 23:13 Read only Bit 12 PD_ALM: Power-down alarm status diagnostic flag This bit indicates the status of PD_ALM . 0 = No fault (default after reset) 1 = Fault present Bit 11 LED_ALM: LED alarm status diagnostic flag This bit indicates the status of LED_ALM . 0 = No fault (default after reset) 1 = Fault present Bit 10 LED2OPEN: LED2 open diagnostic flag This bit indicates that LED2 is open. 0 = No fault (default after reset) 1 = Fault present Bit 9 LED1OPEN: LED1 open diagnostic flag This bit indicates that LED1 is open. 0 = No fault (default after reset) 1 = Fault present This bit indicates that LED2 is open. 0 = No fault (default after reset) 1 = Fault present Bit 8 LEDSC: LED short diagnostic flag This bit indicates an LED short. 0 = No fault (default after reset) 1 = Fault present Bit 7 OUTNSHGND: OUTN to GND diagnostic flag This bit indicates that OUTN is shorted to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit 6 OUTPSHGND: OUTP to GND diagnostic flag This bit indicates that OUTP is shorted to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit 5 PDOC: PD open diagnostic flag This bit indicates that PD is open. 0 = No fault (default after reset) 1 = Fault present Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 79 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 Bit 4 www.ti.com PDSC: PD short diagnostic flag This bit indicates a PD short. 0 = No fault (default after reset) 1 = Fault present Bit 3 INNSCGND: INN to GND diagnostic flag This bit indicates a short from the INN pin to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit 2 INPSCGND: INP to GND diagnostic flag This bit indicates a short from the INP pin to the GND cable. 0 = No fault (default after reset) 1 = Fault present Bit 1 INNSCLED: INN to LED diagnostic flag This bit indicates a short from the INN pin to the LED cable. 0 = No fault (default after reset) 1 = Fault present Bit 0 INPSCLED: INP to LED diagnostic flag This bit indicates a short from the INP pin to the LED cable. 0 = No fault (default after reset) 1 = Fault present 80 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Figure 123. CONTROL3: Control Register (Address = 31h, Reset Value = 0000h) 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 0 0 0 0 0 0 0 4 SOMI_ TRI 15 TX3_MO DE 3 CLKOUT _TRI 14 13 12 0 0 0 2 1 0 CLKDIV[2:0] This register controls the clock divider ratio. Bits 23:16 Must be 0 Bit 15 TX3_MODE: Selection of third LED This bit transitions the control from the default two LEDs (on TXP, TXN) to the third LED on TX3. 0 = LEDs on TXP, TXN are active 1 = LED on TX3 is active. Timing engine controls on TXP are transferred to TX3. Maximum current setting supported for the third LED is 50 mA. Bits 14:5 Must be 0 Bit 4 SOMI_TRI: Serial data output 3-state mode This bit determines the state of the SPISOMI output pin. In order to avoid loading the SPI bus when multiple devices are connected, this bit must be set to 1 (3-state mode) whenever the device SPI is inactive. 0 = SPISOMI output buffer is active (normal operation, default) 1 = SPISOMI output buffer is in 3-state mode Bit 3 CLKOUT_TRI: CLKOUT output 3-state mode This bit determines the state of the CLKOUT output pin. 0 = CLKOUT buffer is active (normal operation, default) 1 = CLKOUT buffer is in 3-state mode Bits 2:0 CLKDIV[2:0]: Clock divider ratio These bits set the ratio of the clock divider and determine the frequency of CLKOUT relative to the input clock frequency. Table 8 shows the clock divider ratio settings. Table 8. Clock Divider Ratio Settings (1) (2) CLKDIV[2:0] DIVIDER RATIO INPUT CLOCK FREQUENCY RANGE 000 Divide-by-2 8 MHz to 12 MHz (1) 001 Do not use Do not use 010 Divide-by-4 16 MHz to 24 MHz (1) 011 Divide-by-6 24 MHz to 36 MHz 100 Divide-by-8 32 MHz to 48 MHz 101 Divide-by-12 48 MHz to 60 MHz 110 Do not use Do not use 111 Divide by 1 (2) 4 MHz to 6 MHz These frequency ranges can be used when generating the clock using the crystal. When using divide-by-1, the external clock should have a duty cycle between 48% to 52%. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 81 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Figure 124. PDNCYCLESTC: PDNCYCLESTC Register (Address = 32h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 PDNCYCLESTC[15:0] 16 0 4 15 3 14 13 PDNCYCLESTC[15:0] 2 1 Bits 23:16 Must be 0 Bits 15:0 PDNCYCLESTC[15:0]: Dynamic (cycle-to-cycle) power-down start count 12 0 The contents of this register can be used to position the start of the PDN_CYCLE signal with respect to the pulse repetition period (PRP). The count is specified as the number of cycles of CLKOUT. If the dynamic power-down feature is not required, then do not program this register. Figure 125. PDNCYCLEENDC: PDNCYCLEENDC Register (Address = 33h, Reset Value = 0000h) 23 0 11 22 0 10 21 0 9 20 0 8 19 0 7 18 17 0 0 6 5 PDNCYCLEENDC[15:0] 16 0 4 15 3 14 13 PDNCYCLEENDC[15:0] 2 1 Bits 23:16 Must be 0 Bits 15:0 PDNCYCLEENDC[15:0]: Dynamic (cycle-to-cycle) power-down end count 12 0 The contents of this register can be used to position the end of the PDN_CYCLE signal with respect to the pulse repetition period (PRP). The count is specified as the number of cycles of CLKOUT. If the dynamic power-down feature is not required, then do not program this register. 82 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 9 Application and Implementation 9.1 Application Information The AFE4403 is ideally suited as an analog front-end for processing PPG (photoplethysmography) signals. The information contained in PPG signals can be used for measuring SPO2 as well as for monitoring heart rate. The high dynamic range of the device enables measuring SPO2 with a high degree of accuracy, even under conditions of low perfusion (ac:dc ratio). An SPO2 measurement system involves two different wavelength LEDs: usually Red and IR. By computing the ratio of the ac:dc at the two different wavelengths, SPO2 can be calculated. Heart rate monitoring systems can also benefit from the high dynamic range of the AFE4403, which enables a high-fidelity pulsating signal to be captured, even in cases where the signal strength is low. 9.2 Typical Application Device connections in a typical application is shown in Figure 126. The schematic shows a cabled application in which the LEDs and photodiode are connected to the device through a cable. However, in an application without cables, the LEDs and photodiode can be directly connected to the TXP, TXN, TX3, INP, and INN pins directly. Figure 126. Schematic 9.2.1 Design Requirements An SPO2 application usually involves a Red LED and IR LED. In addition, a heart rate monitoring application can use a different wavelength LED, such as a Green LED. The LEDs can be connected either in the common anode configuration or H-bridge configuration to the TXP, TXN pins. The LED connected to the TX3 pin can only be connected in the common anode configuration. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 83 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure Refer to LED Configurations for different ways to connect the LEDs to the TXP, TXN, and TX3 pins. The photodiode (shown in Figure 127) receives light from both the Red and IR phases and usually has good sensitivities at both these wavelengths. Figure 127. Photodiode The photodiode connected as shown in Figure 127 operates in zero bias because of the negative feedback from the transimpedance amplifier. The signal current generated by the photodiode is converted into a voltage by the transimpedance amplifier, which has a programmable transimpedance gain. The rest of the signal chain then presents a voltage to the ADC. The full-scale output of the transimpedance amplifier is ±1 V and the full-scale input to the ADC is ±1.2 V. An automatic gain control (AGC) loop can be used to set the target dc voltage at the ADC input to approximately 50% of its full-scale. Such an AGC loop can control a combination of the LED current and TIA gain to achieve this target value. 9.2.3 Application Curves This section outlines the trends seen in the Typical Characteristics curves from an application perspective. Figure 5 illustrates the receiver currents in external clock mode with CLKOUT tri-stated. The curve in Figure 5 are taken without the dynamic power-down feature enabled, so much lower currents can be achieved using the dynamic power-down feature. Enabling the crystal mode or removing the CLKOUT tri-state increases the receiver currents from the values depicted in the curve. Figure 6 illustrates the transmitter currents with a zero LED current setting. The average LED current can be computed based on the value of the PRF and LED pulse durations, and can be added to the LED_DRV_SUP current described in Figure 6. Figure 7 illustrates the total receiver current (analog plus digital supply) for different clock divider ratios. For each clock divider ratio, the external clock frequency is swept in frequency such that the divided clock changes between 3 MHz to 7 MHz. Note however that the supported range for the divided clock is 4 MHz to 6 MHz at each division ratio. Also, the external clock should be limited to be between 4 MHz to 60 MHz. Figure 8 illustrates the power savings arising out of the dynamic power-down mode. This mode can be set by defining the start and end points for the signal PDN_CYCLE within the pulse repetition period. In Figure 8, the LED pulse durations are chosen to be 100 µs and the conversions are also chosen to be 100 µs wide. Thus, the entire active period fits in 500 µs. With the timing margins for t1 and t2 indicated in Figure 67, the PDN_CYCLE pulse spans the rest of the pulse repetition period. As PRF reduces, the duty cycle of the PDN_CYCLE pulse (as a fraction of the pulse repetition period) increases, which is the reason for the power reduction at lower PRFs as seen in Figure 8. Figure 9 illustrates the power savings as a function of the PDN_CYCLE duration at a fixed PRF of 100 Hz. A 100-Hz PRF corresponds to a period of 10 ms. Figure 9 indicates the PDN_CYCLE duration swept from 0 ms to 9 ms. With higher durations of PDN_CYCLE, the receiver power reduces. Figure 10 illustrates the baseband response of the switched RC filter for a 5% and 25% duty cycle. When the duty cycle reduces, the effective bandwidth of the filter reduces. 84 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 Typical Application (continued) Figure 128 shows the SNR of the signal chain as a function of the output voltage level. The data are taken by looping back the transmitter outputs to the receiver inputs using an external op amp that converts the transmitter voltage to a receiver input current. The loopback op amp and external resistors are an extra source of noise in this measurement, so the actual noise levels are higher than the total noise of the transmitter plus the receiver. The SNR in this curve (and other curves) is expressed in terms of dBFS, where the full-scale of the channel is used as the reference level. Because the valid operating range of the signal chain is ±1 V, a full-scale of 2 V is used for converting the output noise to a dBFS number. %FS refers to the percentage of the output level as a function of the positive full-scale. For example, a 50 %FS curve corresponds to the case where the output level is 0.5 V. Also, the total noise in this curve is the total integrated noise in the digital output. All noise is contained in the Nyquist band, which extends from –PRF / 2 to PRF / 2. SNR (dBFS) over Nyquist Bandwidth 106 Output voltage = 0 %FS Output voltage = 10 %FS 104 Output voltage = 25 %FS Output voltage = 50 %FS 102 Output voltage = 75 %FS 100 98 96 0 5 10 15 20 Duty Cycle (%) 25 C007 Figure 128. SNR over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback) Figure 129 is a representation of the same data as Figure 10. However, the noise is represented in terms of the input-referred noise current in pArms. By multiplying this number with the TIA gain setting (500 k in this case), the output noise voltage can be computed. Input-Referred Noise Current (pArms) over Nyquist Bandwidth 50 Output voltage = 0 %FS 45 Output voltage = 10 %FS 40 Output voltage = 25 %FS Output voltage = 50 %FS 35 Output voltage = 75 %FS 30 25 20 15 10 0 5 10 15 Duty Cycle (%) 20 25 C006 Figure 129. Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback) Figure 13 illustrates the SNR from the receiver as a function of the sampling duty cycle (which is the sampling pulse duration referred to the pulse repetition period) for different settings of TIA gain. This curve is taken at 100Hz PRF. The maximum duty cycle is limited to 25%. A lower sampling duty cycle also means a lower LED pulse duration duty cycle, which results in power saving. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 85 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Typical Application (continued) Figure 14 illustrates the input-referred noise corresponding to Figure 13. Figure 15 and Figure 16 illustrate the SNR and input-referred noise current in a 0.1-Hz to 20-Hz band for the LED-ambient data. By performing a digital ambient subtraction, the low-frequency noise in the signal chain can be significantly attenuated. The noise levels in the bandwidth of interest are lower than the noise over the full Nyquist bandwidth. For a PPG signal, the signal band of interest is usually less than 10 Hz. By performing some digital low-pass filtering in the processor, this noise reduction can be achieved. Figure 17 and Figure 18 illustrate the noise reduction from ADC averaging. TI therefore recommends setting the number of ADC averages to the maximum allowed at a given PRF. Figure 19 and Figure 20 illustrate the noise at different PRFs over a 20-Hz bandwidth. At a higher PRF, the 20Hz noise band is a smaller fraction of the Nyquist band. Thus, noise is lower at higher PRFs in these figures. Figure 21 and Figure 22 illustrate the noise at different PRFs over a 20-Hz bandwidth with dynamic power-down mode enabled. The active window remains as 500 µs and all samples and conversions are performed at this time. For the rest of the period, the device is in dynamic power-down with the t1 and t2 values as described in Figure 67. Again, the noise reduces with higher PRF. Figure 23 and Figure 24 illustrate the noise as a function of the PDN_CYCLE duration varied from 0 ms to 9 ms, with the active duration (available for conversion) occupying the rest of the period. With higher PDN_CYCLE durations, the number of allowed ADC averages reduces, ehich explains the slight increase in noise at higher PDN_CYCLE durations. Figure 25 and Figure 26 illustrate the noise as a function of temperature over a 20-Hz bandwidth. The measurements are performed with a transmitreceive loopback as explained earlier. The input current is maintained at 1 µA. Thus, for 250-k gain setting, the output voltage is 0.5 V and for a 500-k gain setting, the output voltage is 1 V. Figure 27 and Figure 28 illustrate the noise reduction using additional gain in stage 2. Figure 29 shows the noise as a function of the internal (divided) clock frequency. The external clock is varied from 7 MHz to 14 MHz with a clock division ratio of 2. This range of external clock results in the internal clock varying from 3.5 MHz to 7 MHz. Out of this range, 4 MHz to 6 MHz is the allowed range for the internal (divided) clock at all clock division ratios. Figure 30 illustrates the deviation in the measured LED current with respect to the calculated current when the LED current code is swept from 0 to 255 in steps of 1. Figure 31 and Figure 32 illustrate the transmitter+receiver noise (in external loopback mode) as a function of the TX_REF voltage setting. At lower TX_REF voltages, there is a slight increase in the transmitter noise. This increase is not very apparent from the curves because the transmitter noise is at a level much lower than the total noise. Figure 33 illustrates the transmitter current as a function of the current setting code. Figure 34 illustrates the spread of the transmitter current taken across a large number of devices for the same current setting. Figure 35 illustrates how the LED current changes linearly with the TX_REF voltage for a fixed code. 86 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 10 Power Supply Recommendations The AFE4403 has two sets of supplies: the receiver supplies (RX_ANA_SUP, RX_DIG_SUP) and the transmitter supplies (TX_CTRL_SUP, LED_DRV_SUP). The receiver supplies can be between 2.0 V to 3.6 V, whereas the transmitter supplies can be between 3.0 V to 5.25 V. Another consideration that determines the minimum allowed value of the transmitter supplies is the forward voltage of the LEDs being driven. The current source and switches inside the AFE require voltage headroom that mandates the transmitter supply to be a few hundred millivolts higher than the LED forward voltage. TX_REF is the voltage that governs the generation of the LED current from the internal reference voltage. Choosing the lowest allowed TX_REF setting reduces the additional headroom required but results in higher transmitter noise. Other than for the highest-end clinical SPO2 applications, this extra noise resulting from a lower TX_REF setting can be acceptable. Consider a design where the LEDs are meant to be used in common anode configuration with a current setting of 50 mA. Assume that the LED manufacturer mentions the highest forward voltage of the LEDs is 2.5 V at this current setting. Further, assume that the TX_REF voltage is set to 0.5 V. The voltage headroom required in this case is 1 V. Thus, the LED_DRV_SUP must be driven with a voltage level greater than or equal to 3.5 V (2.5 V plus 1 V). LED_DRV_SUP and TX_CTRL_SUP are recommended to be tied together to the same supply (between 3.0 V to 5.25 V). The external supply (connected to the common anode of the two LEDs) must be high enough to account for the forward drop of the LEDs as well as the voltage headroom required by the current source and switches inside the AFE. In most cases, this voltage is expected to fall below 5.25 V; thus the external supply can be the same as LED_DRV_SUP. However, there may be cases (for instance when two LEDs are connected in series) where the voltage required on the external supply is higher than 5.25 V. Such a case must be handled with care to ensure that the voltage on the TXP and TXN pins remains less than 5.25 V and never exceeds the supply voltage of LED_DRV_SUP, TX_CTRL_SUP by more than 0.3 V. Many scenarios of power management are possible. Case 1: The LED forward voltage is such that a voltage of 3.3 V is acceptable on LED_DRV_SUP. In this case, a single 3.3-V supply can be used to drive all four pins (RX_ANA_SUP, RX_DIG_SUP, TX_CTRL_SUP, LED_DRV_SUP). Care should be taken to provide some isolation between the transmit and receive supplies because LED_DRV_SUP carries the high-switching current from the LEDs. Case 2: A low-voltage supply of 2.2 V is available in the system. In this case, a boost converter can be used to derive the voltage for LED_DRV_SUP, as shown in Figure 130. 2.2-V supply (Connect to RX_ANA, RX_DIG) Boost Converter 3.6 V (Connect to LED_DRV_SUP, TX_CTRL_SUP) Figure 130. Boost Converter The boost converter requires a clock (usually in the megahertz range) and there is usually a ripple at the boost converter output at this switching frequency. While this frequency is much higher than the signal frequency of interest (which is at maximum a few tens of hertz around dc), a small fraction of this switching noise can possibly alias to the low-frequency band. Therefore, TI strongly recommends that the switching frequency of the boost converter be offset from every multiple of the PRF by at least 20 Hz. This offset can be ensured by choosing the appropriate PRF. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 87 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com Case 3: In cases where a high-voltage supply is available in the system, a buck converter or an LDO can be used to derive the voltage levels required to drive RX_ANA and RX_DIG, as shown in Figure 131. 3.9V (Connect to LED_DRV_SUP, TX_CTRL_SUP) 2.2V supply (Connect to RX_ANA/RX_DIG) LDO Figure 131. Buck Converter or an LDO 10.1 Power Consumption Considerations The lowest power consumption mode of the AFE4403 corresponds to the following settings: • PRF = 62.5 Hz, • External clock mode (XTALDIS = 1), and • CLKOUT tri-stated (CLKOUT_TRI = 1). With the above settings, the currents taken from the supplies are as shown in Table 9. The LED driver current is with zero LED current setting. Table 9. Current Consumption in Normal Mode SUPPLY VOLTAGE (V) CURRENT (µA) RX_ANA 2 490 RX_DIG 2 155 TX_CTRL_SUP 3 15 LED_DRV_SUP 3 55 Enabling the crystal (XTALDIS = 0) leads to an additional power consumption that can be estimated to be approximately equal to (2 × Csh + 0.5 × C1 + 0.5 × C2) × 0.4 × fXTAL, where Csh is the effective shunt capacitance of the crystal, C1 and C2 are the capacitances from the XIN and XOUT pins to ground, and fXTAL is the frequency of the crystal. Removing the CLKOUT tri-state leads to an additional power consumption of approximately CLOAD × VSUP × f, where VSUP is the supply voltage of RX_DIG in volts, f = 4 MHz, CLOAD = the capacitive load on the CLKOUT pin + 2 pF. 88 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 The power consumption can be reduced significantly by using the dynamic power-down mode. An illustration of this mode is shown in Table 10, where: • PRF = 62.5 Hz, • Dynamic power-down is active for 14.7 ms every pulse repetition period, • All four bits (DYNAMIC[4:1]) are set to 1, • External clock mode (XTALDIS = 1), and • CLKOUT is tri-stated (CLKOUT_TRI = 1). Table 10. Current Consumption in Dynamic Power-Down Mode SUPPLY VOLTAGE (V) CURRENT (µA) RX_ANA 2 150 RX_DIG 2 155 TX_CTRL_SUP 3 5 LED_DRV_SUP 3 5 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 89 AFE4403 SBAS650B – MAY 2014 – REVISED JULY 2014 www.ti.com 11 Layout 11.1 Layout Guidelines Some key layout guidelines are mentioned below: 1. TXP, TXN, and TX3 are fast-switching lines and should be routed away from sensitive reference lines as well as from the INP, INN inputs. 2. If the INP, INN lines are required to be routed over a long trace, TI recommends that VCM be used as a shield for the INP, INN lines. 3. The device can draw high-switching currents from the LED_DRV_SUP pin. Therefore, TI recommends having a decoupling capacitor electrically close to the pin. 11.2 Layout Example Figure 132. Example Layout 90 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 AFE4403 www.ti.com SBAS650B – MAY 2014 – REVISED JULY 2014 12 Device and Documentation Support 12.1 Trademarks SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: AFE4403 91 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) AFE4403YZPR ACTIVE DSBGA YZP 36 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -20 to 70 AFE4403 AFE4403YZPT ACTIVE DSBGA YZP 36 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -20 to 70 AFE4403 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) AFE4403YZPR DSBGA YZP 36 3000 180.0 8.4 AFE4403YZPT DSBGA YZP 36 250 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.16 3.16 0.71 4.0 8.0 Q1 3.16 3.16 0.71 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE4403YZPR DSBGA YZP 36 3000 182.0 182.0 20.0 AFE4403YZPT DSBGA YZP 36 250 182.0 182.0 20.0 Pack Materials-Page 2 D: Max = 3.07 mm, Min = 3.01 mm E: Max = 3.07 mm, Min = 3.01 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated