Maxim MAX15025BATB+T Single/dual, 16ns, high sink/source current gate driver Datasheet

19-1053; Rev 0; 10/07
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Features
The MAX15024/MAX15025 single/dual, high-speed
MOSFET gate drivers are capable of operating at frequencies up to 1MHz with large capacitive loads. The
MAX15024 includes internal source-and-sink output
transistors with independent outputs allowing for control
of the external MOSFET’s rise and fall time. The
MAX15024 is a single gate driver capable of sinking an
8A peak current and sourcing a 4A peak current. The
MAX15025 is a dual gate driver capable of sinking a 4A
peak current and sourcing a 2A peak current. An integrated adjustable LDO voltage regulator provides gatedrive amplitude control and optimization.
o 8A Peak Sink Current/4A Peak Source Current
(MAX15024)
The MAX15024A/C and MAX15025A/C/E/G accept transistor-to-transistor (TTL) input logic levels while the
MAX15024B/D and MAX15025B/D/F/H accept CMOSinput logic levels. High sourcing/sinking peak currents, a
low propagation delay, and thermally enhanced packages make the MAX15024/MAX15025 ideal for high-frequency and high-power circuits. The MAX15024/
MAX15025 operate from a 4.5V to 28V supply. A separate output driver supply input enhances flexibility and
permits a soft-start of the power MOSFETs used in synchronous rectifiers.
o Independent Source and Sink Outputs (MAX15024)
The MAX15024/MAX15025 are available in 10-pin
TDFN packages and are specified over the -40°C to
+125°C automotive temperature range.
Applications
o 4A Peak Sink Current/2A Peak Source Current
(MAX15025)
o Low 16ns Propagation Delay
o 4.5V to 28V Supply Voltage Range
o On-Board Adjustable LDO for Gate-Drive
Amplitude Control and Optimization
o Separate Output Driver Supply
o Matched Delays Between Inverting and
Noninverting Inputs (MAX15024)
o Matched Delays Between Channels (MAX15025)
o CMOS or TTL Logic-Level Inputs with Hysteresis
for Noise Immunity
o -40°C to +125°C Operating Temperature Range
o Thermal-Shutdown Protection
o 1.95W Thermally Enhanced TDFN Power Packages
Ordering Information
PART
PIN-PACKAGE
Synchronous Rectifier Drivers
Power-Supply Modules
Switching Power Supply
Pin Configurations
REG
DRV
P_OUT
N_OUT
PGND
TOP VIEW
10
9
8
7
6
MAX15024
4
5
IN-
VCC
*EP = EXPOSED PAD.
3
IN+
2
GND
1
FB/SET
EP*
TDFN
Pin Configurations continued at end of data sheet.
PKG
CODE
TOP
MARK
MAX15024AATB+T*
10 TDFN-EP**
T1033-1
ATX
MAX15024BATB+T
10 TDFN-EP**
T1033-1
ATY
MAX15024CATB+T*
10 TDFN-EP**
T1033-1
—
MAX15024DATB+T*
10 TDFN-EP**
T1033-1
—
MAX15025AATB+T
10 TDFN-EP**
T1033-1
ATZ
MAX15025BATB+T*
10 TDFN-EP**
T1033-1
AUA
MAX15025CATB+T*
10 TDFN-EP**
T1033-1
AUB
MAX15025DATB+T*
10 TDFN-EP**
T1033-1
AUC
MAX15025EATB+T*
10 TDFN-EP**
T1033-1
—
MAX15025FATB+T*
10 TDFN-EP**
T1033-1
—
MAX15025GATB+T*
10 TDFN-EP**
T1033-1
—
MAX15025HATB+T* 10 TDFN-EP**
T1033-1
—
Note: All devices are specified over the -40°C to +125°C operating
temperature range.
+Denotes a lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad. T = Tape and reel.
See the Selector Guide at the end of the data sheet.
Block Diagrams appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX15024/MAX15025
General Description
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70°C)
10-Pin TDFN, Single-Layer Board
(derate 18.5mW/°C above +70°C) ...........................1481.5mW
Junction-to-Case Thermal Resistance ............................8.5°C/W
10-Pin TDFN, Multilayer Board
(derate 24.4mW/°C above +70°C) ...........................1951.2mW
Junction-to-Case Thermal Resistance ............................8.5°C/W
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
VCC to GND ............................................................-0.3V to +30V
REG to GND ..............-0.3V to the lower of +22V or (VCC + 0.3V)
DRV to PGND .........................................................-0.3V to +22V
IN_ ..........................................................................-0.3V to +22V
FB/SET to GND.........................................................-0.3V to +6V
P_OUT to DRV ........................................................-22V to +0.3V
N_OUT to PGND.....................................................-0.3V to +22V
OUT1, OUT2 to PGND ..............................-0.3V to (VDRV + 0.3V)
PGND to GND .......................................................-0.3V to +0.3V
P_OUT, N_OUT Continuous Source/Sink Current* .......... 200mA
OUT1, OUT2 Continuous Source/Sink Current*................200mA
*Continuous output current is limited by the power dissipation of the package.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX15024 ELECTRICAL CHARACTERISTICS
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+ 25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
VDRV Turn-On Voltage
VCC
MAX15024B/D
6.5
28.0
MAX15024A/C
4.5
28.0
VCC = VREG = VDRV (MAX15024D)
6.5
18.0
VCC = VREG = VDRV (MAX15024C)
4.5
18.0
V
VCC = VREG = 10V, IN+ = VCC, IN- = GND
1.7
2.3
V
Quiescent Supply Current
IN_ = VCC or GND
700
1350
µA
Quiescent Supply Current
Under UVLO Condition
IN_ = VCC or GND
250
Switching Supply Current
Switching at 250kHz, CL = 0
1.5
3.0
mA
3.4
3.8
V
VCC Undervoltage Lockout
VDRV_ON
VCC powered only, VREG =
VDRV decoupled with
minimum 1µF to GND
UVLO_ VCC
VCC rising
3.0
VCC Undervoltage-Lockout
Hysteresis
µA
300
VCC Undervoltage Lockout to
Output Delay
VCC rising
100
VCC falling
2
mV
µs
REG REGULATOR (VCC = 12V, REG = VDRV, CL = 1µF, FB/SET = GND)
Output Voltage
VREG
Dropout Voltage
VR_DO
10
11
VCC = 6.5V, ILOAD = 100mA
0.4
0.9
VCC = 4.5V, ILOAD = 50mA
0.2
0.5
12V < VCC < 28V, 0 < ILOAD < 10mA
9
V
V
Load Regulation
VCC = 12V, ILOAD = 0 to 100mA
1
%
Line Regulation
12V < VCC < 28V
10
mV
FB/SET Reference Voltage
External resistive divider connected at
FB/SET
FB/SET Threshold
VFB falling
FB/SET Input Leakage Current
VFB = 5.5V (Note 2)
2
1.10
1.23
1.35
220
-125
_______________________________________________________________________________________
V
mV
+125
nA
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+ 25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
TA = +25°C
0.45
0.60
TA = +125°C
0.625
0.850
VCC = VREG = VDRV = 4.5V, TA = +25°C
sinking 100mA
TA = +125°C
(MAX15024C/D)
0.50
0.65
0.7
0.9
UNITS
DRIVER OUTPUT (SINK)
VCC = VREG = VDRV = 10V,
sinking 100mA
Driver Output Resistance
Peak Output Current
RON-N
IPK-N
N_OUT = 10V
SOA condition: CL x VDRV2 ≤ 20µJ,
Maximum Load Capacitance
for VDRV = 10V
Latchup Robustness
Ω
8
A
200
nF
500
mA
DRIVER OUTPUT (SOURCE)
TA = +25°C
0.875
1.500
TA = +125°C
1.2
2.0
VCC = VREG = VDRV = 4.5V, TA = +25°C
sourcing 100mA
TA = +125°C
(MAX15024C/D)
0.95
1.65
1.25
2.20
VCC = VREG = VDRV = 10V,
sourcing 100mA
Driver Output Resistance
Peak Output Current
RON-P
IPK-P
P_OUT = 0V
Latchup Robustness
Ω
4
A
500
mA
LOGIC INPUTS
Logic 1 Input Voltage
VIH
Logic 0 Input Voltage
VIL
Logic Input Hysteresis
Logic Input Current Leakage
MAX15024A/C
2.0
MAX15024B/D
4.25
V
MAX15024A/C
0.8
MAX15024B/D
2
MAX15024A/C
0.4
MAX15024B/D
1
VIN = 18V or GND
-75
Input Capacitance
0.01
V
V
+75
10
µA
pF
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 10V, P_OUT AND N_OUT ARE CONNECTED TOGETHER
(see Figure 1)
Rise Time
tR
Fall Time
tF
CLOAD = 1nF
3
CLOAD = 5nF
12
CLOAD = 10nF
24
CLOAD = 1nF
3
CLOAD = 5nF
8
CLOAD = 10nF
16
ns
ns
Turn-On Delay Time
tD-ON
CLOAD = 1nF (Note 2)
8
16
32
ns
Turn-Off Delay Time
tD-OFF
CLOAD = 1nF (Note 2)
8
16
32
ns
Mismatch Propagation Delays
from Inverting and Noninverting
Inputs to Output
CLOAD = 1nF
1
ns
_______________________________________________________________________________________
3
MAX15024/MAX15025
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+ 25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 4.5V (see Figure 1) (MAX15024C/D)
Rise Time
Fall Time
tR
tF
CLOAD = 1nF
3
CLOAD = 5nF
11
CLOAD = 10nF
22
CLOAD = 1nF
2.5
CLOAD = 5nF
8
CLOAD = 10nF
16
ns
ns
Turn-On Delay Time
tD-ON
CLOAD = 1nF
18
ns
Turn-Off Delay Time
tD-OFF
CLOAD = 1nF
18
ns
CLOAD = 1nF
2
ns
15
ns
+160
°C
15
°C
Mismatch Propagation Delays
from Inverting and Noninverting
Inputs to Output
Minimum Input Pulse Width that
Changes the Output
tPW
THERMAL CHARACTERISTICS
Thermal-Shutdown
Temperature
Temperature rising
Thermal-Shutdown
Temperature Hysteresis
MAX15025 ELECTRICAL CHARACTERISTICS
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
6.5
28
4.5
28
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
VCC
VCC powered only,
MAX15025B/D/F/H
VR = VDRV decoupled
with minimum 1µF
MAX15025A/C/E/G
to GND
VCC = VREG = VDRV (MAX15025F/H)
6.5
18.0
VCC = VREG = VDRV (MAX15025E/G)
4.5
18.0
V
VCC = VREG = 10V, IN1 = VCC, IN2 = VCC
(MAX15025A/B/E/F) or GND for
(MAX15025C/D/G/H)
1.7
2.3
V
Quiescent Supply Current
IN_ = VCC or GND
700
1350
µA
Quiescent Supply Current
Under UVLO Condition
IN_ = VCC or GND
250
VDRV Turn-On Voltage
VDRV_ON
Switching Supply Current
VCC Undervoltage Lockout
4
Switching at 250kHz, CL = 0
UVLO_ VCC
VCC rising
3.0
µA
1.5
3.0
mA
3.4
3.8
V
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
VCC Undervoltage-Lockout
Hysteresis
TYP
MAX
300
VCC Undervoltage Lockout to
Output Delay
VCC rising
100
VCC falling
2
UNITS
mV
µs
REG REGULATOR (VCC = 12V, VREG = VDRV, CL = 1µF, FB/SET = GND)
Output Voltage
VREG
Dropout Voltage
VR_DO
12V < VCC < 28V, 0 < ILOAD < 10mA
10
11
VCC = 6.5V, ILOAD = 100mA
9
0.4
0.9
VCC = 4.5V, ILOAD = 50mA
0.2
0.5
V
V
Load Regulation
VCC = 12V, ILOAD = 0 to 100mA
1
%
Line Regulation
12V < VCC < 28V
10
mV
FB/SET Reference Voltage
External resistive divider connected at
FB/SET
FB/SET Threshold
VFB rising
FB/SET Input Leakage Current
VFB = 5.5V
1.10
1.23
1.35
220
-125
V
mV
+125
nA
DRIVER OUTPUT SINK
VCC = VREG = VDRV = 10V,
sinking 100mA
Driver Output Resistance
Peak Output Current
RON-N
IPK-N
VCC = VREG = VDRV = 4.5V,
sinking 100mA
(MAX15025E/F/G/H)
TA = +25°C
1.0
1.6
TA = +125°C
1.25
2.10
TA = +25°C
1.10
1.65
TA = +125°C
1.5
2.2
OUT_ = 10V
SOA condition: CL x VDRV2 ≤ 20µJ,
Maximum Load Capacitance
for VDRV = 10V
Latchup Robustness
Ω
4
A
100
nF
500
mA
DRIVER OUTPUT SOURCE
VCC = VREG = VDRV = 10V,
sourcing 100mA
Driver Output Resistance
Peak Output Current
RON-P
IPK-P
VCC = VREG = VDRV = 4.5V,
sourcing 100mA
(MAX15025E/F/G/H)
TA = +25°C
1.75
2.50
TA = +125°C
2.25
3.50
TA = +25°C
1.85
2.60
TA = +125°C
2.50
3.75
OUT_ = 0V
Latchup Robustness
Ω
2
A
500
mA
LOGIC INPUTS
Logic 1 Input Voltage
VIH
Logic 0 Input Voltage
VIL
Logic Input Hysteresis
Logic Input Current Leakage
Input Capacitance
MAX15025A/C/E/G
2.0
MAX15025B/D/F/H
4.25
V
MAX15025A/C/E/G
0.8
MAX15025B/D/F/H
2
MAX15025A/C/E/G
0.4
MAX15025B/D/F/H
1
VIN = 18V or GND
-75
+0.01
10
V
V
+75
µA
pF
_______________________________________________________________________________________
5
MAX15024/MAX15025
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(VCC = VDRV = VREG = 10V, FB/SET = GND, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = TJ =
+25°C). (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 10V (see Figure 1)
Rise Time
Fall Time
tR
tF
CLOAD = 1nF
6
CLOAD = 5nF
24
CLOAD = 10nF
48
CLOAD = 1nF
5
CLOAD = 5nF
16
CLOAD = 10nF
ns
ns
32
Turn-On Delay Time
tD-ON
CLOAD = 1nF (Note 2)
8
16
32
ns
Turn-Off Delay Time
tD-OFF
CLOAD = 1nF (Note 2)
8
16
32
ns
Mismatch Propagation Delays
Between 2 Channels
CLOAD = 1nF
1
ns
SWITCHING CHARACTERISTICS FOR VCC = VDRV = VREG = 4.5V (see Figure 1) (MAX15025E/F/G/H)
Rise Time
Fall Time
tR
tF
CLOAD = 1nF
5
CLOAD = 5nF
20
CLOAD = 10nF
42
CLOAD = 1nF
4
CLOAD = 5nF
15
ns
ns
CLOAD = 10nF
30
Turn-On Delay Time
tD-ON
CLOAD = 1nF
18
ns
Turn-Off Delay Time
tD-OFF
CLOAD = 1nF
18
ns
CLOAD = 1nF
2
ns
15
ns
+160
°C
15
°C
Mismatch Propagation Delays
Between 2 Channels
Minimum Input Pulse Width that
Changes the Output
tPW
THERMAL CHARACTERISTICS
Thermal-Shutdown Temperature
Thermal-Shutdown Temperature
Hysteresis
Temperature rising
Note 1: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 2: Design guaranteed by bench characterization. Limits are not production tested.
6
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
FALL TIME vs. SUPPLY VOLTAGE
(WITH 5nF LOAD)
TA = +85°C
20
TA = +25°C
TA = 0°C
10
25
TA = +125°C
TA = +85°C
20
15
TA = -40°C
TA = 0°C
TA = +25°C
18
16
MAX15024/25 toc03
MAX15025
FALL TIME (ns)
RISE TIME (ns)
30
30
MAX15024/25 toc02
MAX15025
TA = +125°C
MAX15024/25 toc01
40
PROPAGATION DELAY TIME
vs. TEMPERATURE (1nF LOAD)
PROPAGATION DELAY TIME (ns)
RISE TIME vs. SUPPLY VOLTAGE
(DUAL DRIVER WITH 5nF LOAD)
RISING
14
12
FALLING
10
8
TA = -40°C
10
0
14
16
18
20
-60 -40 -20 0
20 40 60 80 100 120 140
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(PROGRAMMED EXTERNALLY TO 5V)
SUPPLY CURRENT
vs. LOAD CAPACITANCE
SUPPLY CURRENT
vs. TEMPERATURE
1500
75kHz
100kHz
1000
500
24
SWITCHING
250kHz
18
12
NOT SWITCHING
6
40kHz
4
6
8
1400
SWITCHING
250kHz
1200
1000
800
600
NOT SWITCHING
400
0
0
10 12 14 16 18 20
0
2000
4000
6000
8000
10,000
-40
0
40
80
120
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (nF)
TEMPERATURE (°C)
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE (TTL)
SUPPLY CURRENT
vs. LOGIC IN
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(5nF RISING)
2.5
RISING
2.0
1.5
1.0
FALLING
MAX15024/25 toc09
1600
MAX15024/25 toc08
MAX15024/25 toc07
3.0
INPUT
LOW TO HIGH
1400
SUPPLY CURRENT (µA)
2
VCC = VREG = VDRV = 10V
1600
200
0
0
1800
MAX15024/25 toc06
VCC = VREG = VDRV = 10V
SUPPLY CURRENT (µA)
500kHz
MAX15024/25 toc05
2000
30
SUPPLY CURRENT (mA)
MAX15024/25 toc04
1MHz
SUPPLY CURRENT (µA)
12
SUPPLY VOLTAGE (V)
2500
INPUT THRESHOLD VOLTAGE (V)
6
10
10 11 12 13 14 15 16 17 18 19 20
1200
MAX15025
IN_
1V/div
1000
800
OUT_
5V/div
INPUT
HIGH TO LOW
600
400
0.5
200
0
00
4
8
12
SUPPLY VOLTAGE (V)
16
20
0
1
2
3
4
5
6
20ns/div
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
MAX15024/MAX15025
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(5nF FALLING)
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(10nF FALLING)
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(10nF RISING)
MAX15024/25 toc10
MAX15024/25 toc11
MAX15024/25 toc12
MAX15025
MAX15025
MAX15025
IN_
1V/div
IN_
1V/div
IN_
1V/div
OUT_
5V/div
OUT_
5V/div
20ns/div
20ns/div
PROPAGATION DELAY MISMATCH
vs. TEMPERATURE
LINE REGULATION OF VREG
(PROGRAMMED EXTERNALLY TO 5.04V)
2.5
5.2
10.5
1.5
VREG (V)
5.1
VREG (V)
2.0
LOAD REGULATION OF VREG
11.0
MAX15024/25 toc14
5.3
MAX15024/25 toc13
3.0
MAX15024/25 toc15
20ns/div
5.0
1.0
4.9
0.5
4.8
10.0
9.5
0
9.0
4.7
-40
0
40
120
80
5
10
TEMPERATURE (°C)
15
20
25
0
30
20 40 60 80 100 120 140 160 180 200
LOAD CURRENT (mA)
SUPPLY VOLTAGE
FB/SET CURRENT
vs. TEMPERATURE
FB/SET VOLTAGE
vs. TEMPERATURE
1.236
1.234
MAX15024/25 toc17
1.238
20
FB/SET CURRENT (nA)
MAX15024/25 toc16
1.240
FB/SET VOLTAGE (V)
PROPAGATION DELAY BETWEEN CHANNELS (ns)
OUT_
5V/div
15
10
5
1.232
0
1.230
0
20
40
60
80
TEMPERATURE (°C)
8
100
120
0
20
40
60
80
TEMPERATURE (°C)
_______________________________________________________________________________________
100
120
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
PIN
MAX15024
MAX15025A
MAX15025B
MAX15025E
MAX15025F
MAX15025C
MAX15025D
MAX15025G
MAX15025H
1
1
2
2
NAME
FUNCTION
1
FB/SET
LDO Regulator Output Set. Feedback for VREG adjustment (VFB > 200mV).
Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a
resistor ladder to set VREG.
2
VCC
Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of
1µF. Input of the internal housekeeping regulator and of the main REG
regulator.
3
3
3
GND
Signal Ground
4
—
—
IN+
Driver Noninverting Logic Input. Connect to VCC when not used.
—
4
4
IN1
Driver 1 Noninverting Logic Input
5
—
—
IN-
Driver Inverting Logic Input. Connect to GND when not used.
—
5
—
IN2
Driver 2 Noninverting Logic Input
—
—
5
IN2
Driver 2 Inverting Logic Input
6
6
6
PGND
Power Ground. Sink current return. Source of the internal pulldown
n-channel transistor.
7
—
—
N_OUT
Sink Output. Open-drain n-channel output. N_OUT sinks current for power
MOSFET turn-off.
—
7
7
OUT2
Driver 2 Output
8
—
—
P_OUT
Source Output. Pullup p-channel output (open drain). Sources current for
power MOSFET turn-on.
—
8
8
OUT1
Driver 1 Output
9
9
9
DRV
Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1µF
ceramic capacitor to PGND placed in close proximity to the device. DRV
can be powered independently from REG. Connect DRV, REG, and VCC
together when there is no need for special DRV supply sequencing and
the power-MOSFET gate voltage does not need to be regulated or limited.
10
10
10
REG
Voltage Regulator Output. Connect to DRV for driving the power MOSFET
with regulated VGS amplitude. Bypass with a low-ESR 1µF (minimum)
ceramic capacitor to GND placed in close proximity to the device to
ensure regulator stability.
EP
EP
EP
EP
Exposed Pad. Internally connected to GND. Connect to GND plane or
thermal pad and use multiple vias to a solid copper area on the bottom of
the PCB.
_______________________________________________________________________________________
9
MAX15024/MAX15025
Pin Description
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Detailed Description
The MAX15024 single gate driver’s internal source and
sink transistor outputs are brought out of the IC to independent outputs allowing control of the external
MOSFET’s rise and fall time. The MAX15024 single
gate driver is capable of sinking an 8A peak current
and sourcing a 4A peak current. The MAX15025 dual
gate drivers are capable of sinking a 4A peak current
and sourcing a 2A peak current.
An integrated adjustable low-dropout linear voltage
regulator (LDO) provides gate drive amplitude control
and optimization. The single gate-driver propagation
delay time is minimized and matched between the
inverting and noninverting inputs. The dual gate-driver
propagation delay is matched between channels.
The MAX15024 has a dual input (IN+ and IN-), allows
the use of an inverting or noninverting input, and is
offered in TTL or CMOS-logic standards. The
MAX15025 is offered with configurations of inverting
and noninverting inputs with TTL or CMOS standards
(see the Selector Guide).
The MAX15024A/B and MAX15025A/B/C/D can be powered using VCC only, whereas the MAX15024C/D and
MAX15025E/F/G/H can be used in two configurations:
• VCC powered only
• VCC, REG, and DRV are connected together
LDO Voltage Regulator Feedback Control
The MAX15024/MAX15025 include an internal LDO
designed to deliver a stable reference voltage for use
as a supply voltage for the internal MOSFET gate drivers. Connect the LDO feedback FB/SET to GND to set
VREG to a stable 10V. Connect FB/SET to a resistordivider between VREG and GND to set VREG:
VREG = VFB/SET x (1 + R2 / R1) (see Figure 2)
VCC Undervoltage Lockout
When VCC is below the UVLO threshold, the internal nchannel transistor is ON and the internal p-channel transistor is OFF, holding the output at GND independent of
the state of the inputs so that the external MOSFETs
remain OFF in the UVLO condition. The UVLO threshold is
3.5V (typ) with 200mV (typ) hysteresis to avoid chattering.
When the device is operated at very low temperatures
and below the UVLO threshold, the driver output could
go high impedance. In this case, it is recommended
adding a 10kΩ resistor to PGND to discharge the gate
of the external MOSFET (see Figures 4 and 5).
10
Input Control
The MAX15024 features inverting and noninverting
input terminals. These inputs provide for flexibility of
design and use. Connect IN+ to VCC when using IN- as
an inverting input. Connect IN- to GND when using IN+
as a noninverting input.
Shoot-Through Protection
The MAX15024/MAX15025 provide protection that
avoids any cross-conduction between the internal pchannel and n-channel devices. It also eliminates shootthrough, thus reducing the quiescent supply current.
Exposed Pad (EP)
The MAX15024/MAX15025 include an exposed pad
allowing greater heat dissipation from the internal die to
the outside environment. Solder the exposed pad carefully to GND or thermal pad to enhance the thermal
performance.
Applications Information
Supply Bypassing, Device Grounding,
and Placement
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the
VDRV pin can approach 4A, while at the PGND pin, the
peak current can approach 8A. V DRV drops and
ground shifts are forms of negative feedback for inverters and, if excessive, can cause multiple switching
when the inverting input is used and the input slew rate
is low. The device driving the input should be referenced to the MAX15024/MAX15025 GND. Ground
shifts due to insufficient device grounding can disturb
other circuits sharing the same AC ground return path.
Any series inductance in the VDRV, OUT_, and/or PGND
paths can cause oscillations due to the very high di/dt
that results when the MAX15024/MAX15025 are
switched with any capacitive load. A 0.1µF or larger
value ceramic capacitor is recommended for bypassing VDRV to GND and should be placed as close to the
pins as possible. When driving very large loads
(> 10nF) at minimum rise time, 10µF or more of parallel
storage capacitance is recommended. A ground plane
is highly recommended to minimize ground return resistance and series inductance. Care should be taken to
place the MAX15024/MAX15025 as close as possible to
the external MOSFET being driven to further minimize
board inductance and AC path resistance.
______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Layout Information
The MAX15024/MAX15025 MOSFET drivers source and
sink large currents to create very fast rise and fall edges
at the gate of the switching MOSFET. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. The following
printed-circuit board (PCB) layout guidelines are recommended when designing with the MAX15024/MAX15025:
• Place one or more 1µF decoupling ceramic capacitor(s) from VDRV to PGND as close to the device as
possible. At least one storage capacitor of 10µF (min)
should be located on the PCB with a low resistance
path to the VCC pin of the MAX15024/MAX15025.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from MOSFET gate to
OUT_ of the MAX15024/MAX15025 to PGND of the
MAX15024/MAX15025, and to the source of the
MOSFET. When the gate of the MOSFET is being
pulled high, the active current loop is from the VDD
terminal of the VDRV terminal of decoupling capacitor, to the VDRV of the MAX15024/MAX15025, to the
OUT_ of the MAX15024/MAX15025, to the MOSFET
gate, to the MOSFET source, and to the negative terminal of the decoupling capacitor. Both charging
current loop and discharging current loop are important. It is important to minimize the physical distance
and the impedance in these AC current paths.
• Keep the device as close as possible to the MOSFET.
• In the multilayer PCB, the inner layers should consist
of a GND plane containing the discharging and
charging current loops.
IN+
VIH
VIL
P_OUT AND
N_OUT CONNECTED
TOGETHER
OR OUT1/OUT2
90%
10%
tD-OFF
tF
tD-ON
tR
Figure 1. Timing Diagram
______________________________________________________________________________________
11
MAX15024/MAX15025
Power Dissipation
Power dissipation of the MAX15024/MAX15025 consists of three components: the quiescent current,
capacitive charge and discharge of internal nodes, and
the output current (either capacitive or resistive load).
The sum of these components must be kept below the
maximum power-dissipation limit. The quiescent current is 700µA typ. The current required to charge and
discharge the internal nodes is frequency dependent
(see the Typical Operating Characteristics ). The
MAX15024/MAX15025 power dissipation when driving
a ground-referenced resistive load is:
P = D x RON(MAX) x ILOAD2
where D is the fraction of the period the MAX15024/
MAX15025s’ output pulls high, RON(MAX) is the maximum on-resistance of the device with the output high
(p-channel), and ILOAD is the output load current of the
MAX15024/MAX15025. For capacitive loads, the power
dissipation for each driver is:
P = CLOAD x VDRV2 x FREQ
where CLOAD is the capacitive load, VDRV is the driver
supply voltage, and FREQ is the switching frequency.
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Typical Operating Circuits
VCC
(UP TO 18V)
REG
DRV
VDRV < 18V
DRV
VCC
R2
C1
MAX15024
REG
FB/SET
P_OUT
MAX15024
R1
FB/SET
P_OUT
GND
N_OUT
IN-
PGND
N_OUT
VCC
(UP TO 28V)
VCC
PGND
GND
IN-
IN+
IN+
Figure 2. Connect FB/SET to GND for VREG = 10V (Connect EP
to GND)
Figure 3. Operation Using a Different Supply Rail for DRV
(Connect EP to GND)
REG
VCC
(UP TO 28V)
DRV
DRV
VCC
R2
MAX15025
OUT1
REG
FB/SET
MAX15024C/D
R1
FB/SET
P_OUT
OUT2
VCC
(UP TO 28V)
GND
N_OUT
VCC
GND
INPGND
PGND
IN1
IN+
IN2
Figure 4. Operation Using a VCC = DRV = REG (Connect EP
to GND)
12
Figure 5. Connect FB/SET to GND for VREG = 10V (Connect EP
to GND)
______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
VR
VCC
LDO
UVLO
FB/SET
VDRV
IN_ LOGIC
LEVEL SHIFT-UP
PREDRIVER
P
IN+
P_OUT
IN-
N_OUT
IN_ LOGIC
LEVEL SHIFT-UP
GND
PREDRIVER
N
PGND
MAX15024A
MAX15024B
VCC
REG
LDO
UVLO
FB/SET
DRV
IN_ LOGIC
LEVEL SHIFT-UP
P
PREDRIVER
IN1
OUT1
IN_ LOGIC
LEVEL SHIFT-UP
IN_ LOGIC
LEVEL SHIFT-UP
PREDRIVER
PREDRIVER
N
P
IN2
GND
OUT2
IN_ LOGIC
LEVEL SHIFT-UP
PREDRIVER
N
PGND
MAX15025
______________________________________________________________________________________
13
MAX15024/MAX15025
Block Diagrams
Selector Guide
LOGIC
LEVELS
TOP
MARK
VCCPOWERED
ONLY
VCC = VREG =
VDRV
Complementary
TTL
ATX
✔
—
Complementary
CMOS
ATY
✔
—
Complementary
TTL
—
✔
✔
Complementary
CMOS
—
✔
✔
4A/2A
Noninverting
TTL
ATZ
✔
—
2
4A/2A
Noninverting
CMOS
AUA
✔
—
MAX15025CATB+
2
4A/2A
Noninverting (1)/
Inverting (2)
TTL
AUB
✔
—
MAX15025DATB+
2
4A/2A
Noninverting (1)/
Inverting (2)
CMOS
AUC
✔
—
PART
NO. OF
CHANNELS
PEAK
CURRENTS
(SINK/SOURCE)
INPUTS
MAX15024AATB+
1
8A/4A
MAX15024BATB+
1
8A/4A
MAX15024CATB+
1
8A/4A
MAX15024DATB+
1
8A/4A
MAX15025AATB+
2
MAX15025BATB+
MAX15025EATB+
2
4A/2A
Noninverting
TTL
—
✔
✔
MAX15025FATB+
2
4A/2A
Noninverting
CMOS
—
✔
✔
MAX15025GATB+
2
4A/2A
Noninverting (1)/
Inverting (2)
TTL
—
✔
✔
MAX15025HATB+
2
4A/2A
Noninverting (1)/
Inverting (2)
CMOS
—
✔
✔
Note: All devices operate in a -40°C to +125°C temperature range and come in a 10-pin TDFN package.
Pin Configurations (continued)
REG
DRV
OUT1
OUT2
PGND
REG
DRV
OUT1
OUT2
PGND
TOP VIEW
10
9
8
7
6
10
9
8
7
6
MAX15025C/G
MAX15025D/H
MAX15025A/E
MAX15025B/F
1
2
FB/SET
VCC
3
4
5
IN2
5
IN1
4
IN2
VCC
3
IN1
2
GND
1
GND
EP
EP
FB/SET
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
TDFN
TDFN
Chip Information
PROCESS: BiCMOS
14
______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
6, 8, &10L, DFN THIN.EPS
______________________________________________________________________________________
15
MAX15024/MAX15025
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX15024/MAX15025
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
PACKAGE VARIATIONS
SYMBOL
MIN.
MAX.
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
A
0.70
0.80
T633-2
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
D
2.90
3.10
T833-2
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
E
2.90
3.10
T833-3
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
A1
0.00
0.05
T1033-1
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
L
0.20
0.40
T1033-2
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
k
0.25 MIN.
T1433-1
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
A2
0.20 REF.
T1433-2
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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is a registered trademark of Maxim Integrated Products, Inc.