NTD4808N Power MOSFET 30 V, 63 A, Single N--Channel, DPAK/IPAK Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb--Free Devices http://onsemi.com V(BR)DSS Applications • CPU Power Delivery • DC--DC Converters • Low Side Switching RDS(ON) MAX ID MAX 8.0 mΩ @ 10 V 30 V 63 A 12.4 mΩ @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Unit 30 V VGS ±20 V ID 12 A Continuous Drain Current RθJA (Note 1) TA = 25°C Power Dissipation RθJA (Note 1) TA = 25°C PD 2.0 W Continuous Drain Current RθJA (Note 2) TA = 25°C ID 9.8 A Power Dissipation RθJA (Note 2) TA = 85°C Steady State TA = 85°C 7.5 1.3 W Continuous Drain Current RθJC (Note 1) TC = 25°C ID 63 A Power Dissipation RθJC (Note 1) TC = 25°C PD 54.6 W TA = 25°C IDM 126 A TA = 25°C IDmaxPkg 45 A TJ, TSTG --55 to +175 °C TC = 85°C Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) 49 IS 45 A Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain--to--Source Avalanche Energy (VDD = 24 V, VGS = 10 V, IL = 17 Apk, L = 1.0 mH, RG = 25 Ω) EAS 144.5 mJ Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4 4 4 1 2 PD tp=10ms S N--CHANNEL MOSFET 9.5 TA = 25°C Pulsed Drain Current G 1 3 2 3 1 2 3 DPAK 3 IPAK IPAK CASE 369AA (STRAIGHT LEAD) CASE 369D STYLE 2 CASE 369AC STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 48 08NG Value VDSS YWW 48 08NG Gate--to--Source Voltage Symbol YWW 48 08NG Parameter Drain--to--Source Voltage 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4808N G = Year = Work Week = Device Code = Pb--Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2010 June, 2010 -- Rev. 5 1 Publication Order Number: NTD4808N/D NTD4808N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Junction--to--Case (Drain) Parameter RθJC 2.75 Junction--to--TAB (Drain) RθJC--TAB 3.5 Junction--to--Ambient – Steady State (Note 1) RθJA 73.5 Junction--to--Ambient – Steady State (Note 2) RθJA 116 Unit °C/W 1. Surface--mounted on FR4 board using 1 sq--in pad, 1 oz Cu. 2. Surface--mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Symbol Test Condition Min Drain--to--Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain--to--Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate--to--Source Leakage Current IDSS V 27 VGS = 0 V, VDS = 24 V mV/°C TJ = 25 °C 1 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain--to--Source On Resistance RDS(on) 5.6 VGS = 10 to 11.5 V VGS = 4.5 V Forward Transconductance 1.5 gFS ID = 30 A 6.7 ID = 15 A 6.6 ID = 30 A 10.3 ID = 15 A 9.8 VDS = 15 V, ID = 15 A mV/°C 8.0 mΩ 12.4 11.4 S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 180 Total Gate Charge QG(TOT) 11.3 Threshold Gate Charge QG(TH) Gate--to--Source Charge QGS Gate--to--Drain Charge QGD Total Gate Charge QG(TOT) 1538 VGS = 0 V, f = 1 MHz, VDS = 12 V VGS = 4.5 V, VDS = 15 V; ID = 30 A 334 1.6 4.9 pF 13 nC 4.9 VGS = 11.5 V, VDS = 15 V; ID = 30 A 26 nC SWITCHING CHARACTERISTICS (Note 4) Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time td(ON) tr td(OFF) 12.3 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 Ω tf 21.3 14.6 6.0 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4808N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 4) Turn--On Delay Time Rise Time Turn--Off Delay Time Fall Time td(ON) tr td(OFF) 7.7 VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 Ω tf 19.5 ns 23 3.5 DRAIN--SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.93 TJ = 125°C 0.83 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 30 A 1.2 V 20 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 10.4 ns 9.6 QRR 9.7 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 1.1 PACKAGE PARASITIC VALUES TA = 25°C 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 1.88 Ω NTD4808N TYPICAL PERFORMANCE CURVES ID, DRAIN CURRENT (AMPS) 4.5 V 80 TJ = 25°C 80 70 60 4V 50 3.8 V 40 3.6 V 30 3.4 V 20 3.2 V 3V 10 0 1 4 3 2 5 60 50 40 30 TJ = 125°C 20 TJ = 25°C 10 TJ = --55°C 1 2 Figure 1. On--Region Characteristics Figure 2. Transfer Characteristics 9.6 9.2 8.8 8.4 8.0 7.6 7.2 6.8 6.4 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 0.020 TJ = 25°C 0.018 0.016 0.014 VGS = 4.5 V 0.012 0.010 0.008 0.006 VGS = 11.5 V 0.004 0.002 0 10 15 20 VGS, GATE--TO--SOURCE VOLTAGE (VOLTS) IDSS, LEAKAGE (nA) RDS(on), DRAIN--TO--SOURCE RESISTANCE (NORMALIZED) 10000 1.2 1.1 1.0 0.9 0.8 0 25 50 75 100 125 150 35 40 45 50 55 60 VGS = 0 V 1000 TJ = 150°C 100 TJ = 125°C 10 1 0.7 0.6 --50 --25 30 Figure 4. On--Resistance vs. Drain Current and Gate Voltage ID = 30 A VGS = 10 V 1.3 25 ID, DRAIN CURRENT (AMPS) Figure 3. On--Resistance vs. Gate--to--Source Voltage 1.6 1.5 1.4 5 VGS, GATE--TO--SOURCE VOLTAGE (VOLTS) ID = 30 A TJ = 25°C 1.8 1.7 4 3 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) 10 6.0 VDS ≥ 10 V 70 0 RDS(on), DRAIN--TO--SOURCE RESISTANCE (Ω) 0 RDS(on), DRAIN--TO--SOURCE RESISTANCE (mΩ) 5.5 V to 10 V 90 ID, DRAIN CURRENT (AMPS) 100 175 0.1 TJ = 25°C 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) Figure 5. On--Resistance Variation with Temperature Figure 6. Drain--to--Source Leakage Current vs. Drain Voltage http://onsemi.com 4 30 NTD4808N C, CAPACITANCE (pF) 2000 VGS , GATE--TO--SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES TJ = 25°C Ciss 1500 1000 500 0 Coss Crss 5 0 10 15 20 25 5 2 0 0 IS, SOURCE CURRENT (AMPS) 10 td(on) tf 2 3 4 5 6 7 8 9 10 QG, TOTAL GATE CHARGE (nC) 11 12 1 VDD = 15 V ID = 30 A VGS = 11.5 V 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 25 15 10 5 0 0.5 100 1 ms 0.1 10 ms dc 10 1 VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN--TO--SOURCE AVALANCHE ENERGY (mJ) 100 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.7 0.8 1.0 0.9 Figure 10. Diode Forward Voltage vs. Current 10 ms 10 0.6 VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS) VGS = 20 V SINGLE PULSE TC = 25°C 100 TJ = 25°C 20 Figure 9. Resistive Switching Time Variation vs. Gate Resistance I D, DRAIN CURRENT (AMPS) 1 30 tr td(off) 1 VDD = 15 V VGS = 4.5 V ID = 30 A TJ = 25°C 1 Figure 8. Gate--To--Source and Drain--To--Source Voltage vs. Total Charge 100 1000 Q2 3 Figure 7. Capacitance Variation t, TIME (ns) Q1 4 GATE--TO--SOURCE OR DRAIN--TO--SOURCE VOLTAGE (VOLTS) 1 QT 100 90 ID = 17 A 80 70 60 50 40 30 20 10 0 50 Figure 11. Maximum Rated Forward Biased Safe Operating Area 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4808N TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 25°C 100°C 125°C 10 1 1 100 10 PULSE WIDTH (ms) 1000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 13. Avalanche Characteristics 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 1.0E--05 1.0E--04 t1 t2 DUTY CYCLE, D = t1/t2 1.0E--03 1.0E--02 t, TIME (ms) RθJC(t) = r(t) RθJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) -- TC = P(pk) RθJC(t) 1.0E--01 1.0E+00 1.0E+01 Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4808NT4G DPAK (Pb--Free) 2500 / Tape & Reel NTD4808N--1G IPAK (Pb--Free) 75 Units / Rail NTD4808N--35G IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb--Free) 75 Units / Rail Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4808N PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA--01 ISSUE B A E b3 c2 B Z D 1 L4 A 4 L3 b2 e 2 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C H DETAIL A 3 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z c b 0.005 (0.13) M C H L2 GAUGE PLANE C L SEATING PLANE A1 L1 DETAIL A ROTATED 90° CW STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 ------ 0.040 0.155 ------ 6.17 0.243 SCALE 3:1 mm inches *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 -----1.01 3.93 ------ NTD4808N PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC--01 ISSUE O B V NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. C E R DIM A B C D E F G H J K R V W A SEATING PLANE K W F J G D H 3 PL 0.13 (0.005) W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 IPAK (STRAIGHT LEAD DPAK) CASE 369D--01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 --T-SEATING PLANE K J F D G H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 ------ MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 ------ STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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