TI1 MSP430FR5722IPWR Mixed signal microcontroller Datasheet

MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D – JULY 2011 – REVISED AUGUST 2012
MIXED SIGNAL MICROCONTROLLER
FEATURES
1
•
23
•
Embedded Microcontroller
– 16-Bit RISC Architecture up to 24-MHz
Clock
– Wide Supply Voltage Range (2 V to 3.6 V)
– -40°C to 85°C Operation
Optimized Ultra-Low Power Modes
Mode
Active Mode
Consumption
(Typical)
81.4 µA/MHz
Standby (LPM3 With VLO)
6.3 µA
Real-Time Clock (LPM3.5 With Crystal)
1.5 µA
Shutdown (LPM4.5)
0.32 µA
•
•
•
•
Ultra-Low Power Ferroelectric RAM
– Up to 16KB Nonvolatile Memory
– Ultra-Low Power Writes
– Fast Write at 125 ns per Word (16KB in 1
ms)
– Built in Error Coding and Correction (ECC)
and Memory Protection Unit (MPU)
– Universal Memory = Program + Data +
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
Intelligent Digital Peripherals
– 32-Bit Hardware Multiplier (MPY)
– Three-Channel Internal DMA
– Real-Time Clock With Calendar and Alarm
Functions
– Five 16-Bit Timers With up to Three
Capture/Compare
– 16-Bit Cyclic Redundancy Checker (CRC)
High-Performance Analog
– 16-Channel Analog Comparator With
Voltage Reference and Programmable
Hysteresis
– 14-Channel 10-Bit Analog-to-Digital
Converter (ADC) With Internal Reference
and Sample-and-Hold
– 200 ksps at 100-µA Consumption
Enhanced Serial Communication
•
•
•
•
– eUSCI_A0 and eUSCI_A1 Support:
– UART With Automatic Baud-Rate
Detection
– IrDA Encode and Decode
– SPI at Rates up to 10 Mbps
– eUSCI_B0 Supports:
– I2C With Multi-Slave Addressing
– SPI at Rates up to 10 Mbps
– Hardware UART or I2C Bootstrap Loader
(BSL)
Power Management System
– Fully Integrated LDO
– Supply Voltage Supervisor for Core and
Supply Voltages With Reset Capability
– Always-On Zero-Power Brownout Detection
– Serial On-Board Programming With No
External Voltage Needed
Flexible Clock System
– Fixed-Frequency DCO With Six Selectable
Factory-Trimmed Frequencies (Device
Dependent)
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– 32-kHz Crystals (LFXT)
– High-Frequency Crystals (HFXT)
Development Tools and Software
– Free Professional Development
Environments (IAR, CCS, GCC)
– Low-Cost Full-Featured Kit (MSPEXP430FR5739)
– Full Development Kit (MSP-FET430U40A)
– Target Board (MSP-TS430RHA40A)
Family Members
– 20 Different Variants and 5 Available
Packages Summarized in Table 1 and
Table 2
– For Complete Module Descriptions, See the
MSP430FR57xx Family User's Guide
(SLAU272)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
www.ti.com
CAUTION
These products use FRAM nonvolatile memory technology. FRAM retention is sensitive to extreme temperatures, such
as those experienced during reflow or hand soldering. See Absolute Maximum Ratings for more information.
CAUTION
System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical
overstress or disturb of data or code memory. See the application report MSP430™ System-Level ESD Considerations
(SLAA530) for more information.
DESCRIPTION
The Texas Instruments MSP430FR57xx family of ultralow-power microcontrollers consists of multiple devices
featuring embedded FRAM nonvolatile memory, ultralow power 16-bit MSP430 CPU, and different peripherals
targeted for various applications. The architecture, FRAM, and peripherals, combined with seven low-power
modes, are optimized to achieve extended battery life in portable and wireless sensing applications. FRAM is a
new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the stability and
reliability of flash, all at lower total power consumption. Peripherals include 10-bit A/D converter, 16-channel
comparator with voltage reference generation and hysteresis capabilities, three enhanced serial channels
capable of I2C, SPI, or UART protocols, internal DMA, hardware multiplier, real-time clock, five 16-bit timers, and
more. The family members that are available are summarized in Table 1.
Table 1. Family Members
eUSCI
Device
FRAM
(KB)
SRAM
(KB)
System
Clock
(MHz)
ADC10_B
Comp_D
MSP430FR5739
16
1
24
12 ext,
2 int ch.
16 ch.
6 ext, 2 int
ch.
10 ch.
8 ext, 2 int
ch.
12 ch.
5 ext, 2 int
ch.
9 ch.
MSP430FR5738
MSP430FR5737
16
16
1
1
24
24
16 ch.
Timer_A
3, 3
3, 3
3, 3
(1)
Timer_B
3, 3, 3
3
3, 3, 3
(2)
Channel
A:
UART,
IrDA, SPI
Channel
B:
SPI, I2C
2
1
1
2
1
1
10 ch.
MSP430FR5736
16
1
24
12 ch.
3, 3
3
1
1
9 ch.
MSP430FR5735
MSP430FR5734
MSP430FR5733
MSP430FR5732
MSP430FR5731
(1)
(2)
(3)
2
8
8
8
8
4
1
1
1
1
1
24
24
12 ext,
2 int ch.
16 ch.
6 ext, 2 int
ch.
10 ch.
8 ext, 2 int
ch.
12 ch.
24
16 ch.
10 ch.
24
24
12 ch.
12 ext,
2 int ch.
16 ch.
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3
3, 3
3, 3, 3
3
3, 3, 3
2
1
2
1
1
1
I/O
Package
32
RHA
30
DA
17
RGE
21
PW
16
YFF (3)
32
RHA
30
DA
17
RGE
21
PW
16
YFF (3)
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
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MSP430FR572x
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SLAS639D – JULY 2011 – REVISED AUGUST 2012
Table 1. Family Members (continued)
eUSCI
Device
MSP430FR5730
MSP430FR5729
MSP430FR5728
MSP430FR5727
MSP430FR5726
MSP430FR5725
MSP430FR5724
MSP430FR5723
MSP430FR5722
MSP430FR5721
MSP430FR5720
FRAM
(KB)
4
16
16
16
16
8
8
8
8
4
4
SRAM
(KB)
1
1
1
1
1
1
1
1
1
1
1
System
Clock
(MHz)
24
8
8
ADC10_B
Comp_D
6 ext, 2 int
ch.
10 ch.
8 ext, 2 int
ch.
12 ch.
5 ext, 2 int
ch.
9 ch.
12 ext,
2 int ch.
16 ch.
6 ext, 2 int
ch.
10 ch.
8 ext, 2 int
ch.
12 ch.
8
16 ch.
10 ch.
8
8
8
12 ch.
12 ext,
2 int ch.
16 ch.
6 ext, 2 int
ch.
10 ch.
8 ext, 2 int
ch.
12 ch.
8
16 ch.
10 ch.
8
8
8
Copyright © 2011–2012, Texas Instruments Incorporated
12 ch.
12 ext,
2 int ch.
16 ch.
6 ext, 2 int
ch.
10 ch.
8 ext, 2 int
ch.
12 ch.
Timer_A (1) Timer_B (2)
3, 3
3
Channel
A:
UART,
IrDA, SPI
1
Channel
B:
SPI, I2C
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3
3, 3, 3
3
2
1
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
3, 3
3, 3
3, 3, 3
3
2
1
1
1
3, 3
3, 3, 3
2
1
3, 3
3
1
1
I/O
Package
17
RGE
21
PW
16
YFF (3)
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
32
RHA
30
DA
17
RGE
21
PW
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Table 2. Ordering Information (1)
PACKAGED DEVICES (2)
TA
–40°C to
85°C
(1)
(2)
(3)
4
PLASTIC 40-PIN
VQFN
(RHA)
PLASTIC 24-PIN
VQFN
(RGE)
PLASTIC 38-PIN
TSSOP
(DA)
PLASTIC 28-PIN
TSSOP
(PW)
PLASTIC 25-BALL
DSBGA
(YFF) (3)
MSP430FR5721IRHA
MSP430FR5720IRGE
MSP430FR5721IDA
MSP430FR5720IPW
MSP430FR5730IYFF (3)
MSP430FR5723IRHA
MSP430FR5722IRGE
MSP430FR5723IDA
MSP430FR5722IPW
MSP430FR5736IYFF (3)
MSP430FR5725IRHA
MSP430FR5724IRGE
MSP430FR5725IDA
MSP430FR5724IPW
MSP430FR5738IYFF (3)
MSP430FR5727IRHA
MSP430FR5726IRGE
MSP430FR5727IDA
MSP430FR5726IPW
MSP430FR5729IRHA
MSP430FR5728IRGE
MSP430FR5729IDA
MSP430FR5728IPW
MSP430FR5731IRHA
MSP430FR5730IRGE
MSP430FR5731IDA
MSP430FR5730IPW
MSP430FR5733IRHA
MSP430FR5732IRGE
MSP430FR5733IDA
MSP430FR5732IPW
MSP430FR5735IRHA
MSP430FR5734IRGE
MSP430FR5735IDA
MSP430FR5734IPW
MSP430FR5737IRHA
MSP430FR5736IRGE
MSP430FR5737IDA
MSP430FR5736IPW
MSP430FR5739IRHA
MSP430FR5738IRGE
MSP430FR5739IDA
MSP430FR5738IPW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
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Functional Block Diagram –
MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5735IRHA, MSP430FR5739IRHA
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
8 KB
SMCLK
4 KB
(’5731, ‘5721)
FRAM
MCLK
CPUXV2
and
Working
Registers
1 KB
Power
Management
Boot
ROM
SYS
Watchdog
P3.x
I/O Ports
P1/P2
2×8 I/Os
(’5739, ’5729)
(’5735, ‘5725)
PA
P2.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
REF
Interrupt
& Wakeup
PA
1×16 I/Os
SVS
RAM
Memory
Protection
Unit
PB
P4.x
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
eUSCI_A1:
UART,
IrDA, SPI
CRC
eUSCI_B0:
SPI, I2C
ADC10_B
10 Bit
200KSPS
Comp_D
16 channels
16 channels
(12 ext/2 int)
Functional Block Diagram –
MSP430FR5723IRHA, MSP430FR5727IRHA,
MSP430FR5733IRHA, MSP430FR5737IRHA
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
8 KB
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
1 KB
Boot
ROM
Power
Management
P3.x
I/O Ports
P1/P2
2×8 I/Os
(’5737, ’5727)
(’5733, ‘5723)
PA
P2.x
SYS
Watchdog
Interrupt
& Wakeup
PA
1×16 I/Os
SVS
RAM
Memory
Protection
Unit
PB
P4.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
Copyright © 2011–2012, Texas Instruments Incorporated
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
REF
16 channels
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Pin Designation –
MSP430FR5721IRHA, MSP430FR5723IRHA, MSP430FR5725IRHA, MSP430FR5727IRHA,
MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5733IRHA, MSP430FR5735IRHA, MSP430FR5737IRHA,
MSP430FR5739IRHA
RHA PACKAGE
(TOP VIEW)
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
31
32
33
35
34
36
37
39
30
1
2
29
MSP430FR5721
MSP430FR5723
MSP430FR5725
MSP430FR5727
MSP430FR5729
MSP430FR5731
MSP430FR5733
MSP430FR5735
MSP430FR5737
MSP430FR5739
3
4
5
6
7
8
9
28
27
26
25
24
23
22
10
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P4.0/TB2.0
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB2.2
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
20
19
18
17
16
15
14
13
11
21
12
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P3.0/A12*/CD12
P3.1/A13*/CD13
P3.2/A14*/CD14
P3.3/A15*/CD15
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
38
40
AVSS
PJ.4/XIN
PJ.5/XOUT
AVSS
AVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P4.1
* Not available on MSP430FR5737, MSP430FR5733, MSP430FR5727, MSP430FR5723
Note: Power Pad connection to VSS recommended.
6
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Functional Block Diagram –
MSP430FR5721IDA, MSP430FR5725IDA, MSP430FR5729IDA,
MSP430FR5731IDA, MSP430FR5735IDA, MSP430FR5739IDA
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
(’5739, ’5729)
8 KB
(’5735, ‘5725)
SMCLK
4 KB
CPUXV2
and
Working
Registers
Power
Management
Boot
ROM
(’5731, ‘5721)
FRAM
MCLK
1 KB
SYS
Watchdog
PA
P2.x
PB
P3.x
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3
1×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
Interrupt
& Wakeup
PB
1×8 I/Os
REF
SVS
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
eUSCI_A1:
UART,
IrDA, SPI
CRC
eUSCI_B0:
SPI, I2C
ADC10_B
10 Bit
200KSPS
Comp_D
16 channels
16 channels
(12 ext/2 int)
Functional Block Diagram –
MSP430FR5723IDA, MSP430FR5727IDA,
MSP430FR5733IDA, MSP430FR5737IDA
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
(’5737, ’5727)
8 KB
(’5733, ‘5723)
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
1 KB
Boot
ROM
Power
Management
SYS
PA
P2.x
PB
P3.x
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3
1×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
Interrupt
& Wakeup
PB
1×8 I/Os
Watchdog
SVS
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
TA0
TA1
TB0
TB1
TB2
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
RTC_B
MPY32
Copyright © 2011–2012, Texas Instruments Incorporated
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
REF
16 channels
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Pin Designation –
MSP430FR5721IDA, MSP430FR5723IDA, MSP430FR5725IDA, MSP430FR5727IDA,
MSP430FR5729IDA,
MSP430FR5731IDA, MSP430FR5733IDA, MSP430FR5735IDA, MSP430FR5737IDA,
MSP430FR5739IDA
DA PACKAGE
(TOP VIEW)
PJ.4/XIN
PJ.5/XOUT
AVSS
AVCC
1
38
2
37
3
36
4
35
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P3.0/A12*/CD12
P3.1/A13*/CD13
P3.2/A14*/CD14
P3.3/A15*/CD15
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
34
6 MSP430FR5721 33
7 MSP430FR5723 32
8
MSP430FR5725
31
MSP430FR5727
9 MSP430FR5729 30
10
29
11 MSP430FR5731 28
12 MSP430FR5733 27
MSP430FR5735
13
26
MSP430FR5737
14 MSP430FR5739 25
15
24
16
23
17
22
18
21
19
20
AVSS
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P3.7/TB2.2
P3.6/TB2.1/TB1CLK
P3.5/TB1.2/CDOUT
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6/TB1.0/UCA1RXD/UCA1SOMI
* Not available on MSP430FR5737, MSP430FR5733, MSP430FR5727, MSP430FR5723
8
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SLAS639D – JULY 2011 – REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5720IRGE, MSP430FR5724IRGE, MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5734IRGE, MSP430FR5738IRGE
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
(’5734, ‘5724)
SMCLK
4 KB
CPUXV2
and
Working
Registers
1 KB
(’5730, ‘5720)
FRAM
MCLK
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
(’5738, ’5728)
8 KB
Power
Management
Boot
ROM
SYS
Watchdog
PA
P2.x
REF
SVS
Interrupt
& Wakeup
PA
1×11 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
ADC10_B
10 Bit
200KSPS
CRC
eUSCI_B0:
SPI, I2C
Comp_D
10 channels
8 channels
(6 ext/2 int)
Functional Block Diagram –
MSP430FR5722IRGE, MSP430FR5726IRGE,
MSP430FR5732IRGE, MSP430FR5736IRGE
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
(’5732, ‘5722)
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
(’5736, ’5726)
8 KB
1 KB
Boot
ROM
Power
Management
PA
P2.x
SYS
Watchdog
SVS
Interrupt
& Wakeup
PA
1×11 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
Copyright © 2011–2012, Texas Instruments Incorporated
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Comp_D
REF
10 channels
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Pin Designation –
MSP430FR5720IRGE, MSP430FR5722IRGE, MSP430FR5724IRGE, MSP430FR5726IRGE,
MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5732IRGE, MSP430FR5734IRGE, MSP430FR5736IRGE,
MSP430FR5738IRGE
RGE PACKAGE
(TOP VIEW)
PJ.4/XIN
DVCC
DVSS
1
20
21
23
19
18
17
16
15
14
13
VCORE
P1.7/UCB0SOMI/UCB0SCL/TA1.0
P1.6/UCB0SIMO/UCB0SDA/TA0.0
P2.2/UCB0CLK
P2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
12
7
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
PJ.2/TMS/ACLK/CD8
11
5
6
10
3
4
9
MSP430FR5720
MSP430FR5722
MSP430FR5724
MSP430FR5726
MSP430FR5728
MSP430FR5730
MSP430FR5732
MSP430FR5734
MSP430FR5736
MSP430FR5738
2
8
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
22
24
PJ.5/XOUT
AVSS
AVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.3/TCK/CD9
* Not available on MSP430FR5736, MSP430FR5732, MSP430FR5726, MSP430FR5722
Note: Power Pad connection to VSS recommended.
10
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MSP430FR572x
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SLAS639D – JULY 2011 – REVISED AUGUST 2012
Pin Designation –
MSP430FR5730IYFF, MSP430FR5736IYFF, MSP430FR5738IYFF
YFF PACKAGE
(TOP VIEW)
1
1
P1.1
P1.2
P1.3
P1.5
A1
A2
A3
A4
A5
PJ.5
AVCC
AVSS
P1.4
PJ.1
B1
B2
B3
B4
B5
PJ.4
AVSS
PJ.0
PJ.2
PJ.3
C1
C2
C3
C4
C5
DVCC
DVSS
D1
D2
D3
D4
D5
VCORE
P1.6
P1.7
P2.2
P2.0
E1
E2
E3
E4
E5
NC
P2.1 RST/NMI TEST
NC (no connect). This ball must be attached but remain floating (no electrical connection).
P1.0 must be initialized properly to avoid the floating input of the device.
Package Dimensions: The package dimensions for the YFF package are shown in Table 3. See the package
drawing at the end of this data sheet for more details.
Table 3. YFF Package Dimensions
PACKAGED DEVICES
D
E
2.04 ± 0.03
2.24 ± 0.03
MSP430FR5738IYFF
MSP430FR5736IYFF
MSP430FR5730IYFF
Copyright © 2011–2012, Texas Instruments Incorporated
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Functional Block Diagram –
MSP430FR5720IPW, MSP430FR5724IPW, MSP430FR5728IPW,
MSP430FR5730IPW, MSP430FR5734IPW, MSP430FR5738IPW
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
(’5734, ‘5724)
SMCLK
4 KB
CPUXV2
and
Working
Registers
1 KB
(’5730, ‘5720)
FRAM
MCLK
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
(’5738, ’5728)
8 KB
Power
Management
Boot
ROM
SYS
Watchdog
PA
P2.x
REF
SVS
Interrupt
& Wakeup
PA
1×15 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
ADC10_B
10 Bit
200KSPS
CRC
eUSCI_B0:
SPI, I2C
Comp_D
12 channels
12 channels
(8 ext/2 int)
Functional Block Diagram –
MSP430FR5722IPW, MSP430FR5726IPW,
MSP430FR5732IPW, MSP430FR5736IPW
PJ.4/XIN
DVCC DVSS VCORE
PJ.5/XOUT
AVCC AVSS
P1.x
16 KB
Clock
System
ACLK
(’5732, ‘5722)
SMCLK
FRAM
MCLK
CPUXV2
and
Working
Registers
I/O Ports
P1/P2
1×8 I/Os
1×7 I/Os
(’5736, ’5726)
8 KB
1 KB
Boot
ROM
Power
Management
PA
P2.x
SYS
Watchdog
SVS
Interrupt
& Wakeup
PA
1×15 I/Os
RAM
Memory
Protection
Unit
MAB
DMA
MDB
3 Channel
EEM
(S: 3+1)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
12
JTAG/
SBW
Interface
TA0
TA1
TB0
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
RTC_B
MPY32
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CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Comp_D
REF
12 channels
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Pin Designation –
MSP430FR5720IPW, MSP430FR5722IPW, MSP430FR5724IPW, MSP430FR5726IPW,
MSP430FR5728IPW,
MSP430FR5730IPW, MSP430FR5732IPW, MSP430FR5734IPW, MSP430FR5736IPW,
MSP430FR5738IPW
PW PACKAGE
(TOP VIEW)
PJ.4/XIN
PJ.5/XOUT
AVSS
AVCC
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/MCLK/CD7
PJ.2/TMS/ACLK/CD8
PJ.3/TCK/CD9
1
28
2
27
3
26
4
25
MSP430FR5738
MSP430FR5736
5 MSP430FR5734
6 MSP430FR5732
7 MSP430FR5730
24
23
22
8
21
9
20
MSP430FR5728
MSP430FR5726
10 MSP430FR5724
11 MSP430FR5722
12 MSP430FR5720
19
18
17
13
16
14
15
P2.4/TA1.0/A7*/CD11
P2.3/TA0.0/A6*/CD10
DVCC
DVSS
VCORE
P1.7/UCB0SOMI/UCB0SCL/TA1.0
P1.6/UCB0SIMO/UCB0SDA/TA0.0
P2.2/UCB0CLK
P2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.6
P2.5/TB0.0
* Not available on MSP430FR5736, MSP430FR5732, MSP430FR5726, MSP430FR5722
Copyright © 2011–2012, Texas Instruments Incorporated
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Table 4. Terminal Functions
TERMINAL
NAME
P1.0/TA0.1/DMAE0/
RTCCLK/A0/CD0/VeREF-
P1.1/TA0.2/TA1CLK/
CDOUT/A1/CD1/VeREF+
P1.2/TA1.1/TA0CLK/
CDOUT/A2/CD2
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
(1)
(2)
14
NO.
RHA
1
2
3
4
5
6
7
RGE
1
2
3
N/A
N/A
N/A
N/A
DA
5
6
7
8
9
10
11
I/O
PW
5
6
7
N/A
N/A
N/A
N/A
(1)
DESCRIPTION
YFF
(2)
A2
A3
N/A
N/A
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
RTC clock calibration output
Analog input A0 – ADC (not available on devices without ADC)
Comparator_D input CD0
External applied reference voltage (not available on devices without
ADC)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
Comparator_D output
Analog input A1 – ADC (not available on devices without ADC)
Comparator_D input CD1
Input for an external reference voltage to the ADC (not available on
devices without ADC)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
TA0 input clock
Comparator_D output
Analog input A2 – ADC (not available on devices without ADC)
Comparator_D input CD2
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A12 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD12 (not available on package options PW,
RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A13 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD13 (not available on package options PW,
RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A14 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD14 (not available on package options PW,
RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
Analog input A15 – ADC (not available on devices without ADC or
package options PW, RGE)
Comparator_D input CD15 (not available on package options PW,
RGE)
I = input, O = output, N/A = not available
The functions associated with P1.0 are implemented but not available on the device pinout. To avoid floating inputs, this digital I/O
should be properly configured. The pullup/down resistors of P1.0 should be enabled.
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Table 4. Terminal Functions (continued)
TERMINAL
NAME
P1.3/TA1.2/UCB0STE/
A3/CD3
P1.4/TB0.1/UCA0STE/
A4/CD4
P1.5/TB0.2/UCA0CLK/
A5/CD5
PJ.0/TDO/TB0OUTH/
SMCLK/CD6 (3)
PJ.1/TDI/TCLK/TB1OUTH/
MCLK/CD7 (3)
NO.
RHA
8
9
10
11
12
RGE
4
5
6
7
8
DA
12
13
14
15
16
I/O
PW
8
9
10
11
12
(1)
DESCRIPTION
YFF
A4
B4
A5
C3
B5
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
Slave transmit enable – eUSCI_B0 SPI mode
Analog input A3 – ADC (not available on devices without ADC)
Comparator_D input CD3
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
Slave transmit enable – eUSCI_A0 SPI mode
Analog input A4 – ADC (not available on devices without ADC)
Comparator_D input CD4
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal
output – eUSCI_B0 SPI master mode
Analog input A5 – ADC (not available on devices without ADC)
Comparator_D input CD5
I/O
General-purpose digital I/O
Test data output port
Switch all PWM outputs high impedance input – TB0
SMCLK output
Comparator_D input CD6
I/O
General-purpose digital I/O
Test data input or test clock input
Switch all PWM outputs high impedance input – TB1 (not available
on devices without TB1)
MCLK output
Comparator_D input CD7
13
9
17
13
C4
I/O
General-purpose digital I/O
Test mode select
Switch all PWM outputs high impedance input – TB2 (not available
on devices without TB2)
ACLK output
Comparator_D input CD8
14
10
18
14
C5
I/O
General-purpose digital I/O
Test clock
Comparator_D input CD9
P4.0/TB2.0
15
N/A
N/A
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on
devices without TB2 or package options DA, PW, RGE)
P4.1
16
N/A
N/A
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options DA, PW, RGE)
PJ.2/TMS/TB2OUTH/
ACLK/CD8 (3)
PJ.3/TCK/CD9
(3)
(3)
See JTAG Operation for use with JTAG function.
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Table 4. Terminal Functions (continued)
TERMINAL
NO.
NAME
RHA
P2.5/TB0.0/UCA1TXD/
UCA1SIMO
17
P2.6/TB1.0/UCA1RXD/
UCA1SOMI
TEST/SBWTCK
(3) (4)
RST/NMI/SBWTDIO
(3) (4)
P2.0/TB2.0/UCA0TXD/
UCA0SIMO/TB0CLK/ACLK
(4)
P2.1/TB2.1/UCA0RXD/
UCA0SOMI/TB0.0 (5)
P2.2/TB2.2/UCB0CLK/ TB1.0
P3.4/TB1.1/TB2CLK/ SMCLK
(4)
(5)
16
RGE
N/A
DA
19
I/O
PW
15
(1)
DESCRIPTION
YFF
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
Transmit data – eUSCI_A1 UART mode, Slave in, master out –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
Receive data – eUSCI_A1 UART mode, Slave out, master in –
eUSCI_A1 SPI mode (not available on devices without UCSI_A1)
18
N/A
20
16
N/A
I/O
19
11
21
17
D5
I
20
12
22
18
D4
I/O
Reset input active low
Non-maskable interrupt input
Spy-Bi-Wire data input/output
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB2)
Transmit data – eUSCI_A0 UART mode, Slave in, master out –
eUSCI_A0 SPI mode
TB0 clock input
ACLK output
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB2)
Receive data – eUSCI_A0 UART mode, Slave out, master in –
eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB2)
Clock signal input – eUSCI_B0 SPI slave mode, Clock signal
output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on
devices without TB1)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB1)
TB2 clock input (not available on devices without TB2 or package
options PW, RGE)
SMCLK output (not available on package options PW, RGE)
21
22
23
24
13
14
15
N/A
23
24
25
26
19
20
21
N/A
E5
D3
E4
N/A
Test mode pin – enable JTAG pins
Spy-Bi-Wire input clock
See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
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MSP430FR572x
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SLAS639D – JULY 2011 – REVISED AUGUST 2012
Table 4. Terminal Functions (continued)
TERMINAL
NAME
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
P3.7/TB2.2
P1.6/TB1.1/UCB0SIMO/
UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/
UCB0SCL/TA1.0
VCORE
(6)
NO.
RHA
25
26
27
28
RGE
N/A
N/A
N/A
16
DA
27
28
29
30
I/O
PW
N/A
N/A
N/A
22
29
17
31
23
(1)
DESCRIPTION
YFF
N/A
N/A
N/A
E2
E3
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on
devices without TB1)
Comparator_D output (not available on package options PW, RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on
devices without TB2)
TB1 clock input (not available on devices without TB1 or package
options PW, RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options PW, RGE)
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on
devices without TB2 or package options PW, RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on
devices without TB1)
Slave in, master out – eUSCI_B0 SPI mode
I2C data – eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on
devices without TB1)
Slave out, master in – eUSCI_B0 SPI mode
I2C clock – eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
30
18
32
24
E1
Regulated core power supply (internal use only, no external current loading)
DVSS
31
19
33
25
D2
Digital ground supply
DVCC
32
20
34
26
D1
Digital power supply
P2.7
33
N/A
35
N/A
N/A
P2.3/TA0.0/UCA1STE/
A6/CD10
P2.4/TA1.0/UCA1CLK/
A7/CD11
(6)
34
35
N/A
N/A
36
37
27
28
N/A
N/A
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not
available on package options PW, RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options RGE)
TA0 CCR0 capture: CCI0B input, compare: Out0 (not available on
package options RGE)
Slave transmit enable – eUSCI_A1 SPI mode (not available on
devices without eUSCI_A1)
Analog input A6 – ADC (not available on devices without ADC)
Comparator_D input CD10 (not available on package options RGE)
I/O
General-purpose digital I/O with port interrupt and wake up from
LPMx.5 (not available on package options RGE)
TA1 CCR0 capture: CCI0B input, compare: Out0 (not available on
package options RGE)
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal
output – eUSCI_A1 SPI master mode (not available on devices
without eUSCI_A1)
Analog input A7 – ADC (not available on devices without ADC)
Comparator_D input CD11 (not available on package options RGE)
VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.
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Table 4. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
(1)
DESCRIPTION
RHA
RGE
DA
PW
YFF
AVSS
36
N/A
38
N/A
B3
PJ.4/XIN
37
21
1
1
C1
I/O
General-purpose digital I/O
Input terminal for crystal oscillator XT1
PJ.5/XOUT
38
22
2
2
B1
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS
39
23
3
3
C2
Analog ground supply
AVCC
40
24
4
4
B2
Analog power supply
Pad
Pad
N/A
N/A
N/A
QFN package pad. Connection to VSS recommended.
QFN Pad
18
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SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
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Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from low-power modes LPM0 through LPM4, service the request, and restore back
to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the
core supply to minimize power consumption.
The following eight operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK active, MCLK disabled, SMCLK optionally active
– Complete data retention
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK active, MCLK disabled, SMCLK optionally active
– DCO disabled
– Complete data retention
• Low-power mode 2 (LPM2)
– CPU is disabled
– ACLK active, MCLK disabled, SMCLK optionally active
– DCO disabled
– Complete data retention
• Low-power mode 3 (LPM3)
– CPU is disabled
– ACLK active, MCLK and SMCLK disabled
– DCO disabled
– Complete data retention
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK, MCLK, SMCLK disabled
– Complete data retention
• Low-power mode 3.5 (LPM3.5)
– RTC operation
– Internal regulator disabled
– No data retention
– I/O pad state retention
– Wake up from RST, general-purpose I/O, RTC events
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– I/O pad state retention
– Wake up from RST and general-purpose I/O
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Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
System Reset
Power-Up, Brownout, Supply
Supervisors
External Reset RST
Watchdog Timeout (Watchdog
mode)
WDT, FRCTL MPU, CS, PMM
Password Violation
FRAM double bit error detection
MPU segment violation
Software POR, BOR
SVSLIFG, SVSHIFG
PMMRSTIFG
WDTIFG
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
DBDIFG
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
PMMPORIFG, PMMBORIFG
(SYSRSTIV) (1) (2)
Reset
0FFFEh
63, highest
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
Access violation
FRAM single, double bit error
detection
VMAIFG
JMBNIFG, JMBOUTIFG
ACCTIMIFG
ACCVIFG
SBDIFG, DBDIFG
(SYSSNIV) (1)
(Non)maskable
0FFFCh
62
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(SYSUNIV) (1) (2)
(Non)maskable
0FFFAh
61
Comparator_D
Comparator_D interrupt flags
(CBIV) (1) (3)
Maskable
0FFF8h
60
TB0
TB0CCR0 CCIFG0
(3)
Maskable
0FFF6h
59
TB0
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0IFG
(TB0IV) (1) (3)
Maskable
0FFF4h
58
Watchdog Timer
(Interval Timer Mode)
WDTIFG
Maskable
0FFF2h
57
eUSCI_A0 Receive and Transmit
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
UXA0TXIFG (UART mode)
(UCA0IV) (1) (3)
Maskable
0FFF0h
56
eUSCI_B0 Receive and Transmit
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(UCB0IV) (1) (3)
Maskable
0FFEEh
55
ADC10_B
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10INIFG, ADC10IFG0
(ADC10IV) (1) (3) (4)
Maskable
0FFECh
54
Maskable
0FFEAh
53
Maskable
0FFE8h
52
TA0
TA0
(1)
(2)
(3)
(4)
TA0CCR0 CCIFG0
(3)
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0IFG
(TA0IV) (1) (3)
Multiple source flags
A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
Only on devices with ADC, otherwise reserved.
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Table 5. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
eUSCI_A1 Receive and Transmit
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
UXA1TXIFG (UART mode)
(UCA1IV) (1) (3)
Maskable
0FFE6h
51
DMA
DMA0IFG, DMA1IFG, DMA2IFG
(DMAIV) (1) (3)
Maskable
0FFE4h
50
Maskable
0FFE2h
49
TA1
TA1CCR0 CCIFG0
TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG
(TA1IV) (1) (3)
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7
(P1IV) (1) (3)
Maskable
0FFDEh
47
TB1
TB1CCR0 CCIFG0
Maskable
0FFDCh
46
TB1
Maskable
0FFDAh
45
I/O Port P2
P2IFG.0 to P2IFG.7
(P2IV) (1) (3)
Maskable
0FFD8h
44
TB2CCR0 CCIFG0
(3)
Maskable
0FFD6h
43
TB2
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2IFG
(TB2IV) (1) (3)
Maskable
0FFD4h
42
I/O Port P3
P3IFG.0 to P3IFG.7
(P3IV) (5) (6)
Maskable
0FFD2h
41
I/O Port P4
P4IFG.0 to P4IFG.2
(P4IV) (5) (6)
Maskable
0FFD0h
40
RTC_B
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
(RTCIV) (5) (6)
Maskable
0FFCEh
39
0FFCCh
38
Reserved
22
(3)
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1IFG
(TB1IV) (1) (3)
TB2
(5)
(6)
(7)
(3)
Reserved
(7)
⋮
⋮
0FF80h
0, lowest
Multiple source flags
Interrupt flags are located in the module.
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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Memory Organization
Table 6. Memory Organization
(1) (2)
MSP430FR5726
MSP430FR5727
MSP430FR5728
MSP430FR5729
MSP430FR5736
MSP430FR5737
MSP430FR5738
MSP430FR5739
MSP430FR5722
MSP430FR5723
MSP430FR5724
MSP430FR5725
MSP430FR5732
MSP430FR5733
MSP430FR5734
MSP430FR5735
MSP430FR5720
MSP430FR5721
MSP430FR5730
MSP430FR5731
15.5 KB
00FFFFh–00FF80h
00FF7Fh–00C200h
8.0 KB
00FFFFh–00FF80h
00FF7Fh–00E000h
4 KB
00FFFFh–00FF80h
00FF7Fh–00F000h
RAM
1 KB
001FFFh–001C00h
1 KB
001FFFh–001C00h
1 KB
001FFFh–001C00h
Device Descriptor Info
(TLV) (FRAM)
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
128 B
001A7Fh–001A00h
N/A
0019FFh–001980h
Address space mirrored to
Info A
0019FFh–001980h
Address space mirrored to
Info A
0019FFh–001980h
Address space mirrored to
Info A
N/A
00197Fh–001900h
Address space mirrored to
Info B
00197Fh–001900h
Address space mirrored to
Info B
00197Fh–001900h
Address space mirrored to
Info B
Info A
128 B
0018FFh–001880h
128 B
0018FFh–001880h
128 B
0018FFh–001880h
Info B
128 B
00187Fh–001800h
128 B
00187Fh–001800h
128 B
00187Fh–001800h
BSL 3
512 B
0017FFh–001600h
512 B
0017FFh–001600h
512 B
0017FFh–001600h
BSL 2
512 B
0015FFh–001400h
512 B
0015FFh–001400h
512 B
0015FFh–001400h
BSL 1
512 B
0013FFh–001200h
512 B
0013FFh–001200h
512 B
0013FFh–001200h
BSL 0
512 B
0011FFh–001000h
512 B
0011FFh–001000h
512 B
0011FFh–001000h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
4 KB
000FFFh–0h
Memory (FRAM)
Main: interrupt vectors
Main: code memory
Total Size
Information memory
(FRAM)
Bootstrap loader (BSL)
memory (ROM)
Peripherals
(1)
(2)
Size
N/A = Not available
All address space not listed in this table is considered vacant memory.
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Bootstrap Loader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device
memory by the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in
Table 7. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For
complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the
Bootstrap Loader User's Guide (SLAU319).
Table 7. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P2.0
Data transmit
P2.1
Data receive
VCC
Power supply
VSS
Ground supply
JTAG Operation
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 8. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 8. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
JTAG clock input
PJ.2/TMS
IN
JTAG state control
PJ.1/TDI/TCLK
IN
JTAG data input, TCLK input
PJ.0/TDO
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 9. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 9. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
24
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
Power supply
VSS
Ground supply
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FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
• Low-power ultrafast write nonvolatile memory
• Byte and word access capability
• Programmable and automated wait state generation
• Error Correction Coding (ECC) with single bit detection and correction, double bit detection
Memory Protection Unit (MPU)
The FRAM can be protected from inadvertent CPU execution or write access by the MPU. Features of the MPU
include:
• Main memory partitioning programmable up to three segments
• Each segment's (main and information memory) access rights can be individually selected
• Access violation flags with interrupt capability for easy servicing of access violations
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430FR57xx Family User's Guide (SLAU272).
Digital I/O
There are up to four 8-bit I/O ports implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF mode), an internal very-lowpower low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a highfrequency crystal oscillator XT1 (HF mode). The clock system module is designed to meet the requirements of
both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources. The clock
system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1 LF mode), a high-frequency crystal (XT1
HF mode), the internal VLO, or the internal DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by the same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
the same sources made available to ACLK.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also
includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit is implemented to
provide the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if
the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the primary and core
supplies.
Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations.
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Real-Time Clock (RTC_B)
The RTC_B module contains an integrated real-time clock (RTC) (calendar mode). Calendar mode integrates an
internal calendar which compensates for months with fewer than 31 days and includes leap year correction. The
RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC operation is available in
LPM3.5 mode to minimize power consumption.
Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset (POR)
and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector generators,
bootstrap loader entry mechanisms, and configuration management (device descriptors). It also includes a data
exchange mechanism using JTAG called a JTAG mailbox that can be used in the application.
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Table 10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV,
System Reset
SYSSNIV, System NMI
ADDRESS
019Eh
019Ch
INTERRUPT EVENT
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wake up (BOR)
08h
Security violation (BOR)
0Ah
SVSLIFG SVSL event (BOR)
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog timeout (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
DBDIFG FRAM double bit error (PUC)
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
MPUPW MPU password violation (PUC)
22h
CSPW CS password violation (PUC)
24h
MPUSEGIIFG information memory segment violation (PUC)
26h
MPUSEG1IFG segment 1 memory violation (PUC)
28h
MPUSEG2IFG segment 2 memory violation (PUC)
2Ah
MPUSEG3IFG segment 3 memory violation (PUC)
2Ch
Reserved
2Eh
Reserved
30h to 3Eh
No interrupt pending
00h
DBDIFG FRAM double bit error
02h
ACCTIMIFG access time error
04h
ACCVIFG access violation
0Eh
VMAIFG Vacant memory access
10h
JMBINIFG JTAG mailbox input
12h
JMBOUTIFG JTAG mailbox output
14h
SBDIFG FRAM single bit error
Reserved
SYSUNIV, User NMI
019Ah
VALUE
Highest
Lowest
Highest
16h
18h to 1Eh
No interrupt pending
00h
NMIFG NMI pin
02h
OFIFG oscillator fault
04h
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
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PRIORITY
Lowest
Highest
Lowest
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DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC10_B conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
Table 11. DMA Trigger Assignments
TRIGGER
CHANNEL 0
CHANNEL 1
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB1CCR0 CCIFG
(2)
TB1CCR2 CCIFG
(2)
TB1CCR2 CCIFG
(2)
TB1CCR2 CCIFG
(2)
11
TB2CCR0 CCIFG
(3)
TB2CCR0 CCIFG
(3)
TB2CCR0 CCIFG
(3)
12
TB2CCR2 CCIFG
(3)
TB2CCR2 CCIFG
(3)
TB2CCR2 CCIFG
(3)
10
TB1CCR0 CCIFG
(2)
TB1CCR0 CCIFG
(2)
13
Reserved
Reserved
Reserved
14
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
15
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
16
17
18
(1)
(2)
(3)
(4)
(5)
(6)
CHANNEL 2
6
9
28
(1)
UCA1RXIFG
(4)
UCA1TXIFG
(4)
UCB0RXIFG0
UCA1RXIFG
(4)
UCA1TXIFG
(4)
UCB0RXIFG0
UCA1RXIFG
(4)
UCA1TXIFG
(4)
UCB0RXIFG0
19
UCB0TXIFG0
UCB0TXIFG0
UCB0TXIFG0
20
UCB0RXIFG1
UCB0RXIFG1
UCB0RXIFG1
21
UCB0TXIFG1
UCB0TXIFG1
UCB0TXIFG1
22
UCB0RXIFG2
UCB0RXIFG2
UCB0RXIFG2
23
UCB0TXIFG2
UCB0TXIFG2
UCB0TXIFG2
24
UCB0RXIFG3
UCB0RXIFG3
UCB0RXIFG3
25
UCB0TXIFG3
UCB0TXIFG3
UCB0TXIFG3
(5)
ADC10IFGx
27
Reserved
Reserved
Reserved
28
Reserved
Reserved
Reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
31
DMAE0
DMAE0
(6)
ADC10IFGx
(5)
26
(6)
ADC10IFGx
(5)
DMA1IFG
DMAE0
(6)
If a reserved trigger source is selected, no trigger is generated.
Only on devices with TB1, otherwise reserved
Only on devices with TB2, otherwise reserved
Only on devices with eUSCI_A1, otherwise reserved
Only on devices with ADC, otherwise reserved
This function is not available on YFF package types.
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Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each eUSCI module contains two portions,
A and B.
The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430FR572x and MSP430FR573x series include one or two eUSCI_An modules (eUSCI_A0,
eUSCI_A1) and one eUSCI_Bn module (eUSCI_B).
TA0, TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. Each can
support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 12. TA0 Signal Connections
INPUT PIN NUMBER
RHA
RGE, YFF
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
3-P1.2
3-P1.2,
A3‑P1.2
7-P1.2
7-P1.2
TA0CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
OUTPUT PIN NUMBER
RHA
RGE, YFF
DA
PW
3-P1.2
3-P1.2,
A3‑P1.2
7-P1.2
7-P1.2
TA0CLK
TACLK
28-P1.6
16-P1.6,
E2‑P1.6
30-P1.6
22-P1.6
TA0.0
CCI0A
28-P1.6
16-P1.6 ,
E2‑P1.6
30-P1.6
22-P1.6
34-P2.3
N/A
36-P2.3
27-P2.3
TA0.0
CCI0B
TA0.0
34-P2.3
N/A
36-P2.3
27-P2.3
DVSS
GND
DVCC
VCC
TA0.1
CCI1A
1-P1.0
1-P1.0 , N/A
5-P1.0
5-P1.0
CDOUT
(internal)
CCI1B
TA0.1
ADC10
(internal) (1)
ADC10SHSx
= {1}
ADC10
(internal) (1)
ADC10SHSx
= {1}
ADC10
(internal) (1)
ADC10SHSx
= {1}
ADC10
(internal) (1)
ADC10SHSx
= {1}
2-P1.1
2-P1.1,
A2‑P1.1
6-P1.1
6-P1.1
1-P1.0
2-P1.1
(1)
1-P1.0,
N/A
2-P1.1,
A2‑P1.1
5-P1.0
6-P1.1
5-P1.0
6-P1.1
DVSS
GND
DVCC
VCC
TA0.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR0
CCR1
CCR2
TA0
TA1
TA2
TA0.2
Only on devices with ADC
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Table 13. TA1 Signal Connections
RHA
RGE, YFF
INPUT PIN NUMBER
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
2-P1.1
2-P1.1,
A2‑P1.1
6-P1.1
6-P1.1
TA1CLK
TACLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
2-P1.1
2-P1.1,
A2‑P1.1
6-P1.1
6-P1.1
TA1CLK
TACLK
29-P1.7
17-P1.7,
E3‑P1.7
31-P1.7
23-P1.7
TA1.0
CCI0A
35-P2.4
N/A
37-P2.4
28-P2.4
TA1.0
CCI0B
DVSS
GND
3-P1.2
8-P1.3
30
3-P1.2, N/A
4-P1.3,
A4‑P1.3
7-P1.2
12-P1.3
7-P1.2
8-P1.3
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DVCC
VCC
TA1.1
CCI1A
CDOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TA1.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
CCR0
CCR1
CCR2
TA0
TA1
TA2
TA1.0
OUTPUT PIN NUMBER
RHA
RGE, YFF
DA
PW
29-P1.7
17-P1.7,
E3‑P1.7
31-P1.7
23-P1.7
35-P2.4
N/A
37-P2.4
28-P2.4
3-P1.2
3-P1.2, N/A
7-P1.2
7-P1.2
8-P1.3
4-P1.3,
A4‑P1.3
12-P1.3
8-P1.3
TA1.1
TA1.2
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MSP430FR572x
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SLAS639D – JULY 2011 – REVISED AUGUST 2012
TB0, TB1, TB2
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each. Each
can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 14. TB0 Signal Connections
RHA
RGE, YFF
INPUT PIN NUMBER
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
21-P2.0
13-P2.0,
E5‑P2.0
23-P2.0
19-P2.0
TB0CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
21-P2.0
13-P2.0,
E5‑P2.0
23-P2.0
19-P2.0
TB0CLK
TBCLK
22-P2.1
14-P2.1,
D3‑P2.1
24-P2.1
20-P2.1
TB0.0
CCI0A
17-P2.5
N/A
19-P2.5
15-P2.5
TB0.0
CCI0B
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
CCR0
DVSS
9-P1.4
10-P1.5
(1)
5-P1.4,
B4‑P1.4
6‑P1.5, A5P1.5
13-P1.4
14-P1.5
9-P1.4
19-P1.5
TB0
TB0.0
GND
DVCC
VCC
TB0.1
CCI1A
CDOUT
(internal)
CCI1B
DVSS
GND
DVCC
VCC
TB0.2
CCI2A
ACLK
(internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR1
CCR2
TB1
TB2
TB0.1
OUTPUT PIN NUMBER
RHA
RGE, YFF
DA
PW
22-P2.1
14-P2.1,
D3‑P2.1
24-P2.1
20-P2.1
17-P2.5
N/A
19-P2.5
15-P2.5
ADC10
(internal) (1)
ADC10SHSx
= {2}
ADC10
(internal) (1)
ADC10SHSx
= {2}
ADC10
(internal) (1)
ADC10SHSx
= {2}
ADC10
(internal) (1)
ADC10SHSx
= {2}
9-P1.4
5-P1.4,
B4‑P1.4
13-P1.4
9-P1.4
ADC10
(internal) (1)
ADC10SHSx
= {3}
ADC10
(internal) (1)
ADC10SHSx
= {3}
ADC10
(internal) (1)
ADC10SHSx
= {3}
ADC10
(internal) (1)
ADC10SHSx
= {3}
10-P1.5
6-P1.5,
A5‑P1.5
14-P1.5
19-P1.5
TB0.2
Only on devices with ADC
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Table 15. TB1 Signal Connections
RHA
RGE, YFF
INPUT PIN NUMBER
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
26-P3.6
N/A (DVSS),
N/A (DVSS)
28-P3.6
N/A (DVSS)
TB1CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
26-P3.6
N/A (DVSS),
N/A (DVSS)
28-P3.6
N/A (DVSS)
TB1CLK
TBCLK
23-P2.2
N/A (DVSS),
N/A (DVSS)
25-P2.2
N/A (DVSS)
TB1.0
CCI0A
18-P2.6
N/A (DVSS),
N/A (DVSS)
20-P2.6
N/A (DVSS)
TB1.0
CCI0B
DVSS
GND
DVCC
VCC
28-P1.6
N/A (DVSS),
N/A (DVSS)
30-P1.6
N/A (DVSS)
TB1.1
CCI1A
24-P3.4
N/A (DVSS),
N/A (DVSS)
26-P3.4
N/A (DVSS)
TB1.1
CCI1B
DVSS
GND
DVCC
VCC
29-P1.7
N/A (DVSS),
N/A (DVSS)
31-P1.7
N/A (DVSS)
TB1.2
CCI2A
25-P3.5
N/A (DVSS),
N/A (DVSS)
27-P3.5
N/A (DVSS)
TB1.2
CCI2B
DVSS
GND
DVCC
VCC
(1)
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
CCR0
CCR1
CCR2
TB0
TB1
TB2
TB1.0
TB1.1
TB1.2
RHA
RGE, YFF
INPUT PIN NUMBER
DA
PW
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
24-P3.4
N/A (DVSS),
N/A (DVSS)
26-P3.4
N/A (DVSS)
TB2CLK
TBCLK
ACLK
(internal)
ACLK
SMCLK
(internal)
SMCLK
24-P3.4
N/A (DVSS),
N/A (DVSS)
26-P3.4
N/A (DVSS)
TB2CLK
TBCLK
21-P2.0
N/A (DVSS),
N/A (DVSS)
23-P2.0
N/A (DVSS)
TB2.0
CCI0A
15-P4.0
N/A (DVSS),
N/A (DVSS)
N/A (DVSS)
N/A (DVSS)
TB2.0
CCI0B
DVSS
GND
DVCC
VCC
22-P2.1
N/A (DVSS),
N/A (DVSS)
24-P2.1
N/A (DVSS)
TB2.1
CCI1A
26-P3.6
N/A (DVSS),
N/A (DVSS)
28-P3.6
N/A (DVSS)
TB2.1
CCI1B
DVSS
GND
DVCC
VCC
23-P2.2
N/A (DVSS),
N/A (DVSS)
25-P2.2
N/A (DVSS)
TB2.2
CCI2A
27-P3.7
N/A (DVSS),
N/A (DVSS)
29-P3.7
N/A (DVSS)
TB2.2
CCI2B
DVSS
GND
DVCC
VCC
32
OUTPUT PIN NUMBER
RHA
RGE, YFF
DA
PW
23-P2.2
N/A
25-P2.2
N/A
18-P2.6
N/A
20-P2.6
N/A
28-P1.6
N/A
30-P1.6
N/A
24-P3.4
N/A
26-P3.4
N/A
29-P1.7
N/A
31-P1.7
N/A
25-P3.5
N/A
27-P3.5
N/A
RHA
RGE, YFF
DA
PW
21-P2.0
N/A
23-P2.0
N/A
15-P4.0
N/A
36-P4.0
N/A
22-P2.1
N/A
24-P2.1
N/A
26-P3.6
N/A
28-P3.6
N/A
23-P2.2
N/A
25-P2.2
N/A
27-P3.7
N/A
29-P3.7
N/A
TB1 is not present on all device types.
Table 16. TB2 Signal Connections
(1)
(1)
(1)
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
Timer
N/A
N/A
CCR0
CCR1
CCR2
TB0
TB1
TB2
TB2.0
TB2.1
TB2.2
OUTPUT PIN NUMBER
TB2 is not present on all device types.
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MSP430FR572x
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ADC10_B
The ADC10_B module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and a conversion result buffer. A window comparator with a
lower limit and an upper limit allows CPU-independent result monitoring with three window comparator interrupt
flags.
Comparator_D
The primary function of the Comparator_D module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
Shared Reference (REF)
The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM implemented on all devices has the
following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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Peripheral File Map
Table 17. Peripherals
BASE ADDRESS
OFFSET ADDRESS
RANGE
Special Functions (see Table 18)
0100h
000h-01Fh
PMM (see Table 19)
0120h
000h-010h
FRAM Control (see Table 20)
0140h
000h-00Fh
CRC16 (see Table 21)
0150h
000h-007h
Watchdog (see Table 22)
015Ch
000h-001h
CS (see Table 23)
0160h
000h-00Fh
SYS (see Table 24)
0180h
000h-01Fh
Shared Reference (see Table 25)
01B0h
000h-001h
Port P1/P2 (see Table 26)
0200h
000h-01Fh
Port P3/P4 (see Table 27)
0220h
000h-01Fh
Port PJ (see Table 28)
0320h
000h-01Fh
TA0 (see Table 29)
0340h
000h-02Fh
TA1 (see Table 30)
0380h
000h-02Fh
TB0 (see Table 31)
03C0h
000h-02Fh
TB1 (see Table 32)
0400h
000h-02Fh
TB2 (see Table 33)
0440h
000h-02Fh
Real-Time Clock (RTC_B) (see Table 34)
04A0h
000h-01Fh
32-Bit Hardware Multiplier (see Table 35)
04C0h
000h-02Fh
DMA General Control (see Table 36)
0500h
000h-00Fh
DMA Channel 0 (see Table 36)
0510h
000h-00Ah
DMA Channel 1 (see Table 36)
0520h
000h-00Ah
DMA Channel 2 (see Table 36)
0530h
000h-00Ah
MPU Control (see Table 37)
05A0h
000h-00Fh
eUSCI_A0 (see Table 38)
05C0h
000h-01Fh
eUSCI_A1 (see Table 39)
05E0h
000h-01Fh
eUSCI_B0 (see Table 40)
0640h
000h-02Fh
ADC10_B (see Table 41)
0700h
000h-03Fh
Comparator_D (see Table 42)
08C0h
000h-00Fh
MODULE NAME
34
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Table 18. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFRIE1
00h
SFR interrupt flag
SFRIFG1
02h
SFR reset pin control
SFRRPCR
04h
Table 19. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM Control 0
PMMCTL0
00h
PMM interrupt flags
PMMIFG
0Ah
PM5 Control 0
PM5CTL0
10h
Table 20. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
FRAM control 0
FRCTLCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 21. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CRC data input
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
Table 23. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
CS control 0
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
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Table 24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
JTAG mailbox output 1
SYSJMBO1
0Eh
Bus Error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
Table 25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
Shared reference control
REGISTER
REFCTL
OFFSET
00h
Table 26. Port P1/P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pullup/pulldown enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 interrupt vector word
P1IV
0Eh
Port P1 complement selection
P1SELC
16h
Port P1 interrupt edge select
P1IES
18h
Port P1 interrupt enable
P1IE
1Ah
Port P1 interrupt flag
P1IFG
1Ch
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pullup/pulldown enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Dh
Port P2 complement selection
P2SELC
17h
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
Port P2 interrupt enable
P2IE
1Bh
Port P2 interrupt flag
P2IFG
1Dh
36
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Table 27. Port P3/P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
Port P3 output
P3OUT
02h
Port P3 direction
P3DIR
04h
Port P3 pullup/pulldown enable
P3REN
06h
Port P3 selection 0
P3SEL0
0Ah
Port P3 selection 1
P3SEL1
0Ch
Port P3 interrupt vector word
P3IV
0Eh
Port P3 complement selection
P3SELC
16h
Port P3 interrupt edge select
P3IES
18h
Port P3 interrupt enable
P3IE
1Ah
Port P3 interrupt flag
P3IFG
1Ch
Port P4 input
P4IN
01h
Port P4 output
P4OUT
03h
Port P4 direction
P4DIR
05h
Port P4 pullup/pulldown enable
P4REN
07h
Port P4 selection 0
P4SEL0
0Bh
Port P4 selection 1
P4SEL1
0Dh
Port P4 complement selection
P4SELC
17h
Port P4 interrupt vector word
P4IV
1Eh
Port P4 interrupt edge select
P4IES
19h
Port P4 interrupt enable
P4IE
1Bh
Port P4 interrupt flag
P4IFG
1Dh
Table 28. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
Port PJ output
PJOUT
02h
Port PJ direction
PJDIR
04h
Port PJ pullup/pulldown enable
PJREN
06h
Port PJ selection 0
PJSEL0
0Ah
Port PJ selection 1
PJSEL1
0Ch
Port PJ complement selection
PJSELC
16h
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Table 29. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
Capture/compare control 0
TA0CCTL0
02h
Capture/compare control 1
TA0CCTL1
04h
Capture/compare control 2
TA0CCTL2
06h
TA0 counter register
TA0R
10h
Capture/compare register 0
TA0CCR0
12h
Capture/compare register 1
TA0CCR1
14h
Capture/compare register 2
TA0CCR2
16h
TA0 expansion register 0
TA0EX0
20h
TA0 interrupt vector
TA0IV
2Eh
Table 30. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
Capture/compare control 0
TA1CCTL0
02h
Capture/compare control 1
TA1CCTL1
04h
Capture/compare control 2
TA1CCTL2
06h
TA1 counter register
TA1R
10h
Capture/compare register 0
TA1CCR0
12h
Capture/compare register 1
TA1CCR1
14h
Capture/compare register 2
TA1CCR2
16h
TA1 expansion register 0
TA1EX0
20h
TA1 interrupt vector
TA1IV
2Eh
Table 31. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
TB0 register
TB0R
10h
Capture/compare register 0
TB0CCR0
12h
Capture/compare register 1
TB0CCR1
14h
Capture/compare register 2
TB0CCR2
16h
TB0 expansion register 0
TB0EX0
20h
TB0 interrupt vector
TB0IV
2Eh
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Table 32. TB1 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB1 control
TB1CTL
00h
Capture/compare control 0
TB1CCTL0
02h
Capture/compare control 1
TB1CCTL1
04h
Capture/compare control 2
TB1CCTL2
06h
TB1 register
TB1R
10h
Capture/compare register 0
TB1CCR0
12h
Capture/compare register 1
TB1CCR1
14h
Capture/compare register 2
TB1CCR2
16h
TB1 expansion register 0
TB1EX0
20h
TB1 interrupt vector
TB1IV
2Eh
Table 33. TB2 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB2 control
TB2CTL
00h
Capture/compare control 0
TB2CCTL0
02h
Capture/compare control 1
TB2CCTL1
04h
Capture/compare control 2
TB2CCTL2
06h
TB2 register
TB2R
10h
Capture/compare register 0
TB2CCR0
12h
Capture/compare register 1
TB2CCR1
14h
Capture/compare register 2
TB2CCR2
16h
TB2 expansion register 0
TB2EX0
20h
TB2 interrupt vector
TB2IV
2Eh
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Table 34. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
RTC control 1
RTCCTL1
01h
RTC control 2
RTCCTL2
02h
RTC control 3
RTCCTL3
03h
RTC prescaler 0 control
RTCPS0CTL
08h
RTC prescaler 1 control
RTCPS1CTL
0Ah
RTC prescaler 0
RTCPS0
0Ch
RTC prescaler 1
RTCPS1
0Dh
RTC interrupt vector word
RTCIV
0Eh
RTC seconds, RTC counter register 1
RTCSEC, RTCNT1
10h
RTC minutes, RTC counter register 2
RTCMIN, RTCNT2
11h
RTC hours, RTC counter register 3
RTCHOUR, RTCNT3
12h
RTC day of week, RTC counter register 4
RTCDOW, RTCNT4
13h
RTC days
RTCDAY
14h
RTC month
RTCMON
15h
RTC year low
RTCYEARL
16h
RTC year high
RTCYEARH
17h
RTC alarm minutes
RTCAMIN
18h
RTC alarm hours
RTCAHOUR
19h
RTC alarm day of week
RTCADOW
1Ah
RTC alarm days
RTCADAY
1Bh
Binary-to-BCD conversion register
BIN2BCD
1Ch
BCD-to-binary conversion register
BCD2BIN
1Eh
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Table 35. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
16-bit operand 1 – signed multiply
MPYS
02h
16-bit operand 1 – multiply accumulate
MAC
04h
16-bit operand 1 – signed multiply accumulate
MACS
06h
16-bit operand 2
OP2
08h
16 × 16 result low word
RESLO
0Ah
16 × 16 result high word
RESHI
0Ch
16 × 16 sum extension register
SUMEXT
0Eh
32-bit operand 1 – multiply low word
MPY32L
10h
32-bit operand 1 – multiply high word
MPY32H
12h
32-bit operand 1 – signed multiply low word
MPYS32L
14h
32-bit operand 1 – signed multiply high word
MPYS32H
16h
32-bit operand 1 – multiply accumulate low word
MAC32L
18h
32-bit operand 1 – multiply accumulate high word
MAC32H
1Ah
32-bit operand 1 – signed multiply accumulate low word
MACS32L
1Ch
32-bit operand 1 – signed multiply accumulate high word
MACS32H
1Eh
32-bit operand 2 – low word
OP2L
20h
32-bit operand 2 – high word
OP2H
22h
32 × 32 result 0 – least significant word
RES0
24h
32 × 32 result 1
RES1
26h
32 × 32 result 2
RES2
28h
32 × 32 result 3 – most significant word
RES3
2Ah
MPY32 control register 0
MPY32CTL0
2Ch
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Table 36. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
DMA channel 0 source address low
DMA0SAL
02h
DMA channel 0 source address high
DMA0SAH
04h
DMA channel 0 destination address low
DMA0DAL
06h
DMA channel 0 destination address high
DMA0DAH
08h
DMA channel 0 transfer size
DMA0SZ
0Ah
DMA channel 1 control
DMA1CTL
00h
DMA channel 1 source address low
DMA1SAL
02h
DMA channel 1 source address high
DMA1SAH
04h
DMA channel 1 destination address low
DMA1DAL
06h
DMA channel 1 destination address high
DMA1DAH
08h
DMA channel 1 transfer size
DMA1SZ
0Ah
DMA channel 2 control
DMA2CTL
00h
DMA channel 2 source address low
DMA2SAL
02h
DMA channel 2 source address high
DMA2SAH
04h
DMA channel 2 destination address low
DMA2DAL
06h
DMA channel 2 destination address high
DMA2DAH
08h
DMA channel 2 transfer size
DMA2SZ
0Ah
DMA module control 0
DMACTL0
00h
DMA module control 1
DMACTL1
02h
DMA module control 2
DMACTL2
04h
DMA module control 3
DMACTL3
06h
DMA module control 4
DMACTL4
08h
DMA interrupt vector
DMAIV
0Ah
Table 37. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
MPU control 0
MPUCTL0
00h
MPU control 1
MPUCTL1
02h
MPU Segmentation Register
MPUSEG
04h
MPU access management
MPUSAM
06h
42
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Table 38. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA0CTLW0
00h
eUSCI _A control word 1
UCA0CTLW1
03h
eUSCI_A baud rate 0
UCA0BR0
06h
eUSCI_A baud rate 1
UCA0BR1
07h
eUSCI_A modulation control
UCA0MCTLW
08h
eUSCI_A status
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
UCA0IRTCTL
12h
eUSCI_A IrDA receive control
UCA0IRRCTL
13h
eUSCI_A interrupt enable
UCA0IE
1Ah
eUSCI_A interrupt flags
UCA0IFG
1Ch
eUSCI_A interrupt vector word
UCA0IV
1Eh
Table 39. eUSCI_A1 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_A control word 0
UCA1CTLW0
00h
eUSCI _A control word 1
UCA1CTLW1
03h
eUSCI_A baud rate 0
UCA1BR0
06h
eUSCI_A baud rate 1
UCA1BR1
07h
eUSCI_A modulation control
UCA1MCTLW
08h
eUSCI_A status
UCA1STAT
0Ah
eUSCI_A receive buffer
UCA1RXBUF
0Ch
eUSCI_A transmit buffer
UCA1TXBUF
0Eh
eUSCI_A LIN control
UCA1ABCTL
10h
eUSCI_A IrDA transmit control
UCA1IRTCTL
12h
eUSCI_A IrDA receive control
UCA1IRRCTL
13h
eUSCI_A interrupt enable
UCA1IE
1Ah
eUSCI_A interrupt flags
UCA1IFG
1Ch
eUSCI_A interrupt vector word
UCA1IV
1Eh
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Table 40. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
eUSCI_B control word 0
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
eUSCI_B received address
UCB0ADDRX
1Ch
eUSCI_B address mask
UCB0ADDMASK
1Eh
eUSCI I2C slave address
UCB0I2CSA
20h
eUSCI interrupt enable
UCB0IE
2Ah
eUSCI interrupt flags
UCB0IFG
2Ch
eUSCI interrupt vector word
UCB0IV
2Eh
Table 41. ADC10_B Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_B Control register 0
ADC10CTL0
00h
ADC10_B Control register 1
ADC10CTL1
02h
ADC10_B Control register 2
ADC10CTL2
04h
ADC10_B Window Comparator Low Threshold
ADC10LO
06h
ADC10_B Window Comparator High Threshold
ADC10HI
08h
ADC10_B Memory Control Register 0
ADC10MCTL0
0Ah
ADC10_B Conversion Memory Register
ADC10MEM0
12h
ADC10_B Interrupt Enable
ADC10IE
1Ah
ADC10_B Interrupt Flags
ADC10IGH
1Ch
ADC10_B Interrupt Vector Word
ADC10IV
1Eh
Table 42. Comparator_D Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comparator_D control register 0
CDCTL0
00h
Comparator_D control register 1
CDCTL1
02h
Comparator_D control register 2
CDCTL2
04h
Comparator_D control register 3
CDCTL3
06h
Comparator_D interrupt register
CDINT
0Ch
Comparator_D interrupt vector word
CDIV
0Eh
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Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
–0.3 V to 4.1 V
Voltage applied to any pin (excluding VCORE)
(2)
–0.3 V to VCC + 0.3 V
Diode current at any device pin
Storage temperature range, Tstg
±2 mA
(3) (4) (5)
-55°C to 125°C
Maximum junction temperature, TJ
(1)
(2)
(3)
(4)
(5)
95°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg.
For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
Recommended Operating Conditions
MIN
(1)
NOM
Supply voltage during program execution and FRAM programming (AVCC = DVCC)
VSS
Supply voltage (AVSS = DVSS)
TA
Operating free-air temperature
I version
-40
85
TJ
Operating junction temperature
I version
-40
85
CVCORE
Required capacitor at VCORE
CVCC/
CVCORE
Capacitor ratio of VCC to VCORE
(1)
(2)
(3)
Processor frequency (maximum MCLK frequency)
3.6
0
UNIT
V
V
470
°C
°C
nF
10
No FRAM wait states
2 V ≤ VCC ≤ 3.6 V
fSYSTEM
2.0
MAX
VCC
(2)
(3)
With FRAM wait states
NACCESS = {2},
NPRECHG = {1},
2 V ≤ VCC ≤ 3.6 V
,
0
8.0
0
24.0
(3)
,
MHz
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
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Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current
(1) (2) (3)
over recommended operating free-air temperature (unless otherwise noted)
Frequency (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
VCC
1 MHz
TYP
IAM,
FRAM_UNI
IAM,0%
(6)
(7)
FRAM
3V
0.27
FRAM
0% cache hit
ratio
3V
0.42
4 MHz
MAX
TYP
8 MHz
MAX
0.58
0.73
1.2
TYP
16 MHz
MAX
1.0
1.6
2.2
TYP
(4)
(5)
MAX
1.53
2.8
2.3
20 MHz
TYP
(5)
MAX
1.9
2.9
2.8
24 MHz
TYP
(5)
2.2
3.6
3.45
IAM,50%
(7) (8)
FRAM
50% cache hit
ratio
3V
0.31
0.73
1.3
1.75
2.1
2.5
IAM,66%
(7) (8)
FRAM
66% cache hit
ratio
3V
0.27
0.58
1.0
1.55
1.9
2.2
IAM,75%
(7) (8)
FRAM
75% cache hit
ratio
3V
0.25
0.5
0.82
1.3
1.6
1.8
mA
4.3
mA
IAM,100%
(7) (8)
FRAM
100% cache hit
ratio
3V
0.2
0.43
0.3
0.55
0.42
0.8
0.73
1.15
0.88
1.3
1.0
1.5
IAM,
(8) (9)
RAM
3V
0.2
0.4
0.35
0.55
0.55
0.75
1.0
1.25
1.20
1.45
1.45
1.75
(1)
(2)
(3)
(4)
RAM
UNIT
MAX
mA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Characterized with program executing typical data processing.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency,
fMCLK,eff, decreases. The effective MCLK frequency is also dependent on the cache hit ratio. SMCLK is not affected by the number of
wait states or the cache hit ratio. The following equation can be used to compute fMCLK,eff:
fMCLK,eff,MHZ= fMCLK,MHZ x 1 / [# of wait states x ((1 - cache hit ratio percent/100)) + 1]
(5)
(6)
(7)
(8)
(9)
46
MSP430FR573x series only
Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every
four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz).MCLK = SMCLK. One wait state enabled.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz).MCLK = SMCLK. Three wait states enabled.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz).MCLK = SMCLK. Three wait states enabled.
See Figure 1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Active Mode Supply Current Into VCC Excluding External Current.
fACLK = 32786 Hz, fMCLK = fSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (fDCO = 8 MHz). MCLK = SMCLK.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (fDCO = 16 MHz). MCLK = SMCLK.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (fDCO = 20 MHz). MCLK = SMCLK.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (fDCO = 24 MHz). MCLK = SMCLK.
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Typical Active Mode Supply Current, No Wait States
2.50
IAM,0% (mA) = 0.2541 * (f, MHz) + 0.1724
2.00
IAM,50% (mA) = 0.1415 * (f, MHz) + 0.1669
IAM,66%(mA) = 0.1043 * (f, MHz) + 0.1646
IAM, mA
1.50
IAM,75% (mA) = 0.0814 * (f, MHz) + 0.1708
1.00
0.50
IAM,RAM (mA) = 0.05 * (f, MHz) + 0.150
IAM,100% (mA) = 0.0314 * (f, MHz) + 0.1708
0.00
0
1
2
3
4
5
6
7
8
9
fMCLK = f SMCLK , MHz
Figure 1. Typical Active Mode Supply Currents, No Wait States
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Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
-40°C
TYP
MAX
25°C
TYP
ILPM0,1MHz
Low-power mode 0
(3) (4)
2 V,
3V
166
175
LPM0,8MHz
Low-power mode 0
(5) (4)
2 V,
3V
170
177
LPM0,24MHz
Low-power mode 0
(6) (4)
2 V,
3V
274
ILPM2
Low-power mode 2
(7) (8)
2 V,
3V
ILPM3,XT1LF
Low-power mode 3, crystal
mode (9) (8)
ILPM3,VLO
Low-power mode 3,
VLO mode (10) (8)
ILPM4
Low-power mode 4
ILPM3.5
ILPM4.5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
48
(1) (2)
60°C
MAX
TYP
MAX
85°C
TYP
MAX
UNIT
190
225
µA
244
195
225
360
µA
285
340
315
340
455
µA
56
61
80
75
110
210
µA
2 V,
3V
3.4
6.4
15
18
48
150
µA
2 V,
3V
3.3
6.3
15
18
48
150
µA
(11) (8)
2 V,
3V
2.9
5.9
15
18
48
150
µA
Low-power mode 3.5
(12)
2 V,
3V
1.3
1.5
2.2
1.9
2.8
5.0
µA
Low-power mode 4.5
(13)
2 V,
3V
0.3
0.32
0.66
0.38
0.57
2.55
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 1 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz)
Current for brownout, high-side supervisor (SVSH) and low-side supervisor (SVSL) included.
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 8 MHz. DCORSEL = 0,
DCOFSELx = 3 (fDCO = 8 MHz)
Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = 24 MHz. DCORSEL = 1,
DCOFSELx = 3 (fDCO = 24 MHz)
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCORSEL = 0,
DCOFSELx = 3, DCO bias generator enabled.
Current for brownout, high-side supervisor (SVSH) included. Low-side supervisor disabled (SVSL).
Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention. RTC active.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
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Schmitt-Trigger Inputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
2V
0.80
1.40
3V
1.50
2.10
2V
0.45
1.10
3V
0.75
1.65
2V
0.25
0.8
3V
0.30
1.0
20
TYP
35
MAX
50
5
UNIT
V
V
V
kΩ
pF
Inputs – Ports P1 and P2 (1)
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t(int)
(1)
(2)
External interrupt timing
TEST CONDITIONS
(2)
External trigger pulse duration to set interrupt flag
VCC
2 V, 3 V
MIN
MAX
20
UNIT
ns
Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Leakage Current – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.x)
(1)
(2)
High-impedance leakage current
TEST CONDITIONS
(1) (2)
VCC
MIN
MAX
2 V, 3 V
-50
50
UNIT
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
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Outputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
(1)
(2)
TEST CONDITIONS
Low-level output voltage
I(OHmax) = –1 mA
(1)
I(OHmax) = –3 mA
(2)
I(OHmax) = –2 mA
(1)
I(OHmax) = –6 mA
(2)
I(OLmax) = 1 mA
(1)
I(OLmax) = 3 mA
(2)
I(OLmax) = 2 mA
(1)
I(OLmax) = 6 mA
(2)
VCC
2V
3V
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
UNIT
V
VSS VSS + 0.25
2V
VSS VSS + 0.60
V
VSS VSS + 0.25
3V
VSS VSS + 0.60
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fPx.y
Port output frequency
(with load)
Px.y
fPort_CLK
Clock output frequency
ACLK, SMCLK, or MCLK at configured output port,
CL = 20 pF, no DC loading (2)
(1)
(2)
50
(1) (2)
MIN
MAX
2V
16
3V
24
2V
16
3V
24
UNIT
MHz
MHz
A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
CL = 20 pF is connected from the output to VSS.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
16
V CC = 2.0 V
Px.y
TA = -40 ° C
IOL - Typical Low-Level Output Current - mA
14
TA = 25 ° C
12
TA = 85 ° C
10
8
6
4
2
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
V OL Low-Level Output Voltage - V
Figure 2.
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
35
IOL - Typical Low-Level Output Current - mA
V CC = 3.0 V
Px.y
TA = -40 ° C
30
TA = 25 ° C
TA = 85 ° C
25
20
15
10
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
V OL Low-Level Output Voltage - V
Figure 3.
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Typical Characteristics – Outputs (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
IOH - Typical High-Level Output Current - mA
V CC = 2.0 V
Px.y
-2
-4
-6
-8
-10
TA = 85 ° C
-12
TA = 25 ° C
-14
TA = -40 ° C
-16
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
V OH High-Level Output Voltage - V
Figure 4.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
IOH - Typical High-Level Output Current - mA
V CC = 3.0 V
Px.y
-5
-10
-15
-20
-25
TA = 85 ° C
-30
TA = 25 ° C
-35
TA = -40 ° C
-40
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
V OH High-Level Output Voltage - V
Figure 5.
52
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Crystal Oscillator, XT1, Low-Frequency (LF) Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ΔIVCC.LF
TEST CONDITIONS
Additional current consumption
XT1 LF mode from lowest drive
setting
60
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 9 pF
3V
90
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
3V
140
XTS = 0, XT1BYPASS = 0
fXT1,LF,SW
XT1 oscillator logic-level squarewave input frequency, LF mode
XTS = 0, XT1BYPASS = 1
fFault,LF
tSTART,LF
CL,eff
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Oscillator fault frequency, LF mode
(5)
Startup time, LF mode
(2) (3)
10
210
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
Integrated effective load
capacitance, LF mode (8)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
(9)
XTS = 0
UNIT
nA
Hz
50
kHz
kΩ
(6)
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 6 pF
(7)
32.768
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,LF = 32768 Hz, CL,eff = 6 pF
XTS = 0
MAX
32768
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
TYP
3V
XT1 oscillator crystal frequency,
LF mode
OALF
MIN
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
CL,eff = 9 pF, TA = 25°C,
fXT1,LF0
Oscillation allowance for
LF crystals (4)
VCC
30
70
%
10
10000
Hz
1000
3V
ms
1000
1
pF
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVE
settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but
should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
(b) For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Includes startup counter of 4096 clock cycles.
Requires external capacitors at both terminals.
Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin).
Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.
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Crystal Oscillator, XT1, High-Frequency (HF) Mode
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
XT1 oscillator crystal current HF
mode
IVCC,HF
VCC
MIN
TYP
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
175
fOSC = 8 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
TA = 25°C, CL,eff = 16 pF
300
MAX
3V
fOSC = 16 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 16 pF
UNIT
µA
350
fOSC = 24 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
550
fXT1,HF0
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0}
(2)
4
6
MHz
fXT1,HF1
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1}
(3)
6
10
MHz
fXT1,HF2
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2}
(3)
10
16
MHz
fXT1,HF3
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3}
(3)
16
24
MHz
fXT1,HF,SW
XT1 oscillator logic-level squarewave input frequency, HF mode
XTS = 1,
XT1BYPASS = 1
1
24
MHz
Oscillation allowance for
HF crystals (5)
OAHF
tSTART,HF
(1)
(2)
(3)
(4)
(5)
(6)
54
Startup time, HF mode
(6)
(4) (3)
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
fXT1,HF = 4 MHz, CL,eff = 16 pF
450
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1},
fXT1,HF = 8 MHz, CL,eff = 16 pF
320
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2},
fXT1,HF = 16 MHz, CL,eff = 16 pF
200
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
fXT1,HF = 24 MHz, CL,eff = 16 pF
200
fOSC = 4 MHz, XTS = 1,
XT2BYPASS = 0, XT2DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
8
fOSC = 24 MHz, XTS = 1,
XT2BYPASS = 0, XT2DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
Ω
3V
ms
2
To improve EMI on the XT1 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Maximum frequency of operation of the entire device cannot be exceeded.
Maximum frequency of operation of the entire device cannot be exceeded.
When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Includes startup counter of 4096 clock cycles.
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Crystal Oscillator, XT1, High-Frequency (HF) Mode (1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CL,eff
fFault,HF
TEST CONDITIONS
Integrated effective load
capacitance (7) (8)
XTS = 1
Duty cycle, HF mode
XTS = 1, Measured at ACLK,
fXT1,HF2 = 24 MHz
Oscillator fault frequency, HF mode
(9)
XTS = 1
VCC
MIN
TYP
MAX
1
40
(10)
50
145
UNIT
pF
60
%
900
kHz
(7)
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14
pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(9) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP
MAX
5
8.3
13
UNIT
fVLO
VLO frequency
Measured at ACLK
dfVLO/dT
VLO frequency temperature drift
Measured at ACLK
(1)
2 V to 3.6 V
0.5
%/°C
dfVLO/dVCC VLO frequency supply voltage drift
Measured at ACLK
(2)
2 V to 3.6 V
4
%/V
fVLO,DC
Measured at ACLK
(1)
(2)
Duty cycle
2 V to 3.6 V
MIN
2 V to 3.6 V
40
50
60
kHz
%
Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(2.0 to 3.6 V) – MIN(2.0 to 3.6 V)) / MIN(2.0 to 3.6 V) / (3.6 V – 2 V)
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DCO Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Measured at ACLK,
DCORSEL = 0
fDCO,LO
DCO frequency low, trimmed
Measured at ACLK,
DCORSEL = 1 (1)
Measured at ACLK,
DCORSEL = 0
fDCO,MID
DCO frequency mid, trimmed
Measured at ACLK,
DCORSEL = 1 (1)
Measured at ACLK,
DCORSEL = 0
fDCO,HI
DCO frequency high, trimmed
Measured at ACLK,
DCORSEL = 1 (1)
fDCO,DC
(1)
Duty cycle
Measured at ACLK, divide by 1,
No external divide, all DCO
settings
VCC
TA
MIN
TYP
MAX
2 V to 3.6 V
-40°C to 85°C
5.37
±3.5%
2 V to 3.6 V
0°C to 50°C
5.37
±2.0%
2 V to 3.6 V
-40°C to 85°C
16.2
±3.5%
2 V to 3.6 V
0°C to 50°C
16.2
±2.0%
2 V to 3.6 V
-40°C to 85°C
6.67
±3.5%
2 V to 3.6 V
0°C to 50°C
6.67
±2.0%
2 V to 3.6 V
-40°C to 85°C
20
±3.5%
2 V to 3.6 V
0°C to 50°C
20
±2.0%
2 V to 3.6 V
-40°C to 85°C
8
±3.5%
2 V to 3.6 V
0°C to 50°C
8
±2.0%
2 V to 3.6 V
-40°C to 85°C
23.8
±3.5%
2 V to 3.6 V
0°C to 50°C
23.8
±2.0%
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
2 V to 3.6 V
-40°C to 85°C
40
50
60
VCC
MIN
TYP
MAX
44
80
µA
%
MSP40FR573x devices only
MODOSC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IMODOSC
Current consumption
fMODOSC
MODOSC frequency
fMODOSC,DC
Duty cycle
56
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TEST CONDITIONS
Enabled
Measured at ACLK, divide by 1
2 V to 3.6 V
UNIT
2 V to 3.6 V
4.5
5.0
5.5
MHz
2 V to 3.6 V
40
50
60
%
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PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCORE(AM)
Core voltage, active mode
2 V ≤ DVCC ≤ 3.6 V
1.5
V
VCORE(LPM)
Core voltage, low-current mode
2 V ≤ DVCC ≤ 3.6 V
1.5
V
PMM, SVS, BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
5
ISVSH,LPM
SVSH current consumption, low power modes
VCC = 3.6 V
0.8
1.5
µA
VSVSH-
SVSH on voltage level, falling supply voltage
1.83
1.88
1.93
V
1.88
1.93
1.98
VSVSH+
SVSH off voltage level, rising supply voltage
µA
V
tPD,SVSH,
AM
SVSH propagation delay, active mode
dVCC/dt = 10 mV/µs
10
µs
tPD,SVSH,
LPM
SVSH propagation delay, low power modes
dVCC/dt = 1 mV/µs
30
µs
ISVSL
SVSL current consumption
0.3
0.5
µA
Wake-Up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA
MIN
TYP
MAX
UNIT
tWAKE-UP LPM0
Wake-up time from LPM0 to active
mode (1)
2 V, 3 V
-40°C to 85°C
0.58
1
µs
tWAKE-UP LPM12
Wake-up time from LPM1, LPM2 to
active mode (1)
2 V, 3 V
-40°C to 85°C
12
25
µs
tWAKE-UP LPM34
Wake-up time from LPM3 or LPM4 to
active mode (1)
2 V, 3 V
-40°C to 85°C
78
120
µs
2 V, 3 V
0°C to 85°C
310
575
µs
tWAKE-UP LPMx.5
Wake-up time from LPM3.5 or
LPM4.5 to active mode (1)
2 V, 3 V
-40°C to 85°C
310
1100
µs
210
µs
tWAKE-UP RESET
Wake-up time from RST to active
mode (2)
VCC stable
2 V, 3 V
-40°C to 85°C
170
tWAKE-UP BOR
Wake-up time from BOR or power-up
to active mode
dVCC/dt = 2400 V/s
2 V, 3 V
-40°C to 85°C
1.6
(1)
(2)
ms
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is executed.
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTA
Timer_A input clock frequency
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ± 10%
2 V, 3 V
tTA,cap
Timer_A capture timing
All capture inputs, Minimum pulse
duration required for capture
2 V, 3 V
(1)
MIN
TYP
MAX
UNIT
8
24
(1)
20
MHz
ns
MSP430FR573x devices only
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
fTB
Timer_B input clock frequency
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ± 10%
2 V, 3 V
tTB,cap
Timer_B capture timing
All capture inputs, Minimum pulse
duration required for capture
2 V, 3 V
(1)
MIN
TYP
MAX
UNIT
8
24
(1)
20
MHz
ns
MSP430FR573x devices only
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
5
MHz
UNIT
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
UCGLITx = 0
tt
UART receive deglitch time
(1)
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
(1)
58
2 V, 3 V
MIN
TYP
MAX
5
15
20
20
45
60
35
80
120
50
110
180
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
feUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
eUSCI input clock frequency
MAX
UNIT
fSYSTEM
MHz
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
TEST CONDITIONS
STE lead time, STE active to clock
STE lag time, Last clock to STE
inactive
STE access time, STE active to SIMO
data out
STE disable time, STE inactive to
SIMO high impedance
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
(2)
tHD,MO
SIMO output data hold time
(3)
(1)
(2)
(3)
VCC
MIN
(1)
TYP
MAX
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
1
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
55
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
35
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
40
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
30
UCLK edge to SIMO valid,
CL = 20 pF
CL = 20 pF
UNIT
UCxCLK
cycles
UCxCLK
cycles
ns
ns
2V
35
3V
35
2V
0
3V
0
ns
ns
2V
30
3V
30
2V
0
3V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 6 and Figure 7.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 6
and Figure 7.
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tSTE,DIS
tVALID,MO
tSTE,ACC
SIMO
Figure 6. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 7. SPI Master Mode, CKPH = 1
60
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eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
(2)
tHD,SO
SOMI output data hold time
(3)
(1)
(2)
(3)
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2V
7
3V
7
2V
0
3V
0
(1)
TYP
MAX
ns
ns
2V
65
3V
40
2V
40
3V
35
2V
2
3V
2
2V
5
3V
5
30
30
4
4
ns
ns
3V
3V
ns
ns
2V
2V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8 and Figure 9.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8
and Figure 9.
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 8. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 9. SPI Slave Mode, CKPH = 1
62
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eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 10)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2 V, 3 V
0
ns
tSU,DAT
Data setup time
2 V, 3 V
250
ns
tSU,STO
2 V, 3 V
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
2 V, 3 V
2 V, 3 V
0
4.0
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
ns
UCGLITx = 1
25
300
ns
12.5
150
ns
6.25
75
UCGLITx = 2
2 V, 3 V
UCGLITx = 3
UCCLTOx = 1
tTIMEOUT
Clock low timeout
UCCLTOx = 2
2 V, 3 V
UCCLTOx = 3
tSU,STA
tHD,STA
tHD,STA
ns
27
ms
30
ms
33
ms
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 10. I2C Mode Timing
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10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range
All ADC10 pins
IADC10_A
Operating supply current into
AVCC terminal, reference
current not included
fADC10CLK = 5 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
RI
Input MUX ON resistance
AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC
VCC
MIN
TYP
MAX
UNIT
2.0
3.6
V
0
AVCC
V
2V
90
140
3V
100
160
6
8
pF
36
kΩ
2.2 V
µA
10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fADC10CLK
fADC10OSC
tCONVERT
VCC
MIN
TYP
MAX
UNIT
2 V to
3.6 V
0.45
5
5.5
MHz
2 V to
3.6 V
4.5
4.5
5.5
MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
fADC10OSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
External fADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSEL ≠ 0
2 V to
3.6 V
For specified performance of ADC10 linearity
parameters
Internal ADC10 oscillator
ADC10DIV = 0, fADC10CLK = fADC10OSC
(MODOSC)
Conversion time
tADC10ON
Turn on settling time of
the ADC
The error in a conversion started after tADC10ON is
less than ±0.5 LSB,
Reference and input signal already settled
tSample
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an
error of less than ±0.5 LSB
(1)
2.67
µs
(1)
100
2V
1.5
3V
2.0
VCC
MIN
1.4
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
2 V to
3.6 V
-1.4
-1.1
1.1
ns
µs
12 × ADC10DIV × 1/fADC10CLK
10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
TYP
MAX
UNIT
EI
Integral
linearity error
ED
Differential
linearity error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
2 V to
3.6 V
-1
1
LSB
EO
Offset error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
2 V to
3.6 V
-6.5
6.5
mV
Gain error, external
reference
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
2 V to
3.6 V
-1.2
1.2
LSB
-4
4
%
-2
2
LSB
-4
4
%
EG
ET
(1)
64
Gain error, internal
reference (1)
Total unadjusted
error, external
reference
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–)
Total unadjusted
error, internal
reference (1)
2 V to
3.6 V
LSB
Error is dominated by the internal reference.
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REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
(1)
TYP
MAX
UNIT
VeREF+
Positive external reference voltage input
VeREF+ > VeREF–
(2)
1.4
AVCC
V
VeREF–
Negative external reference voltage input
VeREF+ > VeREF–
(3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference voltage
input
VeREF+ > VeREF–
(4)
1.4
AVCC
V
IVeREF+,
IVeREF–
Static input current
CVREF+, CVREF(1)
(2)
(3)
(4)
(5)
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V,
fADC10CLK = 5 MHz,
ADC10SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
-6
6
µA
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V,
fADC10CLK = 5 MHz,
ADC10SHTx = 8h,
Conversion rate 20 ksps
2.2 V, 3 V
-1
1
µA
Capacitance at VREF+ or VREF- terminal
10
(5)
µF
The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_B. Also see the MSP430FR57xx Family User's Guide (SLAU272).
REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VREF+
Positive built-in reference
voltage output
VCC
MIN
TYP
MAX
REFVSEL = {2} for 2.5 V, REFON = 1
TEST CONDITIONS
3V
2.4
2.5
2.6
REFVSEL = {1} for 2 V, REFON = 1
3V
1.92
2.0
2.08
REFVSEL = {0} for 1.5 V, REFON = 1
3V
1.44
1.5
1.56
REFVSEL = {0} for 1.5 V
2.0
REFVSEL = {1} for 2 V
2.2
REFVSEL = {2} for 2.5 V
2.7
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IREF+
Operating supply current into
AVCC terminal (1)
fADC10CLK = 5 MHz,
REFON = 1, REFBURST = 0
TREF+
Temperature coefficient of
built-in reference
REFVSEL = (0, 1, 2}, REFON = 1
PSRR_DC
tSETTLE
(1)
(2)
Power supply rejection ratio
(DC)
Settling time of reference
voltage (2)
3V
V
V
33
45
±35
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (0} for 1.5 V
1600
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (1} for 2 V
1900
AVCC = AVCC (min) - AVCC(max),
TA = 25°C, REFON = 1,
REFVSEL = (2} for 2.5 V
3600
AVCC = AVCC (min) - AVCC(max),
REFVSEL = (0, 1, 2}, REFON = 0 → 1
UNIT
30
µA
ppm/
°C
µV/V
µs
The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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REF, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VSENSOR
See
TEST CONDITIONS
(1)
TCSENSOR
VCC
MIN
ADC10ON = 1, INCH = 0Ah,
TA = 0°C
2 V, 3 V
ADC10ON = 1, INCH = 0Ah
2 V, 3 V
MAX
mV
2.55
mV/°C
tSENSOR(sample)
Sample time required if
channel 10 is selected (2)
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
3V
30
VMID
AVCC divider at channel 11
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
2V
0.97
1.0
1.03
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected (3)
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2 V, 3 V
1000
(2)
(3)
UNIT
790
2V
(1)
30
TYP
µs
V
ns
The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of the built-in
temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1050
Typical Temperature Sensor Voltage - mV
1000
950
900
850
800
750
700
650
600
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Ambient Temperature - Degrees Celsius
Figure 11. Typical Temperature Sensor Voltage
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Comparator_D
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Overdrive = 10 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV)
Propagation delay,
AVCC = 2 V to 3.6 V
tpd
Filter timer added to the
propagation delay of the
comparator
tfilter
MIN
TYP
MAX
UNIT
50
100
200
ns
Overdrive = 100 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV)
80
ns
Overdrive = 250 mV,
(VIN+ – 400 mV) to (VIN+ + 250 mV)
50
ns
CDF = 1, CDFDLY = 00
0.3
0.5
0.9
µs
CDF = 1, CDFDLY = 01
0.5
0.9
1.5
µs
CDF = 1, CDFDLY = 10
0.9
1.6
2.8
µs
CDF = 1, CDFDLY = 11
1.6
3.0
5.5
µs
mV
Voffset
Input offset
AVCC = 2 V to 3.6 V
-20
20
Vic
Common mode input
range
AVCC = 2 V to 3.6 V
0
AVCC - 1
V
Icomp(AVCC)
Comparator only
CDON = 1, AVCC = 2 V to 3.6 V
29
34
µA
Iref(AVCC)
Reference buffer and Rladder
CDREFLx = 01, AVCC = 2 V to 3.6 V
20
24
µA
tenable,comp
Comparator enable time
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
1.1
2.0
µs
tenable,rladder
Resistor ladder enable
time
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
1.1
2.0
µs
VCB_REF
Reference voltage for a
tap
VIN = voltage input to the R-ladder,
n = 0 to 31
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.5)
/ 32
V
VIN ×
(n + 0.5)
/ 32
FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DVCC(WRITE)
Write supply voltage
tWRITE
Word or byte write time
tACCESS
Read access time
tPRECHARGE
Precharge time
tCYCLE
TEST CONDITIONS
2.0
(1)
(1)
Cycle time, read or write operation
(1)
Read and write endurance
tRetention
(1)
MIN
Data retention duration
TYP
MAX
UNIT
3.6
V
120
ns
60
ns
60
ns
120
ns
1015
cycles
TJ = 25°C
100
TJ = 70°C
40
TJ = 85°C
10
years
When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2 V, 3 V
0.025
15
µs
tSBW,
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
1
µs
35
µs
En
tSBW,Rst
Spy-Bi-Wire return to normal operation time
fTCK
TCK input frequency, 4-wire JTAG
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
68
(2)
(1)
2 V, 3 V
19
2V
0
5
MHz
3V
0
10
MHz
2 V, 3 V
20
50
kΩ
35
Tools accessing the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
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INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.2, Input/Output With Schmitt Trigger
Pad Logic
External ADC reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
P1DIR.x
00
01
10
Direction
0: Input
1: Output
11
P1OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREFP1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
P1SEL0.x
P1SEL1.x
P1IN.x
EN
To modules
Bus
Keeper
D
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Table 43. Port P1 (P1.0 to P1.2) Pin Functions
PIN NAME (P1.x)
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
x
(1)
0
FUNCTION
P1.0 (I/O)
1
(1)
(2)
(3)
(4)
70
2
P1SEL0.x
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
0
TA0.1
1
DMAE0
0
RTCCLK
1
(3)
P1.1 (I/O)
TA0.CCI2A
0
TA0.2
1
TA1CLK
0
CDOUT
1
A1 (2) (3)
CD1 (2) (4)
VeREF+ (2)
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
P1SEL1.x
TA0.CCI1A
A0 (2) (3)
CD0 (2) (4)
VeREF- (2)
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
CONTROL BITS/SIGNALS
P1DIR.x
P1.2 (I/O)
(3)
TA1.CCI1A
0
TA1.1
1
TA0CLK
0
CDOUT
1
A2 (2) (3)
CD2 (2) (4)
X
This pin is tied to AVSS for YFF package types. All functions are therefore tied to ground at the pin.
Setting P1SEL1.x and P1SEL0.x disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically
disables output driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
P1DIR.x
00
01
From module 2
10
Direction
0: Input
1: Output
11
P1OUT.x
00
From module 1
01
From module 2
10
DVSS
11
DVSS
0
DVCC
1
1
P1.3/TA1.2/UCB0STE/A3/CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
P1SEL0.x
P1SEL1.x
P1IN.x
EN
To modules
Bus
Keeper
D
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Table 44. Port P1 (P1.3 to P1.5) Pin Functions
PIN NAME (P1.x)
P1.3/TA1.2/UCB0STE/A3/CD3
x
3
FUNCTION
P1.3 (I/O)
P1.4 (I/O)
72
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
(1)
0
1
X
(5)
A4 (2) (3)
CD4 (2) (4)
X
1
1
P1.5(I/O)
I: 0; O: 1
0
0
0
1
1
0
1
1
TB0.CCI2A
0
TB0.2
1
A5
CD5
(5)
0
TB0.1
(2) (3)
(2) (4)
(3)
(4)
0
TB0.CCI1A
UCA0CLK
(1)
(2)
0
1
UCA0STE
5
I: 0; O: 1
TA1.2
A3
CD3
P1.5/TB0.2/UCA0CLK/A5/CD5
P1SEL0.x
0
(2) (3)
(2) (4)
4
P1SEL1.x
TA1.CCI2A
UCB0STE
P1.4/TB0.1/UCA0STE/A4/CD4
CONTROL BITS/SIGNALS
P1DIR.x
X
(5)
X
Direction controlled by eUSCI_B0 module.
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit
Direction controlled by eUSCI_A0 module.
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Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P1REN.x
P1DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P1OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
From module 3
11
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
To modules
D
Table 45. Port P1 (P1.6 to P1.7) Pin Functions
PIN NAME (P1.x)
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
x
6
FUNCTION
P1.6 (I/O)
TB1.CCI1A
TB1.1
7
P1SEL1.x
P1SEL0.x
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
(1)
1
X
(2)
TA0.CCI0A
0
TA0.0
1
P1.7 (I/O)
TB1.CCI2A
TB1.2
I: 0; O: 1
(1)
0
(1)
UCB0SOMI/UCB0SCL
(1)
(2)
(3)
P1DIR.x
I: 0; O: 1
(1)
UCB0SIMO/UCB0SDA
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
CONTROL BITS/SIGNALS
1
X
(3)
TA1.CCI0A
0
TA1.0
1
Not available on all devices and package types.
Direction controlled by eUSCI_B0 module.
Direction controlled by eUSCI_A0 module.
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Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P2REN.x
P2DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
From module 3
11
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 46. Port P2 (P2.0 to P2.2) Pin Functions
PIN NAME (P2.x)
x
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
0
FUNCTION
P2.0 (I/O)
TB2.CCI0A
TB2.0
1
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
X
(2)
0
ACLK
1
P2.1 (I/O)
I: 0; O: 1
(1)
0
(1)
1
X
(2)
TB0.CCI0A
0
TB0.0
1
P2.2 (I/O)
TB2.CCI2A
TB2.2
I: 0; O: 1
(1)
TB1.CCI0A
TB1.0
0
(1)
1
UCB0CLK
74
0
0
1
UCA0RXD/UCA0SOMI
(1)
(2)
(3)
0
TB0CLK
TB2.1
2
P2SEL0.x
0
(1)
TB2.CCI1A
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL1.x
I: 0; O: 1
(1)
UCA0TXD/UCA0SIMO
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
CONTROL BITS/SIGNALS
P2DIR.x
(1)
X
(1)
(3)
0
1
Not available on all devices and package types.
Direction controlled by eUSCI_A0 module.
Direction controlled by eUSCI_B0 module.
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Port P2, P2.3 to P2.4, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P2REN.x
P2DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P2.3/TA0.0/UCA1STE/A6/CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
P2SEL0.x
P2SEL1.x
P2IN.x
EN
To modules
Bus
Keeper
D
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Table 47. Port P2 (P2.3 to P2.4) Pin Functions
PIN NAME (P2.x)
x
P2.3/TA0.0/UCA1STE/A6/CD10
3
FUNCTION
P2.3 (I/O)
P2.4 (I/O)
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
X
(1)
TA1.CCI0B
0
TA1.0
1
A7 (2)
CD11
76
0
1
UCA1CLK
(3)
(4)
I: 0; O: 1
TA0.0
A6
CD10
(1)
(2)
P2SEL0.x
0
(2) (3)
(2) (4)
4
P2SEL1.x
TA0.CCI0B
UCA1STE
P2.4/TA1.0/UCA1CLK/A7/CD11
CONTROL BITS/SIGNALS
P2DIR.x
(3)
(2) (4)
X
(1)
X
Direction controlled by eUSCI_A1 module.
Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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Port P2, P2.5 to P2.6, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
00
From module 2
10
01
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
From module 2
10
DVSS
11
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
To modules
D
Table 48. Port P2 (P2.5 to P2.6) Pin Functions
PIN NAME (P2.x)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
x
5
FUNCTION
P2.5(I/O)
(1)
TB0.CCI0B
TB0.0
6
I: 0; O: 1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
(1)
(1)
TB1.CCI0B
X
(2)
I: 0; O: 1
(1)
0
(1)
UCA1RXD/UCA1SOMI
(1)
(2)
P2SEL0.x
(1)
P2.6(I/O)
TB1.0
P2SEL1.x
(1)
UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
CONTROL BITS/SIGNALS
P2DIR.x
1
(1)
X
(2)
Not available on all devices and package types.
Direction controlled by eUSCI_A1 module.
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Port P2, P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
P2DIR.x
00
01
10
Direction
0: Input
1: Output
11
P2OUT.x
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P2.7
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
To modules
D
Table 49. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
P2.7
(1)
78
x
7
FUNCTION
P2.7(I/O)
(1)
CONTROL BITS/SIGNALS
P2DIR.x
P2SEL1.x
P2SEL0.x
I: 0; O: 1
0
0
Not available on all devices and package types.
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SLAS639D – JULY 2011 – REVISED AUGUST 2012
Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P3REN.x
P3DIR.x
00
01
10
Direction
0: Input
1: Output
11
P3OUT.x
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
P3SEL0.x
P3SEL1.x
P3IN.x
EN
To modules
1
Bus
Keeper
D
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Table 50. Port P3 (P3.0 to P3.3) Pin Functions
PIN NAME (P3.x)
P3.0/A12/CD12
x
0
FUNCTION
P3.0 (I/O)
A12 (1) (2)
CD12 (1) (3)
P3.1/A13/CD13
1
P3.1 (I/O)
(1) (2)
(1) (3)
A13
CD13
P3.2/A14/CD14
2
P3.2 (I/O)
(1) (2)
(1) (3)
A14
CD14
P3.3/A15/CD15
3
P3.3 (I/O)
A15 (1) (2)
CD15 (1) (3)
(1)
(2)
(3)
80
CONTROL BITS/SIGNALS
P3DIR.x
P3SEL1.x
P3SEL0.x
I: 0; O: 1
0
0
X
1
1
I: 0; O: 1
0
0
X
1
1
I: 0; O: 1
0
0
X
1
1
I: 0; O: 1
0
0
X
1
1
Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Not available on all devices and package types.
Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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Port P3, P3.4 to P3.6, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
P3DIR.x
00
01
10
Direction
0: Input
1: Output
11
P3OUT.x
DVSS
0
DVCC
1
1
00
From module 1
01
DVSS
10
From module 2
11
P3.4/TB1.1/TB2CLK/SMCLK
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
To modules
D
Table 51. Port P3 (P3.4 to P3.6) Pin Functions
PIN NAME (P3.x)
P3.4/TB1.1/TB2CLK/SMCLK
x
4
FUNCTION
(1)
P3.4 (I/O)
TB1.CCI1B
TB1.1
(1)
SMCLK
5
P3.6/TB2.1/TB1CLK
6
(1)
(1)
(1)
TB1CLK
0
1
1
1
0
0
0
1
1
1
1
I: 0; O: 1
0
0
0
1
1
1
0
I: 0; O: 1
0
1
TB2.CCI1B
(1)
(1)
(1)
P3.6 (I/O)
TB2.1
0
1
(1)
TB1.CCI2B
CDOUT
P3SEL0.x
0
0
(1)
P3.5 (I/O)
TB1.2
P3SEL1.x
I: 0; O: 1
1
(1)
TB2CLK
P3.5/TB1.2/CDOUT
(1)
CONTROL BITS/SIGNALS
P3DIR.x
(1)
0
1
(1)
0
Not available on all devices and package types.
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Port P3, P3.7, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
P3DIR.x
00
01
10
Direction
0: Input
1: Output
11
P3OUT.x
00
From module 1
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
P3.7/TB2.2
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
To modules
D
Table 52. Port P3 (P3.7) Pin Functions
PIN NAME (P3.x)
P3.7/TB2.2
x
7
FUNCTION
P3.7 (I/O)
(1)
TB2.CCI2B
TB2.2
(1)
82
(1)
(1)
CONTROL BITS/SIGNALS
P3DIR.x
P3SEL1.x
P3SEL0.x
I: 0; O: 1
0
0
0
1
0
1
Not available on all devices and package types.
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Port P4, P4.0, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
00
01
10
Direction
0: Input
1: Output
11
P4OUT.x
00
From module 1
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
P4.0/TB2.0
P4SEL0.x
P4SEL1.x
P4IN.x
Bus
Keeper
EN
To modules
D
Table 53. Port P4 (P4.0) Pin Functions
PIN NAME (P4.x)
P4.0/TB2.0
x
0
FUNCTION
P4.0 (I/O)
(1)
TB2.CCI0B
TB2.0
(1)
(1)
(1)
CONTROL BITS/SIGNALS
P4DIR.x
P4SEL1.x
P4SEL0.x
I: 0; O: 1
0
0
0
1
0
1
Not available on all devices and package types.
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Port P4, P4.1, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
P4DIR.x
00
01
10
Direction
0: Input
1: Output
11
P4OUT.x
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
P4.1
P4SEL0.x
P4SEL1.x
P4IN.x
Bus
Keeper
EN
To modules
D
Table 54. Port P4 (P4.1) Pin Functions
PIN NAME (P4.x)
P4.1
(1)
84
x
1
FUNCTION
P4.1 (I/O)
(1)
CONTROL BITS/SIGNALS
P4DIR.x
P4SEL1.x
P4SEL0.x
I: 0; O: 1
0
0
Not available on all devices and package types.
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Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
To Comparator
From Comparator
CDPD.x
Pad Logic
From JTAG
From JTAG
From JTAG
1
PJREN.x
0
00
PJDIR.x
1
01
10
DVSS
0
DVCC
1
0
Direction
0: Input
1: Output
11
1
JTAG enable
00
PJOUT.x
From module 1
01
1
DVSS
10
0
DVSS
11
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJSEL0.x
PJSEL1.x
PJIN.x
Bus
Keeper
EN
D
To modules
and JTAG
To Comparator
From Comparator
CDPD.x
Pad Logic
From JTAG
From JTAG
From JTAG
1
PJREN.x
PJDIR.x
0
00
1
01
10
DVSS
0
DVCC
1
0
Direction
0: Input
1: Output
11
1
JTAG enable
PJOUT.x
00
DVSS
01
1
DVSS
10
0
DVSS
11
PJ.3/TCK/CD9
PJSEL0.x
PJSEL1.x
PJIN.x
EN
To modules
and JTAG
Bus
Keeper
D
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Table 55. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
PJ.0/TDO/TB0OUTH/SMCLK/CD6
x
0
FUNCTION
PJ.0 (I/O)
TDO
(2)
(3)
1
2
(2)
TDI/TCLK
(3) (4)
86
1
X
1
I: 0; O: 1
0
0
X
X
X
0
1
1
1
1
X
PJ.2 (I/O)
(2)
I: 0; O: 1
0
0
(3) (4)
X
X
X
TB2OUTH
0
ACLK
1
0
1
1
PJ.3 (I/O)
CD9
(4)
1
0
TCK
(1)
(2)
(3)
0
MCLK
CD8
3
0
X
TB1OUTH
TMS
PJ.3/TCK/CD9
0
X
1
(3) (4)
(2)
(1)
PJSEL0.x
X
0
PJ.1 (I/O)
PJSEL1.x
I: 0; O: 1
SMCLK
CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJDIR.x
TB0OUTH
CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
CONTROL BITS/ SIGNALS
X
1
I: 0; O: 1
0
0
X
X
X
X
1
1
X = Don't care
Default condition
The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
Pad Logic
To XT1 XIN
PJREN.4
PJDIR.4
00
01
10
Direction
0: Input
1: Output
11
PJOUT.4
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.4/XIN
PJSEL0.4
PJSEL1.4
PJIN.4
EN
To modules
Bus
Keeper
D
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Pad Logic
To XT1 XOUT
PJSEL0.4
XT1BYPASS
PJREN.5
PJDIR.5
00
01
10
Direction
0: Input
1: Output
11
PJOUT.5
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.5/XOUT
PJSEL0.5
PJSEL1.5
PJIN.5
Bus
Keeper
EN
To modules
D
Table 56. Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P7.x)
PJ.4/XIN
x
4
FUNCTION
PJ.4 (I/O)
XIN crystal mode
XIN bypass mode
PJ.5/XOUT
5
(2)
(2)
PJ.5 (I/O)
XOUT crystal mode
(3)
PJ.5 (I/O)
(1)
(2)
(3)
(4)
88
(4)
PJDIR.x
PJSEL1.5
I: 0; O: 1
X
X
X
X
X
(1)
PJSEL0.4
XT1
BYPASS
0
0
X
0
1
0
PJSEL0.5 PJSEL1.4
X
X
X
0
1
1
I: 0; O: 1
0
0
0
0
X
X
X
X
0
1
0
I: 0; O: 1
X
X
0
1
1
X = Don't care
Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
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DEVICE DESCRIPTORS (TLV)
The following tables list the complete contents of the device descriptor tag-length-value (TLV) structure for each
device type.
Table 57. Device Descriptor Table
Info Block
Die Record
FR5737
FR5736
FR5735
Value
Value
Value
Value
01A00h
05h
05h
05h
05h
05h
01A01h
05h
05h
05h
05h
05h
01A02h
per unit
per unit
per unit
per unit
per unit
Info length
CRC length
01A03h
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
03h
02h
01h
77h
76h
Device ID
01A05h
81h
81h
81h
81h
81h
Hardware revision
01A06h
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
08h
08h
08h
08h
08h
Die Record length
01A09h
0Ah
0Ah
0Ah
0Ah
0Ah
01A0Ah
per unit
per unit
per unit
per unit
per unit
01A0Bh
per unit
per unit
per unit
per unit
per unit
01A0Ch
per unit
per unit
per unit
per unit
per unit
01A0Dh
per unit
per unit
per unit
per unit
per unit
01A0Eh
per unit
per unit
per unit
per unit
per unit
01A0Fh
per unit
per unit
per unit
per unit
per unit
01A10h
per unit
per unit
per unit
per unit
per unit
01A11h
per unit
per unit
per unit
per unit
per unit
01A12h
per unit
per unit
per unit
per unit
per unit
01A13h
per unit
per unit
per unit
per unit
per unit
ADC10 Calibration
Tag
01A14h
13h
13h
13h
05h
13h
ADC10 Calibration
length
01A15h
10h
10h
10h
10h
10h
01A16h
per unit
per unit
NA
NA
per unit
01A17h
per unit
per unit
NA
NA
per unit
01A18h
per unit
per unit
NA
NA
per unit
Die X position
Die Y position
Test results
ADC Gain Factor
ADC Offset
(1)
FR5738
Value
Address
Lot/Wafer ID
ADC10
Calibration
FR5739
Description
CRC value
(1)
01A19h
per unit
per unit
NA
NA
per unit
ADC 1.5-V
Reference
Temp. Sensor 30°C
01A1Ah
per unit
per unit
NA
NA
per unit
01A1Bh
per unit
per unit
NA
NA
per unit
ADC 1.5-V
Reference
Temp. Sensor 85°C
01A1Ch
per unit
per unit
NA
NA
per unit
01A1Dh
per unit
per unit
NA
NA
per unit
ADC 2.0-V
Reference
Temp. Sensor 30°C
01A1Eh
per unit
per unit
NA
NA
per unit
01A1Fh
per unit
per unit
NA
NA
per unit
ADC 2.0-V
Reference
Temp. Sensor 85°C
01A20h
per unit
per unit
NA
NA
per unit
01A21h
per unit
per unit
NA
NA
per unit
ADC 2.5-V
Reference
Temp. Sensor 30°C
01A22h
per unit
per unit
NA
NA
per unit
01A23h
per unit
per unit
NA
NA
per unit
NA = Not applicable
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Table 57. Device Descriptor Table (1) (continued)
REF
Calibration
FR5739
FR5738
FR5737
FR5736
FR5735
Value
Value
Value
Value
Value
01A24h
per unit
per unit
NA
NA
per unit
01A25h
per unit
per unit
NA
NA
per unit
REF Calibration Tag
01A26h
12h
12h
12h
12h
12h
REF Calibration
length
01A27h
06h
06h
06h
06h
06h
REF 1.5-V
Reference
01A28h
per unit
per unit
per unit
per unit
per unit
01A29h
per unit
per unit
per unit
per unit
per unit
REF 2.0-V
Reference
01A2Ah
per unit
per unit
per unit
per unit
per unit
01A2Bh
per unit
per unit
per unit
per unit
per unit
REF 2.5-V
Reference
01A2Ch
per unit
per unit
per unit
per unit
per unit
01A2Dh
per unit
per unit
per unit
per unit
per unit
Description
Address
ADC 2.5-V
Reference
Temp. Sensor 85°C
Table 58. Device Descriptor Table
Info Block
FR5734
FR5733
FR5732
FR5731
FR5730
Value
Value
Value
Value
Value
05h
05h
05h
05h
05h
01A01h
05h
05h
05h
05h
05h
01A02h
per unit
per unit
per unit
per unit
per unit
01A03h
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
00h
7Fh
75h
7Eh
7Ch
Description
Address
Info length
01A00h
CRC length
CRC value
Die Record
Device ID
01A05h
81h
80h
81h
80h
80h
Hardware revision
01A06h
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
08h
08h
08h
08h
08h
Die Record length
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
0Ah
0Ah
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
per unit
01A0Bh
per unit
per unit
per unit
per unit
per unit
01A0Ch
per unit
per unit
per unit
per unit
per unit
01A0Dh
per unit
per unit
per unit
per unit
per unit
01A0Eh
per unit
per unit
per unit
per unit
per unit
01A0Fh
per unit
per unit
per unit
per unit
per unit
01A10h
per unit
per unit
per unit
per unit
per unit
01A11h
per unit
per unit
per unit
per unit
per unit
01A12h
per unit
per unit
per unit
per unit
per unit
01A13h
per unit
per unit
per unit
per unit
per unit
01A14h
13h
13h
13h
05h
13h
ADC10 Calibration
length
01A15h
10h
10h
10h
10h
10h
01A16h
per unit
NA
NA
per unit
per unit
01A17h
per unit
NA
NA
per unit
per unit
01A18h
per unit
NA
NA
per unit
per unit
01A19h
per unit
NA
NA
per unit
per unit
01A1Ah
per unit
NA
NA
per unit
per unit
01A1Bh
per unit
NA
NA
per unit
per unit
ADC Offset
ADC 1.5-V
Reference
Temp. Sensor 30°C
90
01A09h
01A0Ah
ADC10 Calibration
Tag
ADC Gain Factor
(1)
(1)
NA = Not applicable
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Table 58. Device Descriptor Table (1) (continued)
REF
Calibration
FR5734
FR5733
FR5732
FR5731
FR5730
Value
Value
Value
Value
Value
01A1Ch
per unit
NA
NA
per unit
per unit
01A1Dh
per unit
NA
NA
per unit
per unit
ADC 2.0-V
Reference
Temp. Sensor 30°C
01A1Eh
per unit
NA
NA
per unit
per unit
01A1Fh
per unit
NA
NA
per unit
per unit
ADC 2.0-V
Reference
Temp. Sensor 85°C
01A20h
per unit
NA
NA
per unit
per unit
01A21h
per unit
NA
NA
per unit
per unit
ADC 2.5-V
Reference
Temp. Sensor 30°C
01A22h
per unit
NA
NA
per unit
per unit
01A23h
per unit
NA
NA
per unit
per unit
ADC 2.5-V
Reference
Temp. Sensor 85°C
01A24h
per unit
NA
NA
per unit
per unit
01A25h
per unit
NA
NA
per unit
per unit
REF Calibration Tag
01A26h
12h
12h
12h
12h
12h
REF Calibration
length
01A27h
06h
06h
06h
06h
06h
REF 1.5-V
Reference
01A28h
per unit
per unit
per unit
per unit
per unit
01A29h
per unit
per unit
per unit
per unit
per unit
REF 2.0-V
Reference
01A2Ah
per unit
per unit
per unit
per unit
per unit
01A2Bh
per unit
per unit
per unit
per unit
per unit
REF 2.5-V
Reference
01A2Ch
per unit
per unit
per unit
per unit
per unit
01A2Dh
per unit
per unit
per unit
per unit
per unit
Description
Address
ADC 1.5-V
Reference
Temp. Sensor 85°C
Table 59. Device Descriptor Table
Info Block
FR5728
FR5727
FR5726
FR5725
Value
Value
Value
Value
Value
05h
05h
05h
05h
05h
Address
Info length
01A00h
CRC length
01A01h
05h
05h
05h
05h
05h
01A02h
per unit
per unit
per unit
per unit
per unit
01A03h
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
7Bh
7Ah
79h
74h
78h
Device ID
01A05h
80h
80h
80h
81h
80h
Hardware revision
01A06h
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
08h
08h
08h
08h
08h
Die Record length
01A09h
0Ah
0Ah
0Ah
0Ah
0Ah
01A0Ah
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
(1)
FR5729
Description
CRC value
Die Record
(1)
01A0Bh
per unit
per unit
per unit
per unit
per unit
01A0Ch
per unit
per unit
per unit
per unit
per unit
01A0Dh
per unit
per unit
per unit
per unit
per unit
01A0Eh
per unit
per unit
per unit
per unit
per unit
01A0Fh
per unit
per unit
per unit
per unit
per unit
01A10h
per unit
per unit
per unit
per unit
per unit
01A11h
per unit
per unit
per unit
per unit
per unit
01A12h
per unit
per unit
per unit
per unit
per unit
01A13h
per unit
per unit
per unit
per unit
per unit
NA = Not applicable
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Table 59. Device Descriptor Table (1) (continued)
ADC10
Calibration
FR5728
FR5727
FR5726
FR5725
Value
Value
Value
Value
Value
01A14h
13h
13h
13h
05h
13h
01A15h
10h
10h
10h
10h
10h
01A16h
per unit
per unit
NA
NA
per unit
01A17h
per unit
per unit
NA
NA
per unit
01A18h
per unit
per unit
NA
NA
per unit
Address
ADC10 Calibration
Tag
ADC10 Calibration
length
ADC Gain Factor
ADC Offset
REF
Calibration
FR5729
Description
01A19h
per unit
per unit
NA
NA
per unit
ADC 1.5-V
Reference
Temp. Sensor 30°C
01A1Ah
per unit
per unit
NA
NA
per unit
01A1Bh
per unit
per unit
NA
NA
per unit
ADC 1.5-V
Reference
Temp. Sensor 85°C
01A1Ch
per unit
per unit
NA
NA
per unit
01A1Dh
per unit
per unit
NA
NA
per unit
ADC 2.0-V
Reference
Temp. Sensor 30°C
01A1Eh
per unit
per unit
NA
NA
per unit
01A1Fh
per unit
per unit
NA
NA
per unit
ADC 2.0-V
Reference
Temp. Sensor 85°C
01A20h
per unit
per unit
NA
NA
per unit
01A21h
per unit
per unit
NA
NA
per unit
ADC 2.5-V
Reference
Temp. Sensor 30°C
01A22h
per unit
per unit
NA
NA
per unit
01A23h
per unit
per unit
NA
NA
per unit
ADC 2.5-V
Reference
Temp. Sensor 85°C
01A24h
per unit
per unit
NA
NA
per unit
01A25h
per unit
per unit
NA
NA
per unit
REF Calibration Tag
01A26h
12h
12h
12h
12h
12h
REF Calibration
length
01A27h
06h
06h
06h
06h
06h
REF 1.5-V
Reference
01A28h
per unit
per unit
per unit
per unit
per unit
01A29h
per unit
per unit
per unit
per unit
per unit
REF 2.0-V
Reference
01A2Ah
per unit
per unit
per unit
per unit
per unit
01A2Bh
per unit
per unit
per unit
per unit
per unit
REF 2.5-V
Reference
01A2Ch
per unit
per unit
per unit
per unit
per unit
01A2Dh
per unit
per unit
per unit
per unit
per unit
Table 60. Device Descriptor Table
Info Block
(1)
92
FR5724
FR5723
FR5722
FR5721
FR5720
Value
Value
Value
Value
Value
05h
05h
05h
05h
05h
Description
Address
Info length
01A00h
CRC length
01A01h
05h
05h
05h
05h
05h
01A02h
per unit
per unit
per unit
per unit
per unit
01A03h
per unit
per unit
per unit
per unit
per unit
Device ID
01A04h
73h
72h
71h
77h
70h
Device ID
01A05h
81h
81h
81h
80h
81h
Hardware revision
01A06h
per unit
per unit
per unit
per unit
per unit
Firmware revision
01A07h
per unit
per unit
per unit
per unit
per unit
Die Record Tag
01A08h
08h
08h
08h
08h
08h
Die Record length
01A09h
0Ah
0Ah
0Ah
0Ah
0Ah
CRC value
Die Record
(1)
NA = Not applicable
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Table 60. Device Descriptor Table (1) (continued)
FR5724
FR5723
FR5722
FR5721
FR5720
Value
Value
Value
Value
Value
01A0Ah
per unit
per unit
per unit
per unit
per unit
01A0Bh
per unit
per unit
per unit
per unit
per unit
01A0Ch
per unit
per unit
per unit
per unit
per unit
01A0Dh
per unit
per unit
per unit
per unit
per unit
01A0Eh
per unit
per unit
per unit
per unit
per unit
01A0Fh
per unit
per unit
per unit
per unit
per unit
01A10h
per unit
per unit
per unit
per unit
per unit
01A11h
per unit
per unit
per unit
per unit
per unit
01A12h
per unit
per unit
per unit
per unit
per unit
01A13h
per unit
per unit
per unit
per unit
per unit
ADC10 Calibration
Tag
01A14h
13h
13h
13h
05h
13h
ADC10 Calibration
length
01A15h
10h
10h
10h
10h
10h
01A16h
per unit
NA
NA
per unit
per unit
01A17h
per unit
NA
NA
per unit
per unit
01A18h
per unit
NA
NA
per unit
per unit
Description
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
ADC Gain Factor
ADC Offset
REF
Calibration
Address
01A19h
per unit
NA
NA
per unit
per unit
ADC 1.5-V
Reference
Temp. Sensor 30°C
01A1Ah
per unit
NA
NA
per unit
per unit
01A1Bh
per unit
NA
NA
per unit
per unit
ADC 1.5-V
Reference
Temp. Sensor 85°C
01A1Ch
per unit
NA
NA
per unit
per unit
01A1Dh
per unit
NA
NA
per unit
per unit
ADC 2.0-V
Reference
Temp. Sensor 30°C
01A1Eh
per unit
NA
NA
per unit
per unit
01A1Fh
per unit
NA
NA
per unit
per unit
ADC 2.0-V
Reference
Temp. Sensor 85°C
01A20h
per unit
NA
NA
per unit
per unit
01A21h
per unit
NA
NA
per unit
per unit
ADC 2.5-V
Reference
Temp. Sensor 30°C
01A22h
per unit
NA
NA
per unit
per unit
01A23h
per unit
NA
NA
per unit
per unit
ADC 2.5-V
Reference
Temp. Sensor 85°C
01A24h
per unit
NA
NA
per unit
per unit
01A25h
per unit
NA
NA
per unit
per unit
REF Calibration Tag
01A26h
12h
12h
12h
12h
12h
REF Calibration
length
01A27h
06h
06h
06h
06h
06h
REF 1.5-V
Reference
01A28h
per unit
per unit
per unit
per unit
per unit
01A29h
per unit
per unit
per unit
per unit
per unit
REF 2.0-V
Reference
01A2Ah
per unit
per unit
per unit
per unit
per unit
01A2Bh
per unit
per unit
per unit
per unit
per unit
REF 2.5-V
Reference
01A2Ch
per unit
per unit
per unit
per unit
per unit
01A2Dh
per unit
per unit
per unit
per unit
per unit
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
93
MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
www.ti.com
REVISION HISTORY
REVISION
SLAS639
94
COMMENTS
Product Preview release
SLAS639A
Updated Product Preview release including preliminary electrical specifications
SLAS639B
Changes throughout for updated Product Preview
SLAS639C
Production Data release
SLAS639D
Changed PW package options from Product Preview to Production Data.
Added information for YFF package option throughout as Product Preview.
Table 26 and Table 27, Changed offset of PxSELC registers.
Table 28, Added PJSELC register.
Table 29, Removed registers that do no apply (TA0CCTL3,4 and TA0CCR3,4)
Absolute Maximum Ratings, Changed low limit of Tstg from -40°C to -55°C.
FRAM, Added tRetention MIN values for TJ = 25°C and TJ = 70°C.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
MSP430FR5720IPWR
PREVIEW
TSSOP
PW
28
MSP430FR5720IRGER
ACTIVE
VQFN
RGE
24
MSP430FR5720IRGET
ACTIVE
VQFN
RGE
MSP430FR5721IDA
PREVIEW
TSSOP
MSP430FR5721IDAR
ACTIVE
MSP430FR5721IRHAR
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5721IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5722IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5722IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5722IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5723IDA
PREVIEW
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5723IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5723IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5723IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5724IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5724IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5724IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Addendum-Page 1
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Aug-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430FR5725IDA
PREVIEW
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5725IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5725IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5726IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5726IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5726IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5727IDA
PREVIEW
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5727IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5727IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5727IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5728IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5728IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5728IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5729IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5729IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5729IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5730IPW
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5730IRGER
ACTIVE
VQFN
RGE
24
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
3000
Addendum-Page 2
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Aug-2012
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
MSP430FR5730IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5731IDA
PREVIEW
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5731IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5731IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5731IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5732IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5732IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5732IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5733IDA
PREVIEW
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5733IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5733IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5733IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5734IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5734IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5734IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5735IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5735IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5735IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Addendum-Page 3
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
23-Aug-2012
Status
(1)
Package Type Package
Drawing
Pins
MSP430FR5736IPWR
PREVIEW
TSSOP
PW
28
MSP430FR5736IRGER
ACTIVE
VQFN
RGE
24
MSP430FR5736IRGET
ACTIVE
VQFN
RGE
MSP430FR5737IDA
PREVIEW
TSSOP
MSP430FR5737IDAR
ACTIVE
MSP430FR5737IRHAR
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5737IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5738IPWR
PREVIEW
TSSOP
PW
28
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSP430FR5738IRGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5738IRGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5739IDA
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5739IDAR
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
MSP430FR5739IRHAR
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
MSP430FR5739IRHAT
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 4
Samples
(Requires Login)
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2012
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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DLP® Products
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