AMIC A64S16161 2m x 16 bit low voltage super ram Datasheet

A64S16161
Preliminary
2M X 16 Bit Low Voltage Super RAM
Features
● Memory Cell : Dynamic memory( DRAM )
● Refresh: Completely free
1
2
3
4
5
6
A
LB#
OE#
A0
A1
A2
CE2
B
DQ8
UB#
A3
A4
CE1#
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
NC
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
WE#
DQ7
H
A18
A8
A9
A10
A11
A20
● Power Down: Control by CS2( No Data Retention )
● Byte Control : Capable of single byte operation
● Power Consumption: 100μA( Standby Current )
● Operating Temperature Range: -40’C~+85’C
● Composition:2,097,152 Word X 16 Bit
● Supply Power Voltage:2.70V to 3.30V
● Access Time: 70nS
● Access Time ( Page Access Read ): 30nS
● I/O Terminal :Input / Output Common 3-state output
Pin Description
Pin Name
Description
CS1#
Chip select 1 ( Low Active )
CS2
Chip select 2 ( High Active )
WE#
Write enable ( Low Active )
OE#
Output enable ( Low Active )
A0 to A20
Address Input ( A0 to A2 : Page Address)
IO0-7
Lower Byte Input / Output
IO8-15
Upper Byte Input / Output
LB#
Lower Byte Control ( Low Active )
UB#
Upper Byte Control ( Low Active )
VCC
Power Supply
VSS
Ground ( 0V)
Description
A64S16161 is a virtually static RAM, which uses DRAM type memory cells, but it has refresh transparency, so that you need
not to imply refresh operation. Furthermore the interface is completely compatible to a low power Asynchronous type SRAM, you
can operate as same as the Asynchronous SRAM.
A64S16161 is a 2,097,152 Words X 16 bit asynchronous random access memory on a monolithic CMOS chip with
marvelous low power consumption technology. Its low power and also low noise makes it ideal for mobile applications.
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A64S16161
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A8
A10
A11
Address Buffer
A9
Row Decoder
13
A7
8192
Memory Cell
A12
A13
256X16
A14
A15
8
A16
Column
256
Column Gate
A17
Decoder
A18
A19
A20
ATD
Control
16
Refresh
Control
CS1#
CS1#,CS2
CS2
Control
Input / Output Buffer
WE#
OE#
LB#
UB#
WE#,OE#
LB#,UB#
Control
I / O0 ．．．．．．．．．．．．．．
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I / O15
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A64S16161
Functions
Truth Table
A0-20
CS1#
CS2
WE#
OE#
LB#
UB#
I/O0~7
I/O8~15
Mode
V
L
H
H
L
L
L
Data-Out
Data-Out
Read
V
L
H
H
L
L
H
Data-Out
High-Z
Read
V
L
H
H
L
H
L
High-Z
Data-Out
Read
V
L
H
H
X
H
H
High-Z
High-Z
Output Disable
V
L
H
H
H
X
X
High-Z
High-Z
Output Disable
V
L
H
L
H
L
L
Data-In
Data-In
Write
V
L
H
L
H
L
H
Data-In
High-Z
Write
V
L
H
L
H
H
L
High-Z
Data-In
Write
X
H
H
X
X
X
X
High-Z
High-Z
Standby
X
X
L
X
X
X
X
High-Z
High-Z
Power Down*¹
V : Valid Address. X : High or Low .*1 No Data Retention
Read Operation
It is possible to control data width by LB# and UB# pins.
(1)Reading data from lower byte
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and LB #=L.
(2)Reading data from upper byte
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H and UB #=L.
(3)Reading date from both bytes
Date can be read when the address is set while holding CS1#=L, CS2=H, OE #=L , WE #= H , LB #=L and UB #=L.
(4)Page access read
Date can be read by changing A0-A2 when A3-A20 is set while holding CS1#=L, CS2=H, WE #=H, OE #=L, LB #=L and UB #=L.
Writing Operation
(1) Writing data into lower byte ( WE # control )
Data can be written by adding L pulse into WE # when the address is set while holding CS1#=L, CS2=H, OE #=H, LB #=L and
UB #=H.
The data on lower byte are latched up into the memory cell during WE # =L and LB # =L.
(2) Writing data into lower byte (LB # control)
Data can be written by adding L pulse into LB # when the address is set while holding CS1#=L, CS2 =H, OE#=H, UB# =H and
WE#=L.
The data on lower byte are latched up into the memory cell during WE# =L and LB# = L.
(3) Writing data into upper byte (WE # control)
Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and
UB #=L.
The data on upper byte are latched up into the memory cell during WE # =L and UB # = L.
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(4) Writing data into upper byte (UB # control)
Data can be written by adding L pulse into UB # when the address is set while holding CS1 #=L, CS2 =H, OE #=H, LB # =H and
WE #=L.
The data on upper byte are latched up into the memory cell during WE #=L and UB #=L.
(5) Writing data into both byte ( WE # control)
Data can be written by adding L pulse into WE # when the address is set while holding CS1 #=L, CS2=H, OE #=H, LB #=L and
UB #=L.
The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L.
(6) Writing data into both byte (LB #, UB # control)
Data can be written by adding L pulse into LB# and UB# when the address is set while holding CS1#=L, CS2=H, OE #=H and
WE #=L.
The data are latched up into the memory cell during WE #=L, LB #=L and UB #=L
Read or write with using both LB # and UB #, the timing edge of LB # and UB # must be same.
While I/O pins are in the output state, the data that is opposite to the output data should not be given.
Standby cycle
When CS1# is H, the device will be in the standby cycle. In this case data I/O pins are Hi-Z and all input pins are inhibited.
Power Down
When CS2 is L, the device will be in the power down. In this case, an internal refresh stops and the data might be lost.
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Parameter
Symbol
Ratings
Unit
Supply voltage
VCC
-0.5 to 3.6
V
Input voltage
VI
-0.5* to VCC+0.3
V
Input / Output voltage
V I/O
-0.5* to VCC+0.3
V
Input / Output voltage
PD
0.5
W
Operating temperature
Topr
-40 to 85
＇C
Storage temperature
Tstg
-65 to 150
｀C
* If pulse width is less than 5ns it is – 1.0V
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ELECTRICAL CHARACTERISTICS
DC Recommended Operating Conditions (Ta=-40~85＇C)
Parameter
Symbo1
Min
Max
Unit
VCC
2.70
3.30
V
VSS
0
0
V
VIH
VCC-0.3
VCC+0.3
V
VIL
-0.3*
0.3
V
Supply voltage
Input voltage
* If pulse width is less than 5ns it is –1.0V
DC ELECTRICAL CHARACTERISTICS
DC Characteristics (Ta=-40~85’C)
Parameter
Symbol
Condition
Min
Typ*¹
Max
Unit
Input leakage current
ILI
VI=0V to VCC
-1
﹣
1
µA
Output leakage current
ILO
LB# and UB#=H or CS1#=H or WE#=L
-1
﹣
1
µA
or OE#=H or CS2=L VI/O=0V to VCC
High level output voltage
VOH
IOH=-0.5ｍA
Vcc-0.3
﹣
﹣
V
Low level output voltage
VOL
IOL=0.5ｍA
﹣
﹣
0.3
V
Power Down Current
IDDPD
CS2≦0.2V
﹣
﹣
25
µA
Standby Current
IDDS
VCC-0.2V≦CS1#
﹣
60
100
µA
Operating current
IDDA1
I I/O=0ｍA, tcyc=70ns*²
﹣
25
30
ｍA
Operating current
IDDA2
I I/O=0ｍA, tcyc=1uS*²
﹣
3.0
3.5
ｍA
Operating current
IDDA3
I I/O=0ｍA, tcyc=70ns*³
-
20
30
ｍA
*1:Typical values are measured at Ta=25’C and VCC =3.0V
*2:Random access
*3:Page access read
Terminal Capacitance
(Ta=25’C f=1MHz)
Parameter
Symbol
Conditions
Min
Max
Unit
Input Capacitance
CI
VI=0V
﹣
8
pF
I/O Capacitance
C I/O
V I/O=0V
﹣
10
pF
Note：This parameter is measured by sampling , not of all products.
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A64S16161
AC Electrical Characteristics
Read Cycle (Ta = - 30 ~ 85’C)
Parameter
Symbol
Teat Conditions
Min
Max
Unit
Read cycle time
tRC
1
70
32000
nS
Page read cycle time
tRCP
1
30
32000
nS
Address access time
tACC
1
-
70
nS
Page address access time
tACCP
1
-
30
nS
CS1 # access time
tACS
1
-
70
nS
OE # access time
tOE
1
-
35
nS
LB # , UB # access time
tAB
1
-
25
nS
CS1# high pulse width
tC1H
1
30
-
nS
Address set up to OE L #
tASO
1
-5
-
nS
CS1 # output set time
tCHZ
2
0
-
nS
CS1 # output floating time
tCLZ
2
-
15
nS
LB # , UB # output set time
tBLZ
2
0
-
nS
LB # , UB # output floating time
tBLZ
2
-
15
nS
OE # output set time
tOLZ
2
0
-
nS
OE # output floating time
tOHZ
2
-
15
nS
Output hold time
tOH
1
5
-
nS
Parameter
Symbol
Test Conditions
Min
Max
Unit
Write cycle time
tWC
1
70
32000
nS
Chip select time
tCW
1
60
-
nS
CS1# H pulse width
tC1H
Address enable time
tAW
1
60
-
nS
Address set up time
tAS
1
0
-
nS
Write pulse width
tWP
1
40
-
nS
LB,UB select time
tBW
1
60
-
nS
Address hold time
tWR
1
0
-
nS
Data set up time
tDW
1
30
-
nS
Data hold time
tDH
1
0
-
nS
Write Cycle (Ta= - 40~85’C)
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Power Down Cycle(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
CS1 # H set up time for Power Down entry
tSSP
1
0
-
nS
CS1 # H hold time before Power Down exit
tSHP
1
0
-
nS
CS2 L pulse width
TC2LP
1
30
-
nS
CS1 # H hold time after Power Down exit
tHPD
1
300
-
µS
Power Up Timing Requirement(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
CS1 # CS2 set up time after Power Up
tSHU
1
0
-
nS
Standby hold time after Power Up
tHPU
1
300
-
µS
Data Retention Timing Requirement(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
A3 to A20 hold time during active
tBAH
1
-
32
nS
CS1# L hold time for A3 to A20 fix
tCSH
1
-
32
nS
Either tBAH or tCSH required for data retention.
Address Skew Timing Requirement(Ta= - 40~85＇C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Maximum address skew
tSKEW
1
-
10
nS
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A64S16161
TEST CONDITION 1
Input pulse voltage level
VCC – 0.3V / 0.3V
Input ascend / descend time
tr=tf=3nS
Input output timing reference level
2.0V/0.8V
Output load
CL=50pF(Includes Jig capacity)+1TTL
TEST CONDITION 2
Input pulse voltage level
VCC – 0.3V / 0.3V
Input ascend / descend time
tr=tf=3nS
Input output timing reference level
±100mV(The level change from stable voltage
Output load
CL=5pF(Includes Jig capacity)+1TTL
I/O
CL
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A64S16161
TIMING CHART
Read Cycle
tRC
Address
tACC
tOH
tACS
CS1#
tCHZ
tAB
LB#/UB#
tASO
tBHZ
tOE
OE#
tOLZ
tOHZ
tBLZ
Dout
tCLZ
CS2 and WE # must be H level for entire read cycle.
Read Cycle ( Page Access [1] )
Address
(A20-A3)
No Change
tRC
tRCP
tRCP
Address
(A2-A0)
CS1#
tCHZ
tACS
tACCP
tACCP
OE#
tOH
tOH
tOH
tCLZ
Dout
CS2 and WE # must be H level for entire read cycle.
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A64S16161
Read Cycle ( Page Access [2] )
Address
(A20-A3)
No Change
tRC
Address
(A2-A0)
tRCP
tRCP
tACS
CS1#
tASO
tOE
tCHZ
tACCP
tACCP
OE#
tOH
tOH
tOH
tOLZ
Dout
CS2 and WE # must be H level for entire read cycle.
Write Cycle ( WE # Control )
tWC
Address
tAW
tCW
CS1#
tBW
LB# / UB#
tWR
tAS
tWP
WE#
tDW
tDH
Din
CS2 and OE # must be H level for entire read cycle.
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A64S16161
Write Cycle ( LB # / UB # Control )
tWC
Address
tAW
tCW
CS1#
tBW
tWR
tAS
LB# / UB#
tWP
WE#
tDW
tDH
Din
CS2 and OE # must be H level for entire read cycle.
Standby
tC1H
CS1#
Active
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Standby
11
Active
AMIC Technology Corp.
A64S16161
Power Down Mode Entry / Exit
CS1#
tSHP
tHPD
tC2LP
CS2
tSSP
Power Up
CS1#
tSHU
tHPU
CS2
VCC
VCC(min)
Data Retention(1)
tBAH
Address
(A20-A3)
CS1#
This applies for both read and write.
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Data Retention (2)
tCSH
Address
(A20-A3)
No Change
CS1#
This applies for both read and write.
Address Skew(1)
A0-20
tSKEW
tRC / tWC
CS1#
tSKEW is from first address change to last address change
Address Skew(2)
A0-20
tRC / tWC
tSKEW
CS1#
tSKEW is from first address change to last address change
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A64S16161
Address Skew(3)
A0-20
tSKEW
CS1#
tSKEW is from first address change to stand-by
Reference External Wiring Diagram
Address Input
Control
Input / Output
I / O0
WE#
OE#
CS1#
CS2
BU#
LB#
I / O15
A0
A20
A64S16161
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A64S16161
Ordering Information
Part No.
A64S0616G-70I
Access Time (ns)
Operating Current
Max. (mA)
Power Down Mode
Standby Current
Max. (µA)
Package
70
30
25
48B Mini BGA
Note: -I is for industrial operating temperature range
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48 Pins FBGA Package outline drawing
-A0.10
6.00
PIN#1
-B-
CAVITY
0.96
C
C
8.00
C
0.08
0.25
-C-
SOLDER BALL
0.10
0.1
C
SEATING PLANE
DETAIL : A
0.2
“A＂
0.1
M
M
C
A
B
C
SECTION C-C
3.75
0.75
H
B
G
0.35
F
5.25
E
A
D
C
1
B
A
“B＂
2
DETAIL : B
1
2
3
4
5
6
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