IDT IDT71F432S66PF 32k x 32 mcache synchronous pipelined cache ram Datasheet

FEATURES:
•
•
•
•
•
•
•
•
•
•
Uses IDT's Fusion Memory technology
66 and 75 MHz speed grades
3-1-1-1 Pipelined Burst Read
3-1-1-1 Pipelined Burst Write
3-1-1-1-1-1-1-1... extended pipelined operation
Refresh overhead consumes less than 0.5% of cycles
Pinout is superset of industry standard PBSRAM
Interchangeable with PBSRAM in new designs
Compatible with MoSys MCache™ devices
Low operating and standby power consumption
1/3 the power of standard PBSRAM
• Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP)
DESCRIPTION:
The IDT71F432 MCache is a high-performance, low-power
replacement for standard 32K x 32 pipelined burst SRAM
(PBSRAM) in cache applications. The 71F432 is built using
IDT's Fusion Memory technology, which combines the performance of SRAM with the cost structure of DRAM. It is
ABOUT IDT'S Fusion Memory TECHNOLOGY:
What is Fusion Memory?
• Fusion Memory is a new kind of memory technology that
combines the high performance and ease-of-use of SRAM
with the manufacturing costs of DRAM.
Why are Fusion Memory chips so much smaller than SRAM?
• Traditional SRAM uses four or six transistors to make each
memory cell. Fusion Memory uses only one transistor for
each memory cell, so the memory array itself is only about
1/4 the size of an SRAM.
Is Fusion Memory the same as Dynamic Memory?
• Not exactly. While both Fusion Memory and DRAMs use
single-transistor dynamic cells for storage, Fusion Memories use much different designs for all the surrounding
circuitry, such as address drivers, sense amps, and control
circuitry. This gives Fusion Memory a performance level
that is much higher than DRAM.
fundamentally compatible with standard PBSRAM, with additional features to accommodate the internal DRAM operation
of the memory. These additional features are defined so that
71F432 compatible system controllers and properly implemented PC boards can work transparently with either the
71F432 or PBSRAM in cache memory applications.
Six pins, identified as No Connect (NC) on the standard
PBSRAM specifications, are used to support 71F432 operation. These pins are 5V supply (2), host bus W/R#, RESET#
and two proprietary functions labeled F0 and F1. When using
standard PBSRAM, these pins have no effect and the associated functions in the 71F432-compatible chipset are not
activated.
The 71F432 supports PBSRAM operating modes, including burst read (3-1-1-1), burst write (3-1-1-1) and pipelined
burst read or write (3-1-1-1-1-1...). As with all DRAM devices,
refresh is required. The memory is not accessible during the
refresh interval. Refresh occupies 0.5% of the clock cycles,
resulting in a system performance reduction of less than 0.1%.
How does the performance of Fusion Memory cache RAMs
compare with synchronous burst SRAMS?
• The Fusion Memory devices equal the performance of the
SRAMs they are designed to replace.
Are Fusion Memory and PBSRAMs interchangeable?
• A system designed to use the Fusion Memory cache RAMs
can use standard PBSRAMs instead.
What is the difference between MoSys MCache™ and IDT’s
Fusion Memory?
• MCache is MoSys’ trademark for their cache memory
devices. Fusion Memory is IDT’s trademark for the underlying technology. IDT will use the technology in other
products besides cache RAMs. The IDT71F432 and
MoSys' MCache devices are interchangeable.
SRAM
Fusion
Memory
Performance
Integrated Device Technology, Inc.
IDT71F432
32K x 32 MCache
SYNCHRONOUS PIPELINED
CACHE RAM
If Fusion Memory uses dynamic storage, are there refresh
cycles?
• Yes, but the refresh control is handled automatically and
nearly invisibly, using either on-chip circuitry or circuitry in
the chip set used with the memory device. The performance penalty is typically less than 0.1%.
DRAM
Cost
Fusion Memory™ Provides SRAM Performance at DRAM Cost
The IDT logo is a registered trademark and Fusion Memory and CacheRAM are trademarks of Integrated Device Technology
Pentium is a trademark of Intel Corp.
MCache is a trademark of MoSys, Inc.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 1996
©1996 Integrated Device Technology, Inc.
DSC-3555/3
13.1
1
IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
COMMERCIAL TEMPERATURE RANGE
256KB CACHE BLOCK DIAGRAM
CPU D[63:32]
CPU ADS#
CPU W/R#
BE#[8:5]
RESET#
CPU A[17:3]
RESET#
CPU W/R#
BE#[4:1]
CPU A[17:3]
CPU D[31:0]
CPU ADS#
PROCESSOR BUS
CLK
TAG
SRAM
ADSC#
CE#
CHIPSET
CACHE
CONTROLLER
OE#
ADV#
GW#
IDT71F432
IDT71F432
BWE#
32Kx32
32Kx32
F0, F1
CS0
CS1#
PIN DESCRIPTION SUMMARY
SYMBOL
DESCRIPTION
TYPE
A14 – A0
Address Inputs
Input
PIN NUMBER
48, 47, 46, 45, 44, 81, 82, 99,
100, 32, 33, 34, 35, 36, 37
CE#
Chip Enable
Input
98
CS0, CS1#
Chip Selects
Input
97, 92
OE#
Output Enable
Input
86
GW#
Global Write Enable
Input
88
BWE#
Byte Write Enable
Input
87
BW1#, BW2#, BW3#, BW4#
Individual Byte Write Selects
Input
93, 94, 95, 96
CLK
Clock
Input
89
ADV#
Burst Address Advance
Input
83
ADSC#
Address Status (Cache Controller)
Input
85
ADSP#
Address Status (Processor)
Input
84
I/O31-I/O0
Data Input/Output
I/O
29, 28, 25, 24, 23, 22, 19, 18, 13, 12,
9, 8, 7, 6, 3, 2, 79, 78, 75, 74, 73, 72,
69, 68, 63, 62, 59, 58, 57, 56, 53, 52
NC
Reserved for LBO# (burst order)
NC
31
NC
Reserved for ZZ (sleep)
NC
64
RESET#
Host Bus Reset Signal
Input
38
W/R#
Host Bus W/R#
Input
39
F0
Function 0
Special
43
F1
Function 1
Special
42
VDD5
5V Power
Pwr
16, 66
VDD
3.3V Power
Pwr
4, 11, 15, 20, 27, 41, 54, 61, 65, 70, 77, 91
VSS
Ground
Gnd
5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 77
3555 tbl 01
13.1
2
IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD5
VDD
VTERM
Rating
VDD5 Voltage with
Respect to VSS
VDD Voltage with
Respect to VSS
Terminal Voltage with
Respect to VSS
Com’l.
Unit
0 to 5.5
V
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
VDD5
0 to 3.6
–0.5 to VDD+0.5
V
V
TA
Operating Temperature
0 to +70
°C
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–55 to +125
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
20
mA
Parameter
Min.
Supply Voltage
4.75
(1)
Typ.
Max.
Unit
5.0
5.25
V
(1)
V
VDD
Supply Voltage
3.135
3.3
VSS
Supply Voltage
0
0
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
–0.3
(4)
3.6
0
V
(2,3)
—
VDD+0.3
—
V
0.8
V
NOTES:
3555 tbl 03
1. Power sequencing. VDD5 must be ≥ VDD at all times, including during
power up.
2. VIH (max.) must be observed at all times, including during power up.
3. VIH (max.) = VDD + 1.0V for pulse width less than tCYC/2, once per cycle.
4. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
3555 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE (VDD = 3.3V +10/-5%, VDD5 = 5V ± 5%)
Symbol
Parameter
Test Condition
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
—
5
µA
|ILO|
Output Leakage Current
Outputs disabled,
—
5
µA
VOL
Output Low Voltage
IOL = 5mA, VDD = Min.
—
0.4
V
VOH
Output High Voltage
IOH = –5mA, VDD = Min.
2.4
—
V
VOUT = 0V to VDD, VDD = Max.
3555 tbl 04
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING
TEMPERATURE AND SUPPLY VOLTAGE RANGE(1, 2) (VDD = 3.3V +10/-5%, VDD5 = 5V ± 5%)
71F432S75
Symbol
Parameter
IDD
Operating
Supply Current
Idle
ISB
Supply Current
ISB1
Clock Stopped
Supply Current
Test Condition
Device Selected, VIN ≥ VHD or ≤ VLD, Outputs Open,
VDD = Max., VDD5 = Max., f = fMAX(3)
Device Selected, ADSP#, ADSC#, GW#, BW#s,
ADV#≥ VHD, All Other Inputs ≥ VHD, Outputs Open,
VDD, VDD5 = Max.,f = fMAX(3)
Power
S
L
S
L
VIN ≥ VHD, Outputs Open, VDD = Max., VDD5 = Max.,
f = 0(3)
S
L
71F432S66
71F432L66
5V
3.3V
5V
3.3V
Supply Supply Supply Supply Unit
55
18
45
15
mA
35
10
30
2
25
1
mA
15
0.5
5
0.1
NOTES:
1. All values are maximum guaranteed values.
2. VHD = VDD - 0.2V, VLD = 0.2V
3. At f=fMAX,address inputs are cyclinng at maximum frequency of read cycles; f=0 means address input lines are changing.
13.1
5
2
0.1
0.1
mA
3555 tbl 05
3
IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VDD = 3.3V +10/-5%, TA = 0 to 70°C)
Symbol
Parameter
IDT71F432S75
IDT71F432S66
Min.
Max.
IDT71F432L66
Min.
Max.
Unit
Clock Parameters
tF
Clock Frequency
—
75
—
66.7
ns
tCYC
Clock Cycle Time
13.3
—
15
—
ns
tCH(1)
tCL(1)
Clock High Pulse Width
5
—
6
—
ns
Clock Low Pulse Width
5
—
6
—
ns
Output Parameters
tCD
Clock High to Valid Data
—
6
—
7
ns
tCDC
Clock High to Data Change
2
—
2
—
ns
tCLZ(2)
Clock High to Output Active
0
—
0
—
ns
tCHZ(2)
Clock High to Data High-Z
2
15
2
15
ns
tOE
Output Enable Access Time
—
6
—
7
ns
tOLZ(2)
Output Enable Low to Data Active
0
—
0
tOHZ(2)
Output Enable High to Data High-Z
—
6
—
7
ns
ns
ns
Set Up and Hold Times
tSxx
Input Setup Time
2.0
—
2.5
—
tHxx
Input Hold Time
1.5
—
1.5
—
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
ns
3555 tbl 06
TIMING WAVEFORMS
tCYC
CLK
tCH
tSxx
tCL
tHxx
All Inputs
(except OE#)
tCD
tCLZ
tCDC
tCHZ
I/O[31:0]
output
tOLZ
tOE
tOHZ
OE#
13.1
4
IDT71F432 32Kx32 MCache SYNCHRONOUS PIPELINED CACHE RAM
COMMERCIAL TEMPERATURE RANGE
CS0
BW4#
BW3#
BW2#
BW1#
CS1#
VDD
VSS
CLK
GW#
BWE#
OE#
ADSC#
ADSP#
ADV#
A8
A9
A6
A7
CE#
PIN CONFIGURATION
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
I/O16
I/O17
VDD
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDD
I/O22
I/O23
NC
VDD
VDD5
VSS
I/O24
I/O25
VDD
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDD
I/O30
I/O31
NC
1
80
2
79
3
78
4
77
5
76
75
6
7
74
73
8
9
72
71
10
11
70
12
69
13
68
14
67
66
15
PK100-1
16
65
64
17
18
63
14mm x 20mm x 1.4mm body
1.6mm max total height
0.65mm pin pitch
19
20
21
62
61
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
51
30
NC
I/O15
I/O14
VDD
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDD
I/O9
I/O8
VSS
VDD5
VDD
NC
I/O7
I/O6
VDD
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDD
I/O1
I/O0
NC
NC
A5
A4
A3
A2
A1
A0
RESET#
W/R#
VSS
VDD
F1
F0
A10
A11
A12
A13
A14
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TOP VIEW
TQFP
ORDERING INFORMATION
IDT 71F432
Device
Type
X
XX
PF
Power
Speed
Package
75
66
S
L
13.1
Speed in MHz
Standard Power (66 and 75 MHz)
Low Power
(66 MHz only)
5
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