ON MC14060BCPG 14-bit binary counter and oscillator Datasheet

MC14060B
14−Bit Binary Counter and
Oscillator
The MC14060B is a 14−stage binary ripple counter with an on−chip
oscillator buffer. The oscillator configuration allows design of either
RC or crystal oscillator circuits. Also included on the chip is a reset
function which places all outputs into the zero state and disables the
oscillator. A negative transition on Clock will advance the counter to
the next state. Schmitt trigger action on the input line permits very
slow input rise and fall times. Applications include time delay circuits,
counter controls, and frequency dividing circuits.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high−impedance circuit. For proper
operation, Vin and Vout should be constrained to the range VSS (Vin
or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING
DIAGRAMS
16
PDIP−16
P SUFFIX
CASE 648
1
16
SOIC−16
D SUFFIX
CASE 751B
Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
Buffered Outputs Available from Stages 4 Through 10 and
12 Through 14
Common Reset Line
Pin−for−Pin Replacement for CD4060B
Pb−Free Packages are Available*
Parameter
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD
+0.5
V
VDD
DC Supply Voltage Range
Vin,
Vout
Input or Output Voltage Range
(DC or Transient)
Iin,
Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature (8 Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating: Plastic “P and D/DW” Packages: –7.0 mW/°C from
65°C To 125°C.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
 Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 6
1
14060B
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
14
060B
ALYW
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
MC14060BCP
AWLYYWW
SOEIAJ−16
F SUFFIX
CASE 966
MC14060B
ALYW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Publication Order Number:
MC14060B/D
MC14060B
Q12
1
16
VDD
Q13
2
15
Q10
Q14
3
14
Q8
Q6
4
13
Q9
Q5
5
12
RESET
Q7
6
11
CLOCK
Q4
7
10
OUT 1
VSS
8
9
OUT 2
Table 1. Truth Table
Clock
Reset
H
L
L
H
Output State
No Change
Advance to Next State
All Outputs are Low
X = Don’t Care
Figure 1. Pin Assignment
9
10
11
OUT 2
Q4
OUT 1
CLOCK
C
C
12
R
Q
C
Q
C
R
Q5
7
Q
C
Q
C
R
Q12
1
5
Q
C
Q
C
R
Q13
2
Q
C
Q
C
R
Q14
3
Q
C
Q
C
Q
R
Q
RESET
Q6 = PIN 4
Q7 = PIN 6
Figure 2. Logic Diagram
http://onsemi.com
2
Q8 = PIN 14
Q9 = PIN 13
Q10 = PIN 15
VDD = PIN 16
VSS = PIN 8
MC14060B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55°C
Vdc
Min
Max
Min
25°C
Typ
(Note 2)
VDD
Symbol
Characteristic
125°C
Max
Min
Max
Unit
VOL
Output Voltage
Vin = VDD or 0
“0” Level
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
V
VOH
Vin = 0 or VDD
“1” Level
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
V
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11.0
−
−
−
3.5
7.0
11.0
2.75
5.50
8.25
−
−
−
3.5
7.0
11.0
−
−
−
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
5.0
5.0
10
15
–3.0
–0.64
–1.6
– 4.2
−
−
−
−
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mA
VIL
VIH
VIL
VIH
IOH
IOL
Input Voltage
(VO = 4.5 or 0.5 V)
(VO = 9.0 or 1.0 V)
(VO = 13.5 or 1.5 V)
“0” Level
(VO = 0.5 or 4.5 V)
(VO = 1.0 or 9.0 V)
(VO = 1.5 or 13.5 V)
“1” Level
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
“0” Level
(For Input 11
and Output 10)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
“1” Level
Output Drive Current
(VOH = 2.5 V)
(Except Source
Pins 9 and 10)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Sink
V
V
Vdc
Vdc
mA
Iin
Input Current
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
A
Cin
Input Capacitance (Vin = 0)
−
−
−
−
5.0
7.5
−
−
pF
IDD
Quiescent Current
(Per Package)
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
A
IT
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs,
all buffers switching)
5.0
10
15
IT = (0.25 A/kHz) f + IDD
IT = (0.54 A/kHz) f + IDD
IT = (0.85 A/kHz) f + IDD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002.
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3
A
MC14060B
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SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25°C)
Symbol
Characteristic
VDD
Vdc
Min
Typ
(Note 5)
Max
Unit
tTLH
Output Rise Time (Counter Outputs)
5.0
10
15
−
−
−
40
25
20
200
100
80
ns
tTHL
Output Fall Time (Counter Outputs)
5.0
10
15
−
−
−
50
30
20
200
100
80
ns
tPLH
tPHL
Propagation Delay Time
Clock to Q4
5.0
10
15
−
−
−
415
175
125
740
300
200
ns
5.0
10
15
−
−
−
1.5
0.7
0.4
2.7
1.3
1.0
s
Clock to Q14
twH
Clock Pulse Width
5.0
10
15
100
40
30
65
30
20
−
−
−
ns
f
Clock Pulse Frequency
5.0
10
15
−
−
−
5
14
17
3.5
8
12
MHz
tTLH
tTHL
Clock Rise and Fall Time
5.0
10
15
tw
Reset Pulse Width
tPHL
Propagation Delay Time
Reset to On
ns
No Limit
5.0
10
15
120
60
40
40
15
10
−
−
5.0
10
15
−
−
−
170
80
60
350
160
100
ns
−
ns
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
VDD
500 F
PULSE
GENERATOR
CLOCK
NC
NC
Q4
OUT1 Q5
OUT2 Qn
R
VSS
20 ns
CLOCK
PULSE
GENERATOR
0.01 F
ID
90%
50%
10%
50% DUTY CYCLE
CLOCK
NC
NC
Q4
OUT1 Q5
OUT2
Qn
R
VSS
CL
CL
20 ns
CL
20 ns
90%
50%
10%
CLOCK
20 ns
tPLH
VDD
Q
VSS
tTLH
Figure 1. Power Dissipation Test Circuit
and Waveform
CL
CL
tWH
tPHL
90%
50%
10%
tTHL
Figure 2. Switching Time Test Circuit
and Waveforms
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4
CL
MC14060B
11
f 10OUT 1
RESET
if 1 kHz ≤ f ≤ 100 kHz
and 2Rtc < RS < 10Rtc
(f in Hz, R in ohms, C in farads)
9OUT 2
Rtc
The formula may vary for other frequencies. Recommended
maximum value for the resistors in 1 M.
Ctc
RS
1
2.3 RtcCtc
Figure 3. Oscillator Circuit Using RC Configuration
TYPICAL RC OSCILLATOR CHARACTERISTICS
100
VDD = 15 V
4.0
f, OSCILLATOR FREQUENCY (kHz)
FREQUENCY DEVIATION (%)
8.0
0
1.0 V
− 4.0
− 8.0
− 12
5.0 V
RTC = 56 k
C = 1000 pF
− 16
− 55
− 25
RS=0, f=10.15kHz @ VDD=10, TA=25°C
RS=120 k, f=7.8kHz @ VDD=10V, TA=25°C
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
10
5
2
1
0.5
f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)
0.2
0.0001
Figure 4. RC Oscillator Stability
10 k
100 k
RTC, RESISTANCE (OHMS)
0.001
0.01
C, CAPACITANCE (F)
1.0 M
0.1
Figure 5. RC Oscillator Frequency as a
Function of RTC and C
CLOCK
11
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ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Table 2. Typical Data for Crystal Oscillator Circuit
RESET
10OUT 1
9OUT 2
18M
RO
CS
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
20
0.1
1.0 k
125
VDD = 10 V
50
CT
Figure 6. Typical Crystal Oscillator Circuit
Characteristic
500 kHz 32 kHz
Circuit Circuit Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
32
6.2
kHz
k
External Resistor/Capacitor Values
RO
CT
CS
47
82
20
750
82
20
k
pF
pF
+6.0
+2.0
+2.0
+2.0
ppm
ppm
+100
+120
ppm
–160
–560
ppm
Frequency Stability
Frequency Changes as a
Function of VDD (TA = 25°C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
Frequency Change as a Function of
Temperature (VDD = 10 V)
TA Change from − 55°C to
+ 25°C Complete Oscillator (Note 6)
TA Change from + 25°C to
+ 125°C Complete Oscillator
(Note 6)
6. Complete oscillator includes crystal, capacitors, and resistors.
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5
MC14060B
ORDERING INFORMATION
Package
Shipping†
MC14060BCP
PDIP−16
500 Units / Rail
MC14060BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14060BD
SOIC−16
48 Units / Rail
MC14060BDR2
SOIC−16
2500 / Tape & Reel
MC14060BDR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC14060BFEL
SOEIAJ−16
(Pb−Free)
2000 / Tape & Reel
MC14060BDTR2
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MC14060B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
SEATING
PLANE
−T−
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 C
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
−A−
−T−
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0
10 0.020 0.040
M
T B
S
A
S
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
MC14060B
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
DETAIL E
H
D
G
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8
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC14060B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE O
16
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.031
MC14060B
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Phone: 81−3−5773−3850
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10
For additional information, please contact your
local Sales Representative.
MC14060B/D
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