DM74LS395 4-Bit Shift Register with TRI-STATEÉ Outputs General Description Features The LS395 is a 4-bit shift register with TRI-STATE outputs and can operate in either a synchronous parallel load or a serial shift-right mode, as determined by the Select input. An asynchronous active LOW Master Reset (MR) input overrides the synchronous operations and clears the register. An active LOW Output Enable (OE) input controls the TRISTATE output buffers, but does not interfere with the other operations. The fourth stage also has a conventional output for linking purposes in multi-stage serial operations. Y Connection Diagram Logic Symbol Shift right or parallel 4-bit register TRI-STATE outputs Input clamp diodes limit high speed termination effects Fully CMOS and TTL compatible Y Y Y Dual-In-Line Package TL/F/9833 – 2 VCC e Pin 16 GND e Pin 8 TL/F/9833 – 1 Order Number DM74LS395WM or DM74LS395N See NS Package Number M16B or N16E Mode Select Table Inputs Operating Mode MR CP @ tn Outputs S DS Pn O0 L H O1 @ tn a 1 O2 O3 Asynchronous Reset Shift, SET First Stage L H X X K L X H X X L L L O0n O1n 02n Shift, RESET First Stage Parallel Load H H K L K H L X X L O0n O1n 02n Pn P0 P1 P2 P3 tn, tn a 1 e Time before and after CP HIGH-to-LOW transition H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9833 RRD-B30M115/Printed in U. S. A. DM74LS395 4-Bit Shift Register with TRI-STATE Outputs February 1992 Absolute Maximum Ratings (Note) Supply Voltage Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. 7V Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 0§ C to a 70§ C b 65§ C to a 150§ C Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH High Level Input Voltage V VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature 0 ts (H) ts (L) Setup Time HIGH or LOW S, DS or Pn to CP 20 20 ns th (H) th (L) Hold Time HIGH or LOW S, DS or Pn to CP 5 5 ns tw (L) CP Pulse Width LOW 18 ns tw (L) MR Pulse Width LOW 20 ns 2 V 0.8 V b 0.4 mA 8 mA 70 §C Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VOH High Level Output Voltage VCC e Min, II e b18 mA VCC e Min, IOH e Max VIL e Max VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min Min Typ (Note 1) Max Units b 1.5 V 2.7 IOL e 4 mA, VCC e Min VCC e Max, VI e 7V V 0.35 0.5 0.25 0.4 V II Input Current @ Max Input Voltage IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA IIL Low Level Input Current VCC e Max, VI e 0.4V b 0.4 mA IOS Short Circuit Output Current VCC e Max (Note 2) b 100 mA Supply Current with Outputs OFF VCC e Max, OE, DS, S e 4.5V CP e K, Pn e GND 29 mA Supply Current with Outputs ON VCC e Max, DS, S e 4.5V OE, CP, Pn e GND 25 mA IOZH TRI-STATE Output Off Current HIGH VCC e VCCH VOZH e 2.7V 20 mA IOZL TRI-STATE Output Off Current LOW VCC e VCCH VOZL e 0.4V b 20 mA ICC 0.1 b 20 Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. 2 mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C Symbol RL e 2 kX, CL e 15 pF Parameter Min Units Max fmax Maximum Shift Frequency tPLH tPHL Propagation Delay CP to On 30 35 25 MHz ns tPHL Propagation Delay MR to On 35 ns tPZH tPZL Output Enable Time 20 20 ns tPHZ tPLZ Output Disable Time 17 23 ns Functional Description served. When the S input is LOW, a CP HIGH-LOW transition transfers data in O0 to O1, O1 to O2, and O2 to O3. A left-shift is accomplished by connecting the outputs back to the Pn inputs, but offset one place to the left, i.e., O3 to P2, O2 to P1, and O1 to P0, with P3 acting as the linking input from another package. When the OE input is HIGH, the output buffers are disabled and the O0 – O3 outputs are in a high impedance condition. The shifting, parallel loading or resetting operations can still be accomplished, however. The ‘LS395 contains four D-type edge-triggered flip-flops and auxiliary gating to select a D input either from a Parallel (Pn) input or from the preceding stage. When the Select input is HIGH, the Pn inputs are enabled. A LOW signal in the S input enables the serial inputs for shift-right operations, as indicated in the Truth Table. State changes are initiated by HIGH-to-LOW transitions on the Clock Pulse (CP) input. Signals on the Pn, DS and S inputs can change when the Clock is in either state, provided that the recommended setup and hold times are ob- Logic Diagram TL/F/9833 – 3 3 4 Physical Dimensions inches (millimeters) 16-Lead Wide Small Outline Molded Package (M) Order Number DM74LS395WM NS Package Number M16B 5 DM74LS395 4-Bit Shift Register with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS395N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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