ISP1105/1106 Advanced USB transceivers Rev. 10 — 28 September 2009 Product data sheet 1. General description The ISP1105/1106 range of Universal Serial Bus (USB) transceivers are compliant with the Universal Serial Bus Specification Rev. 2.0. They can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates. The ISP1105/1106 range can be used as a USB device transceiver or a USB host transceiver. They allow USB Application Specific ICs (ASICs) and Programmable Logic Devices (PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical layer of the Universal Serial Bus. They have an integrated 5 V-to-3.3 V voltage regulator for direct powering via the USB supply VBUS. ISP1105 allows single-ended and differential input modes selectable by a MODE input and it is available in HVQFN16 and HBCC16 packages. ISP1106 allows only differential input mode and is available in both TSSOP16 and HBCC16 packages. The ISP1105/1106 are ideal for portable electronics devices such as mobile phones, digital still cameras, Personal Digital Assistants (PDA) and Information Appliances (IA). 2. Features Complies with Universal Serial Bus Specification Rev. 2.0 Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates Integrated bypassable 5 V-to-3.3 V voltage regulator for powering via USB VBUS VBUS disconnection indication through VP and VM Used as a USB device transceiver or a USB host transceiver Stable RCV output during SE0 condition Two single-ended receivers with hysteresis Low-power operation Supports an I/O voltage range from 1.65 V to 3.6 V ±12 kV ESD protection at the D+, D−, VCC(5.0) and GND pins Full industrial operating temperature range from −40 °C to +85 °C Available in small HBCC16, HVQFN16 (only ISP1105) and TSSOP16 (only ISP1106) packages The ISP1105 HBCC16 and HVQFN16 are lead-free and halogen-free. The ISP1106 HBCC16 is lead-free. ISP1105/1106 Advanced USB transceivers 3. Applications Portable electronic devices, such as: Mobile phone Digital still camera Personal Digital Assistant (PDA) Information Appliance (IA). 4. Ordering information Table 1. Ordering information Commercial product code Package description Packing Minimum sellable quantity ISP1105BSTM HVQFN16; 16 terminals; body 3 × 3 × 0.85 mm 13 inch tape and reel non-dry pack 6000 pieces ISP1105WTS HBCC16; 16 terminals; body 3 × 3 × 0.65 mm 7 inch tape and reel non-dry pack 1400 pieces ISP1105WTM HBCC16; 16 terminals; body 3 × 3 × 0.65 mm 13 inch tape and reel non-dry pack 6000 pieces ISP1106WTS HBCC16; 16 terminals; body 3 × 3 × 0.65 mm 7 inch tape and reel non-dry pack 1400 pieces 13 inch tape and reel non-dry pack 2500 pieces ISP1106DHTM TSSOP16; 16 leads; body width 4.4 mm 4.1 Ordering options Table 2. Selection guide Product Package ISP1105 HVQFN16 and HBCC16 supports both single-ended and differential input modes; see Table 5 and Table 6. Description ISP1106 TSSOP16 and HBCC16 supports only the differential input mode; see Table 6. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 2 of 25 ISP1105/1106 Advanced USB transceivers 5. Block diagram 3.3 V V CC(I/O) VOLTAGE REGULATOR VCC(5.0) Vreg(3.3) Vpu(3.3) SOFTCON 1.5 kΩ(1) OE SPEED D+ VMO/FSE0(2) D− VPO/VO(2) 33 Ω (1%) 33 Ω (1%) MODE(3) LEVEL SHIFTER SUSPND RCV ISP1105 ISP1106 VP VM mbl301 GND (1) Connect to D− for low-speed operation. (2) Pin function depends on device type. (3) Only for ISP1105. Fig 1. Block diagram (combined ISP1105 and ISP1106). ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 3 of 25 ISP1105/1106 Advanced USB transceivers 6. Pinning information 11 VPO/VO 12 VMO/FSE0 14 13 SOFTCON Vpu(3.3) VCC(5.0) Vreg(3.3) 16 VCC(5.0) SOFTCON 2 15 Vreg(3.3) OE 3 14 VMO RCV 4 13 VPO VP 5 12 D+ VM 6 11 D− Fig 3. Fig 4. SUSPND 5 VM 4 VP 3 RCV 2 OE 1 9 V CC(I/O) Bottom view MBL302 Pin configuration ISP1106DHTM (TSSOP16). Fig 5. 15 14 D− 10 D+ 11 VPO/VO 12 VMO/FSE0 13 Vreg(3.3) MBL303 6 7 8 ISP1106WTS 16 15 14 9 D− 10 D+ 11 VPO 12 VMO 13 Vreg(3.3) MBL304 Pin configuration ISP1106WTS (HBCC16). ISP1105_1106_10 Product data sheet 16 9 Pin configuration ISP1105WTS and ISP1105WTM (HBCC16). 10 SPEED GND 8 (exposed diepad) Bottom view Vpu(3.3) 1 SUSPND 7 1 GND 004aaa314 Pin configuration ISP1105BSTM (HVQFN). ISP1106DHTM OE SPEED SPEED 15 2 VCC(I/O) VCC(I/O) 16 ISP1105WTS ISP1105WTM 3 RCV MODE MODE GND (exposed diepad) Fig 2. 4 VP OE 1 Bottom view VM 8 VCC(5.0) D+ 7 SPEED 10 6 VCC(5.0) D− 5 Vpu(3.3) 2 ISP1105BSTM 9 SUSPND VCC(I/O) RCV 8 Vpu(3.3) 3 7 SOFTCON VP 6 GND 4 5 SOFTCON VM SUSPND 6.1 Pinning © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 4 of 25 ISP1105/1106 Advanced USB transceivers 6.2 Pin description Table 3. Symbol[1] Pin description Pin Type Description ISP1105 ISP1106 BSTM WTS, DHTM WTS WTM OE 1 1 3 1 I output enable input (CMOS level with respect to VCC(I/O), active LOW); enables the transceiver to transmit data on the USB bus RCV 2 2 4 2 O differential data receiver output (CMOS level with respect to VCC(I/O)); driven LOW when input SUSPND is HIGH; the output state of RCV is preserved and stable during an SE0 condition input pad; push pull; CMOS output pad; push pull; 4 mA output drive; CMOS VP 3 3 5 3 O single-ended D+ receiver output (CMOS level with respect to VCC(I/O)); for external detection of single-ended zero (SE0), error conditions, speed of connected device; driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad; push pull; 4 mA output drive; CMOS VM 4 4 6 4 O single-ended D− receiver output (CMOS level with respect to VCC(I/O)); for external detection of single-ended zero (SE0), error conditions, speed of connected device; driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) output pad; push pull; 4 mA output drive; CMOS SUSPND 5 5 7 5 I suspend input (CMOS level with respect to VCC(I/O)); a HIGH level enables low-power state while the USB bus is inactive and drives output RCV to a LOW level input pad; push pull; CMOS 6 6 - - I mode input (CMOS level with respect to VCC(I/O)); a HIGH level enables the differential input mode (VPO, VMO) whereas a LOW level enables a single-ended input mode (VO, FSE0); see Table 5 and Table 6 die pad die pad 8 6 - ground supply[2] VCC(I/O) 7 7 9 7 - supply voltage for digital I/O pins (1.65 V to 3.6 V). When VCC(I/O) is not connected, the (D+, D−) pins are in three-state; this supply pin is totally independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3) voltage SPEED 8 8 10 8 I speed selection input (CMOS level with respect to VCC(I/O)); adjusts the slew rate of differential data outputs D+ and D− according to the transmission speed MODE input pad; push pull; CMOS GND LOW — low-speed (1.5 Mbit/s) HIGH — full-speed (12 Mbit/s) input pad; push pull; CMOS D− 9 9 11 9 AI/O negative USB data bus connection (analog, differential); for low-speed mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor D+ 10 10 12 10 AI/O positive USB data bus connection (analog, differential); for full-speed mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 5 of 25 ISP1105/1106 Advanced USB transceivers Table 3. Symbol[1] Pin description …continued Pin Type Description ISP1105 ISP1106 BSTM WTS, DHTM WTS WTM VPO/VO 11 11 - - VPO - - 13 11 VO - - - - 12 12 - - VMO/FSE0 VMO - - 14 12 FSE0 - - - - 13 13 15 13 Vreg(3.3) I driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see Table 5 and Table 6 input pad; push pull; CMOS I driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see Table 5 and Table 6 input pad; push pull; CMOS - internal regulator option: regulated supply voltage output (3.0 V to 3.6 V) during 5 V operation; a decoupling capacitor of at least 0.1 μF is required regulator bypass option: used as a supply voltage input for 3.3 V ± 10 % operation VCC(5.0) 14 14 16 14 - internal regulator option: supply voltage input (4.0 V to 5.5 V); can be connected directly to USB supply VBUS regulator bypass option: connect to Vreg(3.3) Vpu(3.3) 15 15 1 15 - pull-up supply voltage (3.3 V ± 10 %); connect an external 1.5 kΩ resistor on D+ (full-speed) or D− (low-speed); pin function is controlled by input SOFTCON SOFTCON = LOW — Vpu(3.3) floating (high impedance); ensures zero pull-up current SOFTCON = HIGH — Vpu(3.3) = 3.3 V; internally connected to Vreg(3.3) SOFTCON 16 16 2 16 I software controlled USB connection input; a HIGH level applies 3.3 V to pin Vpu(3.3), which is connected to an external 1.5 kΩ pull-up resistor; this allows USB connect/disconnect signalling to be controlled by software input pad; push pull; CMOS [1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals. [2] ISP1105: ground terminal is connected to the exposed die pad (heat sink). ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 6 of 25 ISP1105/1106 Advanced USB transceivers 7. Functional description 7.1 Function selection Table 4. Function table SUSPND OE (D+, D−) RCV VP/VM Function L L driving and receiving active active normal driving (differential receiver active) L H receiving[1] active active receiving active driving during ‘suspend’[3] (differential receiver inactive) active low-power state H L driving inactive[2] H H high-Z[1] inactive[2] [1] Signal levels on (D+, D−) are determined by other USB devices and external pull-up/down resistors. [2] In ‘suspend’ mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always LOW. Out-of-suspend (‘K’) signalling is detected via the single-ended receivers VP and VM. [3] During suspend, the slew-rate control circuit of low-speed operation is disabled. The (D+, D−) lines are still driven to their intended states, without slew-rate control. This is permitted because driving during suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from idle to ‘K’ state) for a period of 1 to 15 ms. 7.2 Operating functions Table 5. Driving function (pin OE = L) using single-ended input data interface for ISP1105 (pin MODE = L) FSE0 VO Data L L differential logic 0 L H differential logic 1 H L SE0 H H SE0 Table 6. Driving function (pin OE = L) using differential input data interface for ISP1105 (pin MODE = H) and ISP1106 VMO VPO Data L L SE0 L H differential logic 1 H L differential logic 0 H H illegal state Table 7. Receiving function (pin OE = H) (D+, D−) RCV VP[1] VM[1] Differential logic 0 L L H Differential logic 1 H H L SE0 RCV*[2] L L [1] VP = VM = H indicates the sharing mode (VCC(5.0) and Vreg(3.3) are disconnected). [2] RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during the SE0 period. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 7 of 25 ISP1105/1106 Advanced USB transceivers 7.3 Power supply configurations The ISP1105/1106 can be used with different power supply configurations, which can be changed dynamically. An overview is given in Table 9. Normal mode — Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. For 5 V operation, VCC(5.0) is connected to a 5 V source (4.0 V to 5.5 V). The internal voltage regulator then produces 3.3 V for the USB connections. For 3.3 V operation, both VCC(5.0) and Vreg(3.3) are connected to a 3.3 V source (3.0 V to 3.6 V). VCC(I/O) is independently connected to a voltage source (1.65 V to 3.6 V), depending on the supply voltage of the external circuit. Disable mode — VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected. In this mode, the internal circuits of the ISP1105/1106 ensure that the (D+, D−) pins are in three-state and the power consumption drops to the low-power (suspended) state level. Some hysteresis is built into the detection of VCC(I/O) lost. Sharing mode — VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In this mode, the (D+, D−) pins are made three-state and the ISP1105/1106 allows external signals of up to 3.6 V to share the (D+, D−) lines. The internal circuits of the ISP1105/1106 ensure that virtually no current (maximum 10 μA) is drawn via the (D+, D−) lines. The power consumption through pin VCC(I/O) drops to the low-power (suspended) state level. Both the VP and VM pins are driven HIGH to indicate this mode. Pin RCV is made LOW. Some hysteresis is built into the detection of Vreg(3.3) lost. Table 8. Pin states in disable or sharing mode Pins Disable mode state Sharing mode state VCC(5.0) / Vreg(3.3) 5 V input / 3.3 V output; 3.3 V input / 3.3 V input not present VCC(I/O) not present 1.65 V to 3.6 V input Vpu(3.3) high impedance (off) high impedance (off) (D+, D−) high impedance high impedance (VP, VM) invalid[1] H RCV invalid[1] L Inputs (VO/VPO, FSE0/VMO, SPEED, high impedance MODE[2], SUSPND, OE, SOFTCON) [1] High impedance or driven LOW. [2] ISP1105 only. Table 9. high impedance Power supply configuration overview VCC(5.0) or Vreg(3.3) VCC(I/O) Configuration Special characteristics Connected connected normal mode - Connected not connected disable mode (D+, D−) and Vpu(3.3) high impedance; VP, VM, RCV: invalid[1] Not connected connected sharing mode (D+, D−) and Vpu(3.3) high impedance; VP, VM driven HIGH; RCV driven LOW [1] High impedance or driven LOW. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 8 of 25 ISP1105/1106 Advanced USB transceivers 7.4 Power supply input options The ISP1105/1106 range has two power supply input options. Internal regulator — VCC(5.0) is connected to 4.0 V to 5.5 V. The internal regulator is used to supply the internal circuitry with 3.3 V (nominal). The Vreg(3.3) pin becomes a 3.3 V output reference. Regulator bypass — VCC(5.0) and Vreg(3.3) are connected to the same supply. The internal regulator is bypassed and the internal circuitry is supplied directly from the Vreg(3.3) power supply. The voltage range is 3.0 V to 3.6 V to comply with the USB specification. The supply voltage range for each input option is specified in Table 10. Table 10. Power supply input options Input option VCC(5.0) Vreg(3.3) Internal regulator supply input for internal voltage reference output supply input for digital regulator (4.0 V to 5.5 V) (3.3 V, 300 μA) I/O pins (1.65 V to 3.6 V) Regulator bypass connected to Vreg(3.3) with maximum voltage drop of 0.3 V (2.7 V to 3.6 V) supply input (3.0 V to 3.6 V) ISP1105_1106_10 Product data sheet VCC(I/O) supply input for digital I/O pins (1.65 V to 3.6 V) © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 9 of 25 ISP1105/1106 Advanced USB transceivers 8. Electrostatic discharge (ESD) 8.1 ESD protection The pins that are connected to the USB connector (D+, D−, VCC(5.0) and GND) have a minimum of ±12 kV ESD protection. The ±12 kV measurement is limited by the test equipment. Capacitors of 4.7 μF connected from Vreg(3.3) to GND and VCC(5.0) to GND are required to achieve this ±12 kV ESD protection (see Figure 6). RC 1 MΩ RD 1500 Ω charge current limit resistor discharge resistance DEVICE UNDER TEST VCC(5V0) A VREG3V3 HIGH VOLTAGE DC SOURCE CS 100 pF storage capacitor B 4.7 μF 4.7 μF GND 004aaa145 Fig 6. Human Body ESD test model. 8.2 ESD test conditions A detailed report on test set-up and results is available on request. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 10 of 25 ISP1105/1106 Advanced USB transceivers 9. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC(5.0) Min Max Unit supply voltage −0.5 +6.0 V VCC(I/O) I/O supply voltage −0.5 +4.6 V Vreg(3.3) regulated supply voltage −0.5 +4.6 V VI DC input voltage −0.5 VCC(I/O) + 0.5 V Ilu latch-up current VI = −1.8 V to 5.4 V - 100 mA electrostatic discharge voltage ILI < 1 μA on pins D+, D−, VCC(5.0) and GND −12000 +12000 V on other pins −2000 +2000 V −40 +125 °C Vesd Tstg Conditions [1][2] storage temperature [1] Testing equipment limits measurement to only ±12 kV. Capacitors needed on VCC(5.0) and Vreg(3.3); see Section 8. [2] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model). 10. Recommended operating conditions Table 12. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC(5.0) supply voltage (internal regulator option) 5 V operation 4.0 5.0 5.5 V Vreg(3.3) supply voltage (regulator bypass option) 3.3 V operation 3.0 3.3 3.6 V VCC(I/O) I/O supply voltage 1.65 - 3.6 V VI input voltage 0 - VCC(I/O) V VI(AI/O) input voltage on analog I/O pins (D+/D−) 0 - 3.6 V Tamb operating ambient temperature −40 - +85 °C ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 11 of 25 ISP1105/1106 Advanced USB transceivers 11. Static characteristics Table 13. Static characteristics: supply pins VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level combinations; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions [1][2] Min Typ Max Unit 3.0 3.3 3.6 V Vreg(3.3) regulated supply voltage output internal regulator option; Iload ≤ 300 μA ICC operating supply current full-speed transmitting and receiving at 12 Mbit/s; CL = 50 pF on D+/D− [3] - 4 8 mA ICC(I/O) operating I/O supply current full-speed transmitting and receiving at 12 Mbit/s [3] - 1 2 mA ICC(idle) supply current during full-speed idle and SE0 full-speed idle: VD+ > 2.7 V, VD− < 0.3 V; SE0: VD+ < 0.3 V, VD− < 0.3 V [4] - - 500 μA ICC(I/O)(static) static I/O supply current full-speed idle, SE0 or suspend - - 20 μA - - 20 μA ICC(susp) ICC(dis) suspend supply current SUSPND = HIGH - - 20 μA VCC(5.0) or Vreg(3.3) not connected - - 20 μA - - 10 μA - - 0.8 V disable mode supply current VCC(I/O) not connected ICC(I/O)(sharing) sharing mode I/O supply current [4] IDx(sharing) sharing mode load current on pins D+ and D− VCC(5.0) or Vreg(3.3) not connected; SOFTCON = LOW; VDx = 3.6 V Vreg(3.3)th regulated supply voltage detection threshold 1.65 V ≤ VCC(I/O) ≤ Vreg(3.3); 2.7 V ≤ Vreg(3.3) ≤ 3.6 V [4] supply lost supply present Vreg(3.3)hys regulated supply voltage detection hysteresis VCC(I/O) = 1.8 V VCC(I/O)th I/O supply voltage detection threshold Vreg(3.3) = 2.7 V to 3.6 V VCC(I/O)hys I/O supply voltage detection hysteresis [5] 2.4 - - V - 0.45 - V supply lost - - 0.5 V supply present 1.4 - - V - 0.45 - V Vreg(3.3) = 3.3 V [1] Iload includes the pull-up resistor current via pin Vpu(3.3). [2] In ‘suspend’ mode, the minimum voltage is 2.7 V. [3] Maximum value is characterized only, not tested in production. [4] Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 μA typ.). [5] When VCC(I/O) < 2.7 V, the minimum value for Vth(reg3.3)(present) is 2.0 V. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 12 of 25 ISP1105/1106 Advanced USB transceivers Table 14. Static characteristics: digital pins VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCC(I/O) = 1.65 to 3.6 V Input levels VIL LOW-level input voltage - - 0.3VCC(I/O) V VIH HIGH-level input voltage 0.6VCC(I/O) - - V IOL = 100 μA - - 0.15 V IOL = 2 mA - - 0.4 V IOH = 100 μA VCC(I/O) − 0.15 - - V IOH = 2 mA VCC(I/O) − 0.4 - - V −1 - +1 μA Output levels VOL VOH LOW-level output voltage HIGH-level output voltage Leakage current ILI input leakage current Example 1: VCC(I/O) = 1.8 V ± 0.15 V Input levels VIL LOW-level input voltage - - 0.5 V VIH HIGH-level input voltage 1.2 - - V Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 100 μA - - 0.15 V IOL = 2 mA - - 0.4 V IOH = 100 μA 1.5 - - V IOH = 2 mA 1.25 - - V Example 2: VCC(I/O) = 2.5 V ± 0.2 V Input levels VIL LOW-level input voltage - - 0.7 V VIH HIGH-level input voltage 1.7 - - V IOL = 100 μA - - 0.15 V IOL = 2 mA - - 0.4 V IOH = 100 μA 2.15 - - V IOH = 2 mA 1.9 - - V Output levels VOL VOH LOW-level output voltage HIGH-level output voltage Example 3: VCC(I/O) = 3.3 V ± 0.3 V Input levels VIL LOW-level input voltage - - 0.9 V VIH HIGH-level input voltage 2.15 - - V IOL = 100 μA - - 0.15 V IOL = 2 mA - - 0.4 V Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOH = 100 μA 2.85 - - V IOH = 2 mA 2.6 - - V pin to GND - - 10 pF Capacitance CIN input capacitance ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 13 of 25 ISP1105/1106 Advanced USB transceivers Table 15. Static characteristics: analog I/O pins (D+, D−) VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VGND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Input levels Differential receiver VDI differential input sensitivity |VI(D+) − VI(D−)| 0.2 - - V VCM differential common mode voltage includes VDI range 0.8 - 2.5 V Single-ended receiver VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Vhys hysteresis voltage 0.4 - 0.7 V - - 0.3 V 2.8 - 3.6 V −1 - +1 μA - - 20 pF 34 39 44 Ω Output levels LOW-level output voltage VOL VOH HIGH-level output voltage RL = 1.5 kΩ to +3.6 V RL = 15 kΩ to GND [1] Leakage current OFF-state leakage current ILZ Capacitance transceiver capacitance pin to GND ZDRV driver output impedance steady-state drive ZINP input impedance 10 - - MΩ RSW internal switch resistance at pin Vpu(3.3) - - 10 Ω 3.0 - 3.6 V CIN Resistance [2] Termination VTERM [3][4] termination voltage for upstream port pull-up (RPU) [1] VOH(min) = Vreg(3.3) − 0.2 V. [2] Includes external resistors of 33 Ω ± 1 % on both D+ and D−. [3] This voltage is available at pins Vreg(3.3) and Vpu(3.3). [4] In ‘suspend’ mode the minimum voltage is 2.7 V. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 14 of 25 ISP1105/1106 Advanced USB transceivers 12. Dynamic characteristics Table 16. Dynamic characteristics: analog I/O pins (D+, D−) VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level combinations; Tamb = −40 °C to +85 °C; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Driver characteristics Full-speed mode tFR rise time CL = 50 pF to 125 pF; 10 % to 90 % of |VOH − VOL|; see Figure 7 4 - 20 ns tFF fall time CL = 50 pF to 125 pF; 90 % to 10 % of |VOH − VOL|; see Figure 7 4 - 20 ns FRFM differential rise/fall time matching (tFR/tFF) excluding the first transition from idle state 90 - 111.1 % VCRS output signal crossover voltage excluding the first transition from idle state; see Figure 10 1.3 - 2.0 V [2] Low-speed mode tLR rise time CL = 50 pF to 600 pF; 10 % to 90 % of |VOH − VOL|; see Figure 7 75 - 300 ns tLF fall time CL = 50 pF to 600 pF; 90 % to 10 % of |VOH − VOL|; see Figure 7 75 - 300 ns LRFM differential rise/fall time matching (tLR/tLF) excluding the first transition from idle state 80 - 125 % VCRS output signal crossover voltage excluding the first transition from idle state; see Figure 10 1.3 - 2.0 V [2] Driver timing Full-speed mode tPLH(drv) driver propagation delay LOW-to-HIGH; see Figure 10 (VO/VPO, FSE0/VMO to D+,D−) - - 18 ns tPHL(drv) driver propagation delay HIGH-to-LOW; see Figure 10 (VO/VPO, FSE0/VMO to D+,D−) - - 18 ns tPHZ driver disable delay (OE to D+,D−) HIGH-to-OFF; see Figure 8 - - 15 ns tPLZ driver disable delay (OE to D+,D−) LOW-to-OFF; see Figure 8 - - 15 ns tPZH driver enable delay (OE to D+,D−) OFF-to-HIGH; see Figure 8 - - 15 ns tPZL driver enable delay (OE to D+,D−) OFF-to-LOW; see Figure 8 - - 15 ns Low-speed mode Not specified: low-speed delay timings are dominated by the slow rise/fall times tLR and tLF. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 15 of 25 ISP1105/1106 Advanced USB transceivers Table 16. Dynamic characteristics: analog I/O pins (D+, D−) …continued VCC = 4.0 V to 5.5 V or Vreg(3.3) = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level combinations; Tamb = −40 °C to +85 °C; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Receiver timings (full-speed and low-speed mode) Differential receiver tPLH(rcv) propagation delay (D+,D− to RCV) LOW-to-HIGH; see Figure 9 - - 15 ns tPHL(rcv) propagation delay (D+,D− to RCV) HIGH-to-LOW; see Figure 9 - - 15 ns Single-ended receiver tPLH(se) propagation delay (D+,D− to VP, VM) LOW-to-HIGH; see Figure 9 - - 18 ns tPHL(se) propagation delay (D+,D− to VP, VM) HIGH-to-LOW; see Figure 9 - - 18 ns [1] Test circuit: see Figure 13. [2] Characterized only, not tested. Limits guaranteed by design. 1.8 V tFR, tLR VOH logic 0.9 V input tFF, tLF 90 % 0V VOL 004aaa572 Fig 7. Rise and fall times. VCRS VOL + 0.3 V VOL 004aaa574 Fig 8. 2.0 V Timing of OE to D+, D−. 1.8 V differential data lines VCRS VCRS logic input 0.9 V tPHL(rcv) tPHL(se) 0V 0.8 V tPLH(rcv) tPLH(se) 0.9 V tPLH(drv) VOH tPHL(drv) VOH logic output 0.9 V VOL Fig 9. VOH − 0.3 V differential data lines 10 % tPHZ tPLZ tPZH tPZL 90 % VOH 10 % 0.9 V 004aaa575 Timing of D+, D− to RCV, VP, VM. differential data lines 0.9 V VOL VCRS 004aaa573 Fig 10. Timing of VO/VPO, FSE0/VMO to D+, D−. ISP1105_1106_10 Product data sheet VCRS © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 16 of 25 ISP1105/1106 Advanced USB transceivers 13. Test information test point 33 Ω 500 Ω D.U.T. 50 pF V MBL142 V = 0 V for tPZH, tPHZ V = Vreg(/3.3) for tPZL, tPLZ Fig 11. Load for enable and disable times. test point D.U.T. 25 pF MGS968 Fig 12. Load for VM, VP and RCV. Vpu(3.3) 1.5 kΩ (1) D.U.T. test point D+/D− 33 Ω CL 15 kΩ MGS967 Load capacitance: (1) CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing) (2) CL = 50 pF or 600 pF (low-speed mode, minimum or maximum timing) (1) Full-speed mode: connected to D+; low-speed mode: connected to D−. Fig 13. Load for D+, D−. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 17 of 25 ISP1105/1106 Advanced USB transceivers 14. Package outline HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm b D B SOT639-2 v M C A B w M C A f terminal 1 index area v M C A B w M C b1 E b3 b2 v M C A B w M C v M C A B w M C detail X e1 Dh C e y y1 C 5 9 e e4 Eh e2 1/2 e4 1 13 16 A1 X 1/2 e3 A2 e3 A 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b b1 b2 b3 D Dh E Eh e e1 e2 e3 e4 f v w y y1 mm 0.8 0.10 0.05 0.7 0.6 0.33 0.27 0.33 0.27 0.38 0.32 0.38 0.32 3.1 2.9 1.45 1.35 3.1 2.9 1.45 1.35 0.5 2.5 2.5 2.45 2.45 0.23 0.17 0.08 0.1 0.05 0.2 OUTLINE VERSION REFERENCES IEC SOT639-2 JEDEC JEITA MO-217 EUROPEAN PROJECTION ISSUE DATE 01-11-13 03-03-12 Fig 14. HBCC16 package outline. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 18 of 25 ISP1105/1106 Advanced USB transceivers HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm A B D SOT758-1 terminal 1 index area A E A1 c detail X e1 C 1/2 e e 5 y y1 C v M C A B w M C b 8 L 4 9 e e2 Eh 1/2 e 12 1 16 terminal 1 index area 13 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.75 1.45 3.1 2.9 1.75 1.45 0.5 1.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT758-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21 Fig 15. HVQFN16 package outline. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 19 of 25 ISP1105/1106 Advanced USB transceivers TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC SOT403-1 JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. TSSOP16 package outline. ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 20 of 25 ISP1105/1106 Advanced USB transceivers 15. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes ISP1105_1106_10 20090928 - ISP1105_1106_9 Modifications: • • • • • Product data sheet Rebranded to the ST-Ericsson template. Section 2 “Features”: updated. Section 4 “Ordering information”: updated. Removed packing information. Removed soldering information. ISP1105_1106_9 20090119 Product data sheet - ISP1105_1106-08 ISP1105_1106-08 (9397 750 09529) 20040219 Product data - ISP1105_1106_1107-07 ISP1105_1106_1107-07 20020329 (9397 750 08872) Product data - ISP1105_1106_1107-06 ISP1105_1106_1107-06 20011130 (9397 750 08681) Product data - ISP1105_1106_1107-05 ISP1105_1106_1107-05 20010903 (9397 750 08643) Product data - ISP1105_1106_1107-04 ISP1105_1106_1107-04 20010802 (9397 750 08515) Preliminary data - ISP1105_1106_1107-03 ISP1105_1106_1107-03 20010704 (9397 750 07879) Preliminary data - ISP1107-02 ISP1107-02 (9397 750 06899) 20010205 Objective specification; ISP1107 stand-alone data sheet only - ISP1107-01 ISP1107-01 (9397 750 08643) 20000223 Objective specification; ISP1107 stand-alone data sheet only -- - ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 21 of 25 ISP1105/1106 Advanced USB transceivers 16. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Selection guide . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . .7 Driving function (pin OE = L) using single-ended input data interface for ISP1105 (pin MODE = L) . . . . . . . . . . . . . . . . . . . . . . . . .7 Driving function (pin OE = L) using differential input data interface for ISP1105 (pin MODE = H) and ISP1106 . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Receiving function (pin OE = H) . . . . . . . . . . . .7 Pin states in disable or sharing mode . . . . . . . .8 Power supply configuration overview . . . . . . . .8 Power supply input options . . . . . . . . . . . . . . . .9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommended operating conditions . . . . . . . . 11 Static characteristics: supply pins . . . . . . . . . .12 Static characteristics: digital pins . . . . . . . . . . .13 Static characteristics: analog I/O pins (D+, D−) 14 Dynamic characteristics: analog I/O pins (D+, D−) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Revision history . . . . . . . . . . . . . . . . . . . . . . . .21 ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 22 of 25 ISP1105/1106 Advanced USB transceivers 17. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Block diagram (combined ISP1105 and ISP1106). 3 Pin configuration ISP1105BSTM (HVQFN).. . . . . .4 Pin configuration ISP1105WTS and ISP1105WTM (HBCC16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration ISP1106DHTM (TSSOP16).. . . .4 Pin configuration ISP1106WTS (HBCC16). . . . . . .4 Human Body ESD test model. . . . . . . . . . . . . . . .10 Rise and fall times. . . . . . . . . . . . . . . . . . . . . . . .16 Timing of OE to D+, D-. . . . . . . . . . . . . . . . . . . . .16 Timing of D+, D- to RCV, VP, VM. . . . . . . . . . . . .16 Timing of VO/VPO, FSE0/VMO to D+, D-.. . . . . .16 Load for enable and disable times. . . . . . . . . . . .17 Load for VM, VP and RCV. . . . . . . . . . . . . . . . . .17 Load for D+, D-. . . . . . . . . . . . . . . . . . . . . . . . . . .17 HBCC16 package outline. . . . . . . . . . . . . . . . . . .18 HVQFN16 package outline. . . . . . . . . . . . . . . . . .19 TSSOP16 package outline. . . . . . . . . . . . . . . . . .20 ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 23 of 25 ISP1105/1106 Advanced USB transceivers 18. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 8 8.1 8.2 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Function selection. . . . . . . . . . . . . . . . . . . . . . . 7 Operating functions . . . . . . . . . . . . . . . . . . . . . 7 Power supply configurations. . . . . . . . . . . . . . . 8 Power supply input options. . . . . . . . . . . . . . . . 9 Electrostatic discharge (ESD). . . . . . . . . . . . . 10 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . 10 ESD test conditions . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommended operating conditions. . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 24 of 25 ISP1105/1106 Advanced USB transceivers Please Read Carefully: The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties of merchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third party intellectual property rights, and in no event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or consequential damages and or loss whatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or the information in it. ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2009 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com ISP1105_1106_10 Product data sheet © ST-ERICSSON 2009. All rights reserved. Rev. 10 — 28 September 2009 25 of 25