Freescale MC33899 Programmable h-bridge power ic Datasheet

Freescale Semiconductor
Advance Information
Document Number: MC33899
Rev. 2.0, 6/2007
Programmable H-Bridge
Power IC
33899
The 33899 is designed to drive a DC motor in both forward and
reverse shaft rotation under pulse-width modulation (PWM) control of
speed and torque. A current mirror output provides an analog
feedback signal proportional to the load current. A serial peripheral
interface (SPI) is used to select slew rate control, current
compensation limits and to read diagnostic status (faults) of the HBridge drive circuits. SPI diagnostic reporting includes open circuit,
short circuit to VIGNP, short circuit to ground, die temperature range,
and undervoltage on VIGNP.
PROGRAMMABLE H-BRIDGE POWER IC
Features
• Drives Inductive Loads in a Full H-Bridge Configuration
VW SUFFIX (Pb-FREE)
• Current Mirror Output Signal (Gain Selectable via External
98ASH70693A
Resistor)
30-PIN HSOP
• Short Circuit Current Limiting
• Thermal Shutdown (Outputs Latched Off Until Reset via SPI)
ORDERING INFORMATION
• Internal Charge Pump Circuit for the Internal High-Side MOSFETs
Temperature
• SPI-Selectable Slew Rate Control and Current Limit Control
Device
Package
Range (TA)
• Overtemperature Shutdown
• Outputs Can Be Disabled to High-Impedance State
MC33899VW/R2
-40°C to 125°C
30 HSOP
• PWM-able up to 11 kHz @ 3.0 A
• Synchronous Rectification Control of the High-Side MOSFETs
• Low RDS(ON) Outputs at High Junction Temperature (< 165 mΩ @ TA = 125°C, VIGNP = 6.0 V)
• Outputs Survive Shorts to -1.0 V
• Pb-Free Packaging Designated by Suffix Code VW
VDDL
+5.0 V
33899
VIGNP
VIGNP
VCC
VDDQ
CSNS
REDIS
CRES
VCCL
FWD
S1
REV
PWM
EN1
MCU
S0
EN2
CS
RS
SCLK
D1
D0
LSCMP
GND
Figure 1. 33899 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGNP
CRES
Charge
Pump
To Gate
Drives
M3
M1
VCC
VCCL
S1
+3.3 V
Internal
Regulator
Current
Sense,
Limitation,
and Mirror
CSNS
S0
M4
M2
Gate
Drives
LSCMP
FWD
REV
PWM
EN1
EN2
VDDQ
SCLK
CS
DI
DO
Direction
and PWM
Control
Command, Fault, and
Temperature Register
PWM
Override
Baseline
Slew Rate
Set
REDIS
RS
Temperature
Sense and
Shutdown
GND
Figure 2. 33899 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Tab
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDQ
DO
DI
SCLK
CS
CRES
REDIS
VIGNP
VIGNP
S0
S0
GND
NC
LSCMP
EN2
CSNS
VCC
VCCL
REV
FWD
PWM
RS
VIGNP
VIGNP
S1
S1
GND
NC
NC
EN1
Tab
Figure 3. 33899 Pin Connections
Table 1. 33899 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 12.
Pin Number
Pin Name
Formal Name
Definition
1
VDDQ
Logic Level Output Bias
2
DO
SPI Data Out
3
DI
SPI Data In
4
SCLK
SPI Serial Clock Input
5
CS
Chip Select
(Active Low)
6
CRES
Charge Pump
7
REDIS
Automatic Output ReEnable Disable
8, 9, 22, 23
VIGNP
Protected Ignition
Voltage
10, 11
S0
Bridge Output 0
to Load
12, 19
GND
Ground
13, 17, 18
NC
No Connect
14
LSCMP
Low-Side Comparator
15
16
EN2
EN1
Master Enable 2
Master Enable 1
These input pins determine the mode of the IC; namely, sleep, standby, and run.
20, 21
S1
Bridge Output 1
to Load
These output pins drive the bi-directional motor and must be connected together
on the PC board.
Sets VOH level of DO output and LSCMP.
SPI control data output pin from the IC to the MCU.
SPI control data input pin from the MCU to the IC.
The SCLK input is the clock signal input for synchronization of serial data transfer.
This pin is an input connected to a chip select output of an MCU.
This pin connects an external capacitor, which is the storage reservoir for the
internal charge pump.
This input pin is a connection to a capacitor that determines the default time the
output will be turned off when the low-side current comparator is tripped, if PWM
has not commanded it. The typical value with a 0.1 µF is 100 µs. If shorted, the
feature is disabled.
This input pin is the primary H-Bridge power input. Note: Not reverse voltage
protected.
These output pins drive the bi-directional motor and must be connected together
on the PC board.
These pins must be connected on the PC board to the exposed pad.
These pins have no internal connections.
This output pin pulses high anytime the low-side current comparator is tripped.
33899
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33899 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 12.
Pin Number
Pin Name
Formal Name
Definition
24
RS
Slew Rate Control
25
PWM
PWM Input
26
FWD
Forward Input
This input pin, along with the reverse input pin REV, determines the direction of
current flow in the H-Bridge.
27
REV
Reverse Input
This input pin, along with the forward input pin FWD, determines the direction of
current flow in the H-Bridge.
28
VCCL
3.3 V Input
3.3 V input source.
29
VCC
5.0 V Input
5.0 V input source.
30
CSNS
Current Sense
Tab/Pad
Thermal
Interface /
GND
Exposed Pad Thermal
Interface
This input pin is connected to a resistor that sets slew timing.
This input pin is used to set the motor switching and frequency duty cycle.
Output of current amplifier.
The exposed pad, a thermal interface for sinking heat from the device, is a highcurrent GND connection and must be connected to GND (pins 12 and 19).
33899
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VIGNP
- 0.3 to 40
V
VCC
- 0.3 to 7.0
V
Logic Output Bias Voltage
VDDQ
- 0.3 to 7.0
V
VCCL Supply Voltage
VCCL
- 0.3 to 5.0
V
Input / Output Voltage (FWD, REV, EN1, EN2, PWM, CS, DI, SCLK, DO, CSNS,
LSCMP, RS, REDIS)
VI / O
- 0.3 to 7.0
V
VS0, VS1
- 0.5 to 40
V
VCRES
- 0.3 to 50
V
Human Body Model
VESD1
± 2000
Machine Model
VESD2
± 200
TA
- 40 to 125
TJ
- 40 to 150
TSTG
- 65 to 150
°C
RθJA
18
°C/W
RθJC
<0.5
°C/W
T SOLDER
220
°C
ELECTRICAL RATINGS
Protected Power Supply Voltage
Logic Supply Voltage
Motor Outputs
Charge Pump Voltage
V
ESD Voltage (1)
THERMAL RATINGS
°C
Operating Temperature(2)
Ambient
Junction
Storage Temperature
Thermal Resistance, Junction to Ambient
(3)
Thermal Resistance, Junction to Case (Exposed Pad)
Peak Package Reflow Temperature During Solder Mounting (4)
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
2.
3.
4.
The junction temperature is the primary limiting parameter. The module thermal design must provide a low enough thermal impedance
to keep the junction temperature within limits for all anticipated power levels and ambient temperatures.
RθJA is referenced to JEDEC standard 2s2p thermal evaluation board at 1W total device power dissipation in still air. Deviations from
this standard will produce corresponding changes in the actual thermal performance.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics at - 40°C ≤ TJ ≤ +150°C, 4.75 V ≤ VCC ≤ 5.25 V, 3.14 V ≤ VCCL ≤ 3.47 V, 2.97 V ≤ VDDQ ≤ 5.25 V, 6.0 V ≤ VIGNP
≤ 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VIGNP Operating Voltage
VIGNP
6.0
–
26.5
V
VIGNP Operating Current
IVIGNP
–
–
10
–
–
145
POWER INPUT
VIGNP = 14.5 V, H-Bridge Disabled, EN1 = EN2 = 5.0 V
VIGNP Sleep Current
mA
µA
IVIGNP
EN1 = EN2 = 0 V
Undervoltage Shutdown Threshold
VIGNP UV
3.4
–
4.2
V
Overvoltage Shutdown Threshold
VIGNP OV
27
–
32
V
VCC Operating Voltage
VCC
4.75
–
5.25
V
VCC Operating Current @ 5.0 V
IVCC
–
–
5.0
mA
VCC Sleep Current
IVCC
–
–
25
EN1 = EN2 = 0 V
µA
VCCL Operating Voltage
VCCL
3.14
–
3.47
V
VCCL Operating Current @ 3.3 V
IVCCL
–
–
3.0
mA
VCCL Sleep Current
IVCCL
EN1 = EN2 = 0 V
µA
–
–
2.0
VDDQ Operating Voltage
VDDQ
2.97
–
5.25
V
VDDQ Operating Current
IVDDQ
–
–
200
µA
VDDQ Sleep Current
IVDDQ
–
–
50
3.9
–
4.7
2.50
–
2.95
0.2
–
0.5
14
–
–
VIGNP + 10
–
45
EN1 = EN2 = 0 V
µA
POWER-ON RESET
Power-ON Reset Threshold
VCCPOR
VCC Rising
Power-ON Reset Threshold
VCCLPOR
VCCL Rising
Power-ON Reset Hysteresis
V
VPOR HYS
V
V
CHARGE PUMP
CRES Voltage (MOSFETs 1 and 3 or 2 and 4 ON) ICRES = - 0.1 mA
VCRES
VIGNP = 6.0 V
9.5V ≤ VIGNP ≤ 26.5 V
V
CONTROL INPUTS
Input Low Voltage
VIL
–
EN1, EN2, PWM, CS, SCLK, DI, FWD, REV
Input High Voltage
EN1, EN2, PWM, CS, SCLK, DI, FWD, REV
V
–
0.8
VIH
V
2.0
–
–
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics at - 40°C ≤ TJ ≤ +150°C, 4.75 V ≤ VCC ≤ 5.25 V, 3.14 V ≤ VCCL ≤ 3.47 V, 2.97 V ≤ VDDQ ≤ 5.25 V, 6.0 V ≤ VIGNP
≤ 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INPUTS (CONTINUED)
Input Leakage Current — Digital Inputs
µA
IIN
- 5.0
–
5.0
IDWN
27
–
70
IUP
- 70
–
- 27
–
–
0.4
VDDQ - 0.5
–
–
- 5.0
–
5.0
40
–
–
–
–
165
–
–
1.0
–
–
1.4
–
–
1.8
0.2 VCC
–
0.6 VCC
VCC = 0 V, EN1 = EN2 = 0 V, RL = 600 Ω, VIGN = 16 V
–
–
100
VCC = 5.0 V, EN1 = EN2 = 0 V, RL = 600 Ω, VIGN = 18 V
–
–
100
SCLK, DI: VIN = 0 V
µA
Input Bias Current
EN1, EN2, FWD, REV, PWM: VIN = 5.0 V
CS: VIN = 0 V
DATA OUTPUT
Data Output Low Voltage
VDO_OL
IOL = 1.6 mA
Data Output High Voltage
VDO_OH
IOH = - 800 µA
Data Out Tri-State Leakage
V
ILEAK
V
µA
POWER OUTPUT
Breakdown Voltage
VBVDS
S0, S1, VIGNP: I = 100 µA
ON-Resistance (Each Output FET)
RDS(ON)
IOUT = 3.5 A, VIGNP = 6.0 V
Body Diode Forward Voltage (All 4 Output Diodes) (6)
ENx = 0 V, IOUT = 3.0 A, TJ = 23°C
ENx = 0 V, IOUT = 3.0 A, TJ = -40°C
V
VBIAS
VCC = 5.0 V, EN1 = EN2 = 0 V, S0 Shorted to S1 (Through Motor)
OFF-State Output Leakage (between SO and S1)
mΩ
VF
ENx = 0 V, IOUT = 3.0 A, TJ = 150°C
OFF-State Output Bias
V
V
µA
ILEAK
V
Fault Threshold (OFF State) (EN1 = EN2 = 0 V)
Measured at S1
VFAULT_THR1
0.65 VCC
–
0.85 VCC
Measured at S0
VFAULT_THR2
0.15 VCC
–
0.35 VCC
ICSZ
–
–
0.2
kCSNS
250
–
500
kCSNS
340
–
435
kCSNS
–
400
–
CURRENT SENSE
Current Sense Zero
FWD = 5.0 V, REV = 0 V; Then FWD = 0 V, REV = 5.0 V, IS1/S0 = 0 A
mA
Current Sense Ratio: kCSNS = IS1/S0 / ICS
(FWD = 5.0 V, REV = 0 V; Then FWD = 0 V, REV = 5.0 V)
IS1/S0 = - 0.4 A
IS1/S0 = - 1.6 A
IS1/S0 = - 6.0 A(7)
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Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics at - 40°C ≤ TJ ≤ +150°C, 4.75 V ≤ VCC ≤ 5.25 V, 3.14 V ≤ VCCL ≤ 3.47 V, 2.97 V ≤ VDDQ ≤ 5.25 V, 6.0 V ≤ VIGNP
≤ 26.5 V unless otherwise noted. Typical values reflect the approximate parameter means at TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VCSNS_SAT
VCC - 0.2
–
VCC + 0.2
V
5.8
–
10.2
CURRENT SENSE (CONTINUED)
Current Sense Saturation Voltage
FWD = 5.0 V, REV = 0 V; Then FWD = 0 V, REV = 5.0 V, RCSNS= 10 kΩ
IHSLIM
High-Side Current Limit
DI Bit 4 and Bit 3 = 00
A
7.2
–
11.9
DI Bit 4 and Bit 3 = 10
(5)
8.0
–
13.5
DI Bit 4 and Bit 3 = 11
(5)
10.0
–
17.9
DI Bit 4 and Bit 3 = 00
5.3
–
8.6
DI Bit 4 and Bit 3 = 01
6.4
–
10.0
DI Bit 4 and Bit 3 = 10
7.4
–
11.0
10.0
–
15.0
DI Bit 4 and Bit 3 = 00
3.2
–
5.2
DI Bit 4 and Bit 3 = 01
4.2
–
6.4
DI Bit 4 and Bit 3 = 10
5.0
–
7.5
DI Bit 4 and Bit 3 = 11
7.5
–
10.6
1.0
3.0
–
DI Bit 4 and Bit 3 = 01
1.0
3.0
–
DI Bit 4 and Bit 3 = 10
1.0
3.0
–
DI Bit 4 and Bit 3 = 11
1.0
3.0
–
DI Bit 4 and Bit 3 = 01
Low-Side Current Limit
ILSLIM
DI Bit 4 and Bit 3 = 11
Low-Side Current Limit Comparator
Current Limit Current Comparator Differential
DI Bit 4 and Bit 3 = 00
A
ILSCMP
ICURLIM ILSCMP
A
A
V
LSCMP Output Voltage
IOL = 100 µA
VLSCMP_OL
–
–
0.1
IOH = -100 µA
VLSCMP_OH
VDDQ-0.5
–
VDDQ
Pullup Current Source
IREDIS_sc
-160
–
-70
µA
Pulldown Current Sink
IREDIS_sk
1.0
5.0
mA
REDIS Current
REDIS Threshold
VREDIS_THR
V
Voltage Where Low-Side MOSFET Turns On
3.6
–
4.4
Voltage Where Low-Side MOSFET Turns Off
3.35
–
4.15
Hysteresis
0.15
–
0.35
THERMAL
Thermal Shutdown (6), SPI Bits = 11
TLIM
157.5
–
172.5
°C
Thermal Hysteresis (6)
THYS
3.0
–
10
°C
TWARN
132.5
–
147.5
°C
TWARN(HYS)
3.0
–
10
°C
Temperature Warning (6), SPI Bits = 01
Temperature Warning Hysteresis (6)
Notes
5. Production test at 125°C is at VIGNP ≤ 18 V. Operation to 26.5V is guaranteed by design.
6.
7.
Guaranteed by characterization in the development phase. Parameter not tested.
Design Information, not production tested.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics at - 40°C ≤ TA ≤ 125°C, 4.75 V ≤ VCC ≤ 5.25 V, 6.0 V ≤ VIGNP ≤ 26.5 V unless otherwise noted. Typical values
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
PWM Frequency (8)
PWM / Output Duty Cycle Accuracy
Symbol
Min
Typ
Max
Unit
f PWM
–
–
11
kHz
-4.5
–
4.5
t SCF
5.0
–
11
µs
PWMMIN
–
–
0.2
µs
5.0
–
10
5.0
–
10
OUTACC
Frequency = 10 kHz, RS = 10 kΩ, Slew Time = 1X, Duty cycle = 50%
Short Circuit Filter (S0 and S1)
Minimum PWM Low Pulse Width (8)
Low-Side Comparator One Shot
µs
t LSC
Pulse Duration After a Low-Side Comparator Trip
Low-Side Comparator Blank Time
%
µs
t LSCB
Blanking Time After a Low-Side Comparator Pulse
Overtemperature Shutdown Filter (time before Die Temp bit is set), (8)
t OTF
5.0
–
13.5
µs
Enable Lead Time (8)
t LEAD
140
–
–
ns
Enable Lag Time (8)
t LAG
50
–
–
ns
–
–
5.0
1.0
–
3.0
200
–
400
100
–
200
–
150
–
Delay Until Output Shuts Off
Dead Timer (9)
Slew Time S0 and S1(11)
µs
t OVS
Time from VIGNP > VOV to MOSFET Output Disable
Sleep Recovery Time(8)(9)(10)
µs
t FDO
Duration of Fault Condition Until Fault Gets Latched In
Overvoltage Shutdown Filter
µs
t DEAD
Time Between High-Side MOSFET and Low-Side MOSFET Transition
Open Load Fault Delay
µs
t SODLY
Short Circuit Detection or EN1 Falling or EN2 Falling Until H-Bridge Disables
t SLEEP
µs
µs
S0 / S1RS
(Output Load = 5.0 mH and 1.6 Ω, 30% to 70%, VIGNP = 14.5 V)
Slew Mode = 1X
RS= 50 kΩ
1.6
0.2
–
–
3.2
0.8
2.8
0.5
–
–
6.3
1.5
RS = 50 kΩ
5.0
RS = 10 kΩ, Short
1.2
–
–
12.8
3.0
RS = 10 kΩ, Short
Slew Mode = 2X
RS = 50 kΩ
RS = 10 kΩ, Short
Slew Mode = 4X
Notes
8. Design information.
9. Guaranteed by characterization in the development phase. Parameter not tested.
10. Sleep recovery time is the time from EN going high until the outputs are ready to respond to input. This time is dependent on the recovery
time of VCCL and VCCL_POR. The recommended value for the VCCL capacitor is designed to permit initialization of internal logic prior to
clearing of the POR condition (See + 3.3 V Input (VCCL) on page 12).
11.
By design, if the RS input is left open, the slew time is the same as when shorted to GND. However, this is a high-impedance input and
will be susceptible to external noise sources unless terminated appropriately. It is highly recommended to terminate this pin with either
a ground or one of the program resistors .
33899
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics at - 40°C ≤ TA ≤ 125°C, 4.75 V ≤ VCC ≤ 5.25 V, 6.0 V ≤ VIGNP ≤ 26.5 V unless otherwise noted. Typical values
reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
f OP
dc
–
6.25
MHz
t SCLK
160
–
–
ns
SCLK High Time (13)
t SCLK_HS
56
–
–
ns
SCLK Low Time (13)
t SCLK_LS
56
–
–
ns
DI Input Setup Time (13)
t DI(SU)
16
–
–
ns
DI Input Hold Time (13)
t DI(HOLD)
20
–
–
ns
DO Access Time
t DO(ACC)
–
–
116
ns
DO Disable Time (14)
t DO(DIS)
–
–
100
ns
DO Output Valid Time
t DO(VALID)
–
–
116
ns
DO Output Hold Time (13)
t DO(HOLD)
0
20
–
SPI CHARACTERISTICS (12)
Transfer Frequency (13)
SCLK Period (13)
No Capacitor on DO
ns
Rise Time (14)
tR
–
–
60
ns
Fall Time (14)
tF
–
–
30
ns
CS Negated Time (13)
t CSN
500
–
–
ns
Input Pins Input Capacitance (8)
C IN
DI
–
–
20
SCLK
–
–
20
pF
Notes
12. All SPI timing is performed with a 100 pF load on DO unless otherwise noted.
13. Design information.
14. Guaranteed by characterization.
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Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
t LAG
t CSN
CS
t LEAD
t SCLK_HS
t SCLK
SCLK
t SCLK_LS
t DO(ACC)
MSB OUT
DO
t DI(SU)
DI
t DO(HOLD)
t DO(VALID)
DATA
t DO(DIS)
DON’T CARE
LSB OUT
t R, t F
t DI(HOLD)
DATA
MSB IN
LSB IN
Figure 4. SPI Timing Diagram
5.0V
VENx
2.0V
0.8V
tSODLY
tENDLY
VS0-S1
@100mA
Figure 5. Shut Off and Enable Delay
S0/S1RS
VS0-S1
S0/S1RS
70%
30%
70%
30%
Figure 6. Slew Time Measurement
33899
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33899 is a programmable H-Bridge, power integrated
circuit (IC) designed to drive DC motors or bi-directional
solenoid controlled actuators, such as throttle control or
exhaust gas recirculation actuators. It is particularly well
suited for the harsh environment found in automotive power
train systems.
The key characteristic of this versatile driver is
configurability. The selectable slew rate permits the customer
to choose the slew rate needed for performance and noise
suppression. The Serial Peripheral Interface (SPI) allows the
system microprocessor to clear the fault register, select a
programmable current limit and select the slew rate. A unique
fault restart feature allows the part to be configured to
maintain limited functionality even in the presence of some
faults.
The 33899 is designed to drive a bi-directional DC motor
using pulse-width modulation (PWM) for speed and torque
control. A current mirror output provides an analog feedback
signal proportional to the load current. SPI diagnostic
reporting includes open circuit, short-to-battery, short-toground, die temperature range and under voltage.
FUNCTIONAL PIN DESCRIPTION
VIGNP INPUT (VIGNP)
OUTPUT POLARITY CONTROL (FWD/REV INPUTS)
VIGNP is the primary power input for the H-Bridge. The
input voltage is 0 V to 26.5 V (40 V during a load dump
transient). This pin must be externally protected against
application of a reverse voltage (through an external inverted
N-channel MOSFET, diode, or switched relay).
The FWD and REV inputs determine the direction of
current flow in the H-Bridge by directing the PWM input to one
of the low-side MOSFETs (refer to Table 5). When a change
in the current direction is commanded via the
microprocessor, the PWM must switch from one low-side
MOSFET to the other without shoot-through current in the HBridge. The gate voltage of the low-side MOSFETs must drop
below and remain below the gate threshold voltage for the
“dead time” before either of the high-side MOSFETs is
commanded on. At no time are the high-side and low-side
MOSFETs simultaneously on at the same side of the HBridge. The FWD and REV inputs have 50 µA pull-downs to
ground that disable all the outputs should an open circuit
condition occur.
+ 5.0 V INPUT (VCC)
+5.0 V power input is required to power the internal analog
circuitry and the +3.3 V internal regulator.
+ 3.3 V INPUT (VCCL)
A +3.3 V internal regulator powers the internal digital
circuitry. The internal supply cannot be used as a power
source by any other IC in the system. This output can be
overdriven by an external supply. The internal supply
requires a 0.47 µF capacitor on this output to insure proper
startup sequencing when coming out of sleep mode.
LOGIC BIAS INPUT (VDDQ)
VDDQ supplies the level shifted bias voltage for the logic
level outputs designed to be read by the microprocessor. This
pin will apply the logic supply voltage to DO and LSCMP
making the output logic levels compliant to logic systems
from 3V to over 5V.
OUTPUTS (S1 AND S0)
The S1 and S0 outputs drive the bi-directional DC motor.
Each output has two internal N-channel MOSFETs
connected a half-bridge configuration between VIGNP and
ground. Only one internal MOSFET is on at any one time for
each output. The FWD, REV, and PWM inputs control the
state of the H-Bridge. The turn on / off slew times are
determined by the selected RS resistor value and the SPI
slew time register contents (refer to Table 8, page 22).
Table 5. FWD / REV Truth Table
FWD
REV
Current Direction
0
0
Off
0
1
Reverse
1
0
Forward
1
1
Off
ENABLE INPUTS (EN1, EN2)
Logic [0] in either of the Enables (EN1 or EN2) disables all
four of the output drivers (refer to Table 6). While either EN1
or EN2 is at logic [1], the 33899 is still capable of detecting
open circuit and short circuit faults on all of the outputs
interfacing with the external load(s). The EN1 and EN2 inputs
have 50 µA pull-downs to ground that disable the outputs
when open circuit conditions occur.
Table 6. Enable Truth Table
EN1
EN2
Status
0
0
Disabled (Sleep Mode)
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Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
EN1
EN2
Status
0
1
Disabled (Standby Mode)
1
0
Disabled (Standby Mode)
1
1
Enabled (Run Mode)
INPUT CONTROL OF H-BRIDGE (PWM)
The PWM input pin controls the sequencing of the
PWM’ing high-side and low-side MOSFETs. A logic [1]
commands the appropriate low-side MOSFET (M2 or M4) ON
and the appropriate high-side MOSFET (M1 or M3) OFF. A
logic [0] commands the appropriate low-side MOSFETs (M2
or M4) OFF and the appropriate high-side MOSFETs (M1 or
M3) ON. The high- and low-side MOSFETs that are PWM’ed
are determined by the commanded direction (FWD or REV).
If a shorted condition exists, the particular output MOSFET
will be latched off after 5.0 µs to 10 µs. Subsequent PWM
edges will retry to turn on the same MOSFET. Only when a
thermal fault is reached are all outputs latched off until the
clear fault bit is set by the microprocessor. Any PWM high-tolow-to-high pulse that is shorter than 500 ns keeps the lowside MOSFET from starting to turn off. The rising edge of this
short pulse re-enables the low-side MOSFET if the pulse
width is at least 200 µs long (if a short circuit latch-off had
occurred during the previous positive PWM pulse). The PWM
input has a 50 µA pull-down to ground that disables all the
outputs should an open circuit condition occur.
High Side FET
Body Diode
S0
S1
Load Current
Low Side FET
Body Diode
Both High Side
FET’s ON until
next PWM Rising
Edge
Current in Load
reverses polarity
Forward Current
Reverse Current
PWM
FWD
REV
Figure 7. 33899 Operation in Current Reversal
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Freescale Semiconductor
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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
LOAD CURRENT FEEDBACK (CSNS)
HIGH-SIDE AND LOW-SIDE SLEW TIME CONTROL
(RS)
The load current sense circuit mirrors a sample of the load
current back to the microcontroller via the CSNS pin. It
supplies a current that is 1/400th of the load current (see
Equation 1). An analog multiplexer routes the enabled highside current to the CSNS pin. An external resistor connected
to the CSNS pin (RCSNS) sets current to voltage gain. The
circuit operates properly in the presence of high-frequency
noise. An external capacitor may be necessary to provide
filtering.
VCSNS =
IOUT
400
The turn-on and the turn-off slew times on S0 and S1 (both
low- and high-side drive outputs) are adjustable from 5.0 µs
(50 kΩ RS) to 1.0 µs (10 kΩ RS) to reduce high-frequency
harmonic energy in the vehicle’s wiring harness. In addition,
slew time control is programmable to be either 1X, 2X, or 4X
(via the SPI) to lower power dissipation at elevated die
temperatures. The characteristics of the turn-on and turn-off
voltage are linear, with no discontinuities, during the output
driver state transitions. If the RS pin detects an impedance of
less than 5.0 kΩ to ground or greater than 1.0 MΩ to ground,
it defaults to the fastest slew time of 1.0 µs.
. RCSNS
Eq. 1
LOW-SIDE COMPARATOR ONE SHOT OUTPUT
(LSCMP)
Note This output is clamped so that it will not exceed VCC.
The LSCMP output pin pulses high for 5 µs to 10 µs any
time the low-side comparator is tripped. Then the output goes
low during a 5 µs to 10 µs blanking time. If another low-side
comparator trip event is detected during the blanking time,
another 5 µs to 10 µs pulse high occurs immediately after the
blanking interval.
CHARGE PUMP RESERVOIR CAPACITOR (CRES)
The charge pump provides an output voltage over the full
operating VIGNP range that is sufficient to drive the output
MOSFETs and ensure that the output RDS(ON) specifications
are met. An external reservoir capacitor of 0.1 µF is
recommended. The charge pump operates at approximately
2.0 MHz to 4.0 MHz in order to prevent interference with AM
entertainment radio.
LS Current Comparator
Iload
5 - 10 µs
5 - 10 µs
PWM
> 40 µs
LSCmp
5 - 10 µs
Pulse Out
5 - 10 µs
Blank Time
5 - 10 µs
Pulse Out
The REDIS min duration = 25 µs,
so CREDIS must be > 1 nF
Figure 8. LS Current Comparator One Shot
AUTOMATIC OUTPUT RE-ENABLE DISABLE
(REDIS)
The REDIS input pin automatically re-enables the low-side
MOSFET once the REDIS input voltage exceeds 4.0 V. An
external capacitor (CREDIS) determines the time interval (see
Equation 2). Once a low-side current comparator is tripped, a
120 µA current source linearly charges the capacitor until
either the next rising edge of PWM or the 4.0 V trip level is
achieved. This re-enables the low-side output MOSFET and
discharges the capacitor to 0 V. This feature is disabled by
grounding this input.
dt =
CREDIS . dv
I
C . 4.0 V
=
120 µA
Eq. 2
As per the above equation, a 2.2 nF capacitor will provide
a nominal 75 µs time interval.
33899
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
LS Current Comparator
Iload
PWM
4 VDC
REDIS
t = 33.3 * C (nF) µs
tmin = 25 µs
Reset to
0 VDC
t = 33.3 * C (nF) µs
tmin = 25 µs
Reset to
0 VDC
Figure 9. Re-enable after a Low Side Current Comparator Trip
LOW-SIDE CURRENT COMPARATOR VS.
CURRENT LIMIT LEVELS
There are two different current limit thresholds for the lowside MOSFETs: current comparator and current limit. Current
comparator is the normal commanded switching current.
Current limit is for fault protection.
The inductance of the load results in just the current
comparator tripping. Once the low-side current comparator
has tripped and filter time expired, the low-side MOSFET
turns off and the high-side MOSFET subsequently turns on
for normal current re-circulation in the load. If an actual hard
short to either VIGNP or ground on the S0/S1 outputs is
encountered, the current limit kicks in and prevents large
current spikes from VIGNP (or to ground) to occur. The
threshold level of the current comparator vs. the high- and
low-side current limits is given in the Static Electrical
Characteristics table, page 8.
As backup protection, there is a linear overcurrent
controller to limit current spike during timer operations.
SERIAL PERIPHERAL INTERFACE (SPI)
The 33899 has a serial peripheral interface consisting of
Chip Select (CS), Serial Clock (SCLK), Serial Data Out (DO),
and Serial Data In (DI). This device is configured as a SPI
slave and is daisy-chainable (single CS for multiple SPI
slaves).
CHIP SELECT (CS)
The CS is a low = true input that selects this device for
serial transfers. On the falling edge of CS, the DO pin is
released from tri-state mode, and all status information is
latched in the SPI shift register. While CS is asserted, register
data is shifted into the DI pin and shifted out of the DO pin on
each subsequent SCLK. On the rising edge of CS, the DO pin
is placed in a high impedance state and the Fault register
reloaded (latched) with the current filtered status data. To
allow sufficient time to reload the Fault register, the CS pin
must remain low for a minimum of t CSN prior to going high
again.
By design, the CS input is immune to spurious pulses of
50 ns or shorter. (DO may come out of tri-state, but no status
bits are cleared and no control bits are changed.)
The CS input has a 50 µA current source to VCC, which
pulls this pin to VCC if an open circuit condition occurs. This
pin has TTL-level compatible input voltages, which allows
proper operation with microprocessors using a 3.0 V to 5.0 V
supply.
SERIAL CLOCK (SCLK)
The SCLK input is the clock signal input for
synchronization of serial data transfer. This pin has TTL-level
compatible input voltages, which allow proper operation with
microprocessors using a 3.3 V to 5.0 V supply.
When CS is asserted, both the microprocessor and the
33899 latch input data on the rising edge of SCLK. The SPI
master typically shifts data out on the falling edge of SCLK,
while the 33899 shifts data out on the falling edge of SCLK to
allow more time to drive the DO pin to the proper level.
SERIAL DATA OUTPUT (DO)
The DO is the SPI data out pin. When CS is asserted (low),
the MSB is the first bit of the word transmitted on DO and the
LSB is the last bit of the word transmitted on DO. After all 8
bits of the fault register are transmitted, the DO output
sequentially transmits the digital data that was just received
on the DI pin. This allows the processor to distinguish a
shorted DI pin condition. The DO output continues to transmit
33899
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
the input data from the DI input until CS eventually transitions
from a logic [0] to a logic [1].
The DO output pin is in a high impedance condition unless
CS is low, at least one enable pin is high and VCC and VCCL
are within the normal operating range. When active, the
output is “rail to rail”, depending on the voltage at the VDDQ
pin.
SERIAL DATA INPUT (DI)
The DI input takes data from the microprocessor while CS
is asserted (low). The MSB is the first bit of each word
received on DI and the LSB is the last bit of each word
received on DI. The 33899 serially wraps around the DI input
bits to the DO output after the DO output transmits its fault
flag bits. The first 8 bits before CS goes high are latched into
the Control register. Any bytes transmitted before the last 8
bits are just wrapped around to the DO output and are not
used by the 33899 (see Figure 10).
This pin has TTL-level compatible input voltages, which
allow proper operation with microprocessors using a 3.3 V to
5.0 V supply.
CS
CS*
DI/DI/
SCLK
SCLK
Not
NotUsed
Used(1(1Byte)
Byte)
ControlRegister
Register(1
(1 Byte)
Byte)
DIDIControl
DODO
Fault/Temp DataData
(1 Byte)
Fault/Temperature
(1 Byte)
1st DI
First
DIByte
Byte
Figure 10. SPI Operation with Extended CS
LOGIC OUT BIAS (VDDQ)
The VDDQ input pin provides the bias voltage for the data
out buffer and LS Comparator. It must be connected to the
same power supply that is used by the microprocessor’s SPI
I / O.
33899
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INTRODUCTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Current Sense
Voltage
Regulation
Temperature
Sense
Charge
Pump
Analog Control and Protection
SPI Interface
PWM Controller
Command and
Fault Registers
Direction
Control
H-Bridge
Output Drivers
S0 - S1
MCU Interface and Output Control
Figure 11. Functional Block Diagram
INTRODUCTION
H-BRIDGE OUTPUT DRIVERS (S0 AND S1)
The 33899 Power IC provides the means to efficiently
drive a DC motor in both forward and reverse shaft rotation
via a monolithic H-Bridge comprising low RDS(ON) N-channel
MOSFETs and integrated control circuitry. The switching
action of the H-Bridge can be pulse-width modulated to
obtain both torque and speed control, with PWM frequencies
up to 11 kHz supported with minimal switching losses.
The outputs comprise four Power MOSFETs configured as
a standard H-Bridge, controlled by the PWM input and the
FWD and REV inputs.
ANALOG CONTROL AND PROTECTION
The 33899 has integrated voltage regulators which supply
the logic and protection functions internally. This reduces the
requirements for external supplies and insures the device is
safely controlled at all times when battery voltage is applied.
An integrated charge pump provides the required bias
levels to insure the output MOSFETs turn fully ON when
commanded.
Each MOSFET provides feedback to the protection
circuitry by way of a current sensor. Each sense signal is
compared with programmable over-current levels and
produces an immediate shutdown in case of a high current
short circuit. The low-side current sense is also capable of
producing a current limiting PWM to reduce overload
conditions as determined by the programmable limits. The
high-side current sense is available to the MCU as an analog
current proportional to the load current.
Each MOSFET has over-temperature protection circuitry
that disables the device. A thermal warning sets a flag in the
SPI register when the device is approaching a protection
limit.
MCU INTERFACE AND OUTPUT CONTROL
The SPI and control logic signals are compatible with both
5V and 3.3V logic systems.
The SPI provides programmable control of output slew
rate and current limits. The status register makes detailed
diagnostics available for protective and warning functions.
The output drivers are controlled by the input signals EN1,
EN2, FWD, REV, and PWM.
The low-side and high-side MOSFETs connected to S0
are controlled by the PWM input when FWD is a logic [1] and
REV is a logic [0]. The low-side MOSFET connected to S1 is
idle in this state. The high-side MOSFET connected to S1 is
statically ON in the forward direction. The low-side and highside MOSFETs connected to S1 are controlled by the PWM
input when FWD is a logic [0] and REV is a logic [1]. The lowside MOSFET connected to S0 is idle in this state. The highside MOSFET connected to S0 is statically ON in the reverse
direction. To reduce power during the recirculation period,
the upper recirculation MOSFET is turned on synchronously
with the OFF-time of the low-side MOSFET.
33899
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Freescale Semiconductor
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FUNCTIONAL INTERNAL BLOCK DESCRIPTION
INTRODUCTION
The PWM input is connected to the system
microprocessor and provides for control of the four MOSFET
outputs. The PWM duty cycle range is 0% to 100%; however,
open load detection circuits require a minimum off-time.
The 33899 holds all outputs off if both FWD and REV are
either logic [0]s or logic [1]s. Figure 12 depicts inputs versus
outputs in forward mode operation.
VIGNP + VF
S0
RDS(ON) * ILOAD
VIGNP RDS(ON) * ILOAD
Load
Current
PWM
INPUT
M1 GATE
M2 GATE
Dead
Time
M3 is “ON”
M4 is “OFF”
Figure 12. 33899 Operation in Forward Mode
33899
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Analog Integrated Circuit Device Data
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Short-to-GND or Short-to-VIGNP Fault Filtering
The 33899 has a short-to-GND and short-to-VIGNP digital
fault filter. After a single fault occurrence, another 7 shorts
consecutive with PWM must be detected before the bit is
latched into the fault register.
Short to -1.0 V on Output Devices
The 33899 can survive a short to -1.0 V through a 300 mΩ
impedance (10 kHz to 1000 kHz) and a direct short to - 0.5 V
on all I/Os that exit the module. A shorted output to these
voltages does not impact correct fault diagnostics for the
effected channel or any other normal operation of the 33899.
This feature applies to the SO and S1 outputs as well.
Loss of Module Ground
Loss of ground condition at the parts level denotes that all
pins of the 33899 see very low impedance to ignition. In the
application, a loss of ground condition results in all I/O pins
floating to ignition voltage VIGNP, while all externally
referenced I/O pins are at worst case pulled to ground.
Loss of Module Ignition Supply
Loss of ignition condition at the parts level denotes that the
power input pins of the 33899 see infinite impedance to the
ignition supply voltage (depending on the application) but
there is some undefined impedance from these pins to
ground.
Output Driver Load(s)
The 33899 is capable of driving any PWM’ed inductive
load of up to 3.5 A of continuous average current (at a
maximum frequency of 11 kHz) with current feedback
capability. The 33899 drives ETC (Electronic Throttle
Control) motors. The typical characteristics of the ETC motor
are as follows:
•Resistance 1.25 Ω to 2.4 Ω (lumped resistance due to
actuator, harness, and connectors) over the
temperature range.
•Inductance 800 µH at 1000 Hz over the temperature
range.
Output Power Density
The die area for the output MOSFETs provides an
adequate thermal resistance to limit junction temperature to
150°C when the device is operated at 11 kHz, 3.5 A
continuous average current, and a 2.0 ms nominal transition
time. This applies to FR4 PC board with a metal pedestal
under the device, which provides a thermal path to the case
of the module.
Output Synchronous Rectification Control
The 33899 uses synchronous rectification to reduce the
power dissipation during the recirculation period. In order to
prevent shoot-through current, the 33899 has a dead time
circuit that turns on the upper recirculation MOSFET after the
lower gate voltage falls below the threshold voltage and turns
it off before the lower gate voltage rises above the threshold
voltage.
Output Overvoltage Shutdown
The 33899 disables all MOSFET outputs when VIGNP is
above the overvoltage shutdown threshold for a time period
greater than t OVS (refer to Dynamic Electrical Characteristics
table, page 9).
Output Avalanche Protection
An inductive fly-back event, namely when the outputs are
suddenly disabled and VIGNP is lost, could result in electrical
overstress of the drivers. To prevent this the VIGNP input to
the 33899 should not exceed 40 V during a fly-back
condition. A zener clamp and/or an appropriately valued
capacitor are common methods of limiting the transient.
Power-ON Reset (POR)
On power-up, the VCC and VCCL supplies to the 33899
typically increase to 5.0 V and 3.3 V, respectively, within
0.3 ms to 3.0 ms. The 33899 has power-ON reset (POR)
circuitry that monitors both the VCC and VCCL voltages.
When either voltage falls below its POR threshold, the S0 and
S1 outputs are driven to the inactive state. When both
voltages rise above the POR threshold, the outputs are
enabled. During POR none of the outputs momentarily
glitches ON. The contents of all SPI registers (both DI and
DO) are cleared on each power-ON reset cycle. See + 3.3 V
Input (VCCL) on page 12 for part requirements to guarantee
normal operation.
Fault Detection
Open load detection is performed in the OFF state, and
short circuit fault detection is performed while the H-Bridge
circuit(s) are enabled (see Figure 13, page 20). However, the
user can determine whether an open circuit has caused the
output current to go to 0 A via the CSNS output. All valid
faults are latched into the SPI Fault register and cleared when
a logic [1] is written to the FLTCLR bit by the system
microprocessor (refer to Table 8, page 22).
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
pulled down internally to ground. In a normal load state, the
low impedance (relative to the internal pull-ups/pull-downs)
will force both load connections to about 0.5 VCC. S1 is
compared with an internal reference of 0.75 VCC nominally,
while S0 is compared to an internal reference of 0.25 VCC
nominally. Table 7 indicates what status the load will be in
based on the combination of the outputs of these two
comparators.
EN1
EN2
VCC
12 kΩ
OF
S1
0.75 VCC
Table 7. OFF-State Fault Detection
SGF
SGFON
0.25 VCC
Fault
Timer
S0
SBFON
12 kΩ
SBF
Note SGFON and SBFON are ON-State Fault.
Figure 13. OFF-State Fault Detection Diagram
In the full or half H-Bridge mode an open, short to ignition,
or short to GND latches the appropriate SPI fault bits until the
FLTCLR bit is set. Any additional faults that occur prior to
setting FLTCLR will be ignored.
Fault Detection During OFF State
Fault detection for both the high-side and low-side outputs
is done during the OFF state, when either the EN1 or EN2 pin
is a logic [1], by analyzing the states of both the high-side and
low-side outputs interacting to the external load. S1 is pulled
up internally via a high-impedance pullup to VCC, while S0 is
S1
S0
Load Status
< 0.75 VCC
> 0.25 VCC
Normal Load
< 0.75 VCC
< 0.25 VCC
Short to Ground
> 0.75 VCC
< 0.25 VCC
Open Load
> 0.75 VCC
> 0.25 VCC
Short to VIGNP
Once any of the above faults are indicated for a period of
time exceeding the OFF-state fault timer, the fault bit will be
latched into the SPI Fault register. The OFF-state fault timer
is started when either the EN1 or EN2 pin transitions from a
logic [1] to a logic [0] (both inputs previously logic [1]) or from
a logic [0] to a logic [1] (both inputs previously logic [0]). The
OFF-state filter time is substantially longer than the ON-state
to allow energy in the load to dissipate. False open state
faults may be set when the outputs are shut down and the
load current (reverse polarity only) takes more than the OFFstate filter time to decay to zero. The microprocessor should
clear the open state fault SPI bit and read the Fault register
again under this condition.
Load Current
(Reverse Polarity)
S0
S1
EN1
S0/S1 are at 2.5 VDC,
No SPI Bits Set
EN2
Wake Up, Open
Fault Timer Starts
tFDO
Open Fault
Timer Starts
Goo Back
to Sleep
Current in Load < 0, Erroneous
Open Fault SPI Bit Set
tFDO
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Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Fault Detection During ON State
While the H-Bridge circuit is in operation (i.e., when a highside MOSFET is ON), the 33899 is capable of detecting both
shorts to VIGNP and shorts to ground. A short will cause the
appropriate MOSFETs to current limit. The current limit is
active for numerous retry periods until an overtemperature
condition is reached, at which time all outputs are turned
OFF.
All ON-state faults must be present for a period of time that
exceeds the fault time before the 33899 will consider them
valid. Once they are valid, they are latched until the SPI has
reported these faults to the microcontroller via the DO pin and
a logic [1] is written to the FLTCLR bit.
In order for the user to be certain that all detectable ONstate faults have been reported, a minimum ON time is
required for the low-side MOSFET. For example, if the PWM
frequency is 11 kHz, ON-state fault detection would not be
guaranteed for duty cycles of less than 11%.
Thermal Shutdown
The H-Bridge has thermal protection circuitry. A thermal
fault sets the thermal shutdown bits (and any other faults that
may be present at that time) and latches off. The H-Bridge will
remain disabled until the microprocessor sets the FLTCLR bit
(refer to Table 8, page 22).
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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI INTERFACE AND REGISTER DESCRIPTION
SPI Control Register Definition
An 8-bit SPI allows the system microprocessor to clear the
Fault register, select a programmable current limit, and select
a 1X, 2X, or 4X slew rate. The SPI Control Register bit
definitions are shown in Table 8.
Note At POR, all bits in the register are cleared to 0s.
Table 8. SPI Control Register Bit Definitions
8 (MSB)
7
6
5
4
3
2
1 (LSB)
FLTCLR
Not Used
Not Used
Not Used
Current Limit
Current Limit
Slew Time
Slew Time
Bit 8: FLTCLR: 0 = Retain faults; 1 = Clear faults
Bit 7: Not used
Bit 6: Not used
Bit 5: Not used
Bits 4 – 3: Set Low Side Current Comparator Limits
00 = 4.0 A
01 = 5.0 A
10 = 6.0 A
11 = 8.5 A
Bits 2 – 1: Slew Time
00 = 1X
01 = 2X
10 = 4X
11 = 4X
SPI Fault Register Definition
The fault diagnostic capability consists of one internal 8-bit
Fault register. Table 9 shows the content of the Fault register.
The output load status of the H-Bridge circuit is reported via
the output DO SPI bits. In addition to output fault information,
die temperature warnings and overtemperature conditions
are reported.
An SPI read cycle is limited by a CS logic [1] to logic [0]
transition, followed by 8 SCLK cycles to shift the fault register
bits out the DO pin. The rising edge of CS sets DO in a high
impedance mode and clears the fault latches if the FLTCLR
bit is set. The thermal fault is immediately set again if the fault
condition is still present. Accurate fault reporting can only be
obtained by reading the DO line at intervals greater than the
fault timer. A thermal fault will be latched as soon as it occurs.
Note At POR, all bits in the register are cleared to 0s.
Table 9. SPI Fault Register Bit Definitions
8 (MSB)
7
6
5
4
3
2
1 (LSB)
ShVIGNP
ShGnd
Open Fault
Overvoltage or
Undervoltage
LS Comparator
EN1, EN2
Status
Die Temp
Die Temp
Bit 8: Short to VIGNP: 0 = No fault; 1 = S1 or S0 shorted to VIGNP (Low-Side Linear Current Limit has tripped)
Bit 7: Short to Ground: 0 = No fault; 1 = S1 or S0 shorted to GND (High-Side Linear Current Limit has tripped)
Bit 6: Open Fault: 0 = No fault; 1 = S1 or S0 is Open Circuited
Bit 5: Overvoltage or Undervoltage: 0 = No fault; 1 = Overvoltage/undervoltage fault
Bit 4: Low-Side Comparator: 0 = No trip; 1 = Tripped
Bit 3: XOR function of EN1, EN2 inputs. 0 = (EN1 same logic level as EN2). 1 = (EN1 not same logic level as EN2).
Bits 2 – 1: Die Temperature
00 = T < 140°C
01 = 140°C < T < Overtemperature Shutdown
10 = Not Defined
11 = Overtemperature Shutdown (Latched Off)
33899
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
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PACKAGING
PACKAGE DIMENSIONS
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Analog Integrated Circuit Device Data
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PACKAGING
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
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Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
2.0
DATE
6/2006
DESCRIPTION OF CHANGES
•
Initial Release
33899
Analog Integrated Circuit Device Data
Freescale Semiconductor
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MC33899
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