Freescale MC68HC711K4MFN4 8-bit microcontroller Datasheet

Freescale Semiconductor, Inc.
Order this document
by MC68HC11KTS/D
M68HC11 K Series
Technical Summary
8-Bit Microcontroller
Freescale Semiconductor, Inc...
The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the
MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1,
MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmultiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static
design allows operation at frequencies from 4 MHz to dc.
This document contains information concerning standard, custom-ROM, and extended-voltage devices. Standard devices include those with disabled ROM (MC68HC11K1), disabled EEPROM
(MC68HC11K3), disabled ROM and EEPROM (MC68HC11K0), or EPROM replacing ROM
(MC68HC711K4). Custom-ROM devices have a ROM array that is programmed at the factory to customer specifications. Extended-voltage devices are guaranteed to operate over a much greater voltage
range (3.0 Vdc to 5.5 Vdc) at lower frequencies than the standard devices. Refer to the device ordering
information tables for details concerning these differences.
1 Features
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 768 Bytes RAM (All Saved During Standby)
• 24 Kbytes ROM or EPROM
• 640 Bytes Electrically Erasable Programmable Read Only Memory (EEPROM)
• Optional Security Feature Protects Memory Contents
• On-Chip Memory Mapping Logic Allows Expansion to Over 1 Mbyte of Address Space
• PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint)
• Nonmultiplexed Address and Data Buses
• Four Programmable Chip Selects with Clock Stretching (Expanded Modes)
• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler
— Three Input Capture (IC) Channels
— Four Output Compare (OC) Channels
— One Additional Channel, Selectable as Fourth IC or Fifth OC
• 8-Bit Pulse Accumulator
• Four 8-Bit or Two 16-Bit Pulse Width Modulation (PWM) Timer Channels
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog
• Clock Monitor
• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Enhanced Synchronous Serial Peripheral Interface (SPI)
• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter
• Seven Bidirectional Input/Output (I/O) Ports (54 Pins)
• One Fixed Input-Only Port (8 Pins)
• Available in 84-Pin Plastic Leaded Chip Carrier (PLCC), 84-Pin Windowed Ceramic Leaded Chip
Carrier (CLCC), and 80-Pin Quad Flat Pack (QFP)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1997
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Freescale Semiconductor, Inc.
Table 1 Standard Device Ordering Information
Package
Temperature
CONFIG
Description
Frequency
MC Order Number
84-Pin PLCC
–40°to + 85°C
$DF
BUFFALO ROM
4 MHz
MC68HC11K4BCFN4
–40°to + 85°C
$DD
No ROM
–40°to + 105°C
Freescale Semiconductor, Inc...
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
80-Pin QFP
(14 mm X 14
mm)
$DD
$DC
$DC
$DC
$DF
$DF
$DF
No ROM
No ROM
No ROM, No EEPROM
No ROM, No EEPROM
No ROM, No EEPROM
OTPROM
OTPROM
OTPROM
–40°to + 85°C
$DF
BUFFALO ROM
–40°to + 85°C
$DD
No ROM
–40°to + 105°C
–40°to + 85°C
–40°to + 105°C
MOTOROLA
2
$DD
$DD
$DC
$DC
No ROM
No ROM, No EEPROM
No ROM, No EEPROM
2 MHz
MC68HC11K1CFN2
3 MHz
MC68HC11K1CFN3
4 MHz
MC68HC11K1CFN4
2 MHz
MC68HC11K1VFN2
3 MHz
MC68HC11K1VFN3
4 MHz
MC68HC11K1VFN4
2 MHz
MC68HC11K1MFN2
3 MHz
MC68HC11K1MFN3
4 MHz
MC68HC11K1MFN4
2 MHz
MC68HC11K0CFN2
3 MHz
MC68HC11K0CFN3
4 MHz
MC68HC11K0CFN4
2 MHz
MC68HC11K0VFN2
3 MHz
MC68HC11K0VFN3
4 MHz
MC68HC11K0VFN4
2 MHz
MC68HC11K0MFN2
3 MHz
MC68HC11K0MFN3
4 MHz
MC68HC11K0MFN4
2 MHz
MC68HC711K4CFN2
3 MHz
MC68HC711K4CFN3
4 MHz
MC68HC711K4CFN4
2 MHz
MC68HC711K4VFN2
3 MHz
MC68HC711K4VFN3
4 MHz
MC68HC711K4VFN4
2 MHz
MC68HC711K4MFN2
3 MHz
MC68HC711K4MFN3
4 MHz
MC68HC711K4MFN4
4 MHz
MC68HC11K4BCFU4
2 MHz
MC68HC11K1CFU2
3 MHz
MC68HC11K1CFU3
4 MHz
MC68HC11K1CFU4
2 MHz
MC68HC11K1VFU2
3 MHz
MC68HC11K1VFU3
4 MHz
MC68HC11K1VFU4
2 MHz
MC68HC11K0CFU2
3 MHz
MC68HC11K0CFU3
4 MHz
MC68HC11K0CFU4
2 MHz
MC68HC11K0VFU2
3 MHz
MC68HC11K0VFU3
4 MHz
MC68HC11K0VFU4
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
Table 1 Standard Device Ordering Information (Continued)
Package
Temperature
CONFIG
Description
84-Pin CLCC
(Windowed)
–40°to + 85°C
$DF
EPROM
–40°to + 105°C
–40°to + 125°C
$DF
$DF
EPROM
EPROM
Frequency
MC Order Number
2 MHz
MC68HC711K4CFS2
3 MHz
MC68HC711K4CFS3
4 MHz
MC68HC711K4CFS4
2 MHz
MC68HC711K4VFS2
3 MHz
MC68HC711K4VFS3
4 MHz
MC68HC711K4VFS4
2 MHz
MC68HC711K4MFS2
3 MHz
MC68HC711K4MFS3
4 MHz
MC68HC711K4MFS4
Freescale Semiconductor, Inc...
Table 2 Extended Voltage (3.0 Vdc to 5.5 Vdc) Device Ordering Information
Package
Temperature
Description
Frequency
MC Order Number
84-Pin PLCC
–20°to + 70°C
Custom ROM
1 MHz
MC68L11K4FN1
3 MHz
MC68L11K4FN3
1 MHz
MC68L11K1FN1
3 MHz
MC68L11K1FN3
1 MHz
MC68L11K0FN1
3 MHz
MC68L11K0FN3
1 MHz
MC68L11K3FN1
3 MHz
MC68L11K3FN3
1 MHz
MC68L11K4FU1
3 MHz
MC68L11K4FU3
1 MHz
MC68L11K1FU1
3 MHz
MC68L11K1FU3
1 MHz
MC68L11K0FU1
3 MHz
MC68L11K0FU3
1 MHz
MC68L11K3FU1
3 MHz
MC68L11K3FU3
No ROM
No ROM, No EEPROM
Custom ROM, No EEPROM
80-Pin QFP
–20°to + 70°C
Custom ROM
No ROM
No ROM, No EEPROM
Custom ROM, No EEPROM
M68HC11 K Series
MC68HC11KTS/D
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Table 3 Custom ROM Device Ordering Information
Package
Temperature
Description
Frequency
MC Order Number
84-Pin PLCC
–40°to + 85°C
Custom ROM
2 MHz
MC68HC11K4CFN2
3 MHz
MC68HC11K4CFN3
4 MHz
MC68HC11K4CFN4
–40°to + 105°C
–40°to + 125°C
Freescale Semiconductor, Inc...
–40°to + 85°C
–40°to + 105°C
–40°to + 125°C
80-Pin QFP
–40°to + 85°C
–40°to + 105°C
–40°to + 85°C
–40°to + 105°C
MOTOROLA
4
Custom ROM
Custom ROM
Custom ROM, No EEPROM
Custom ROM, No EEPROM
Custom ROM, No EEPROM
Custom ROM
Custom ROM
Custom ROM, No EEPROM
Custom ROM, No EEPROM
2 MHz
MC68HC11K4VFN2
3 MHz
MC68HC11K4VFN3
4 MHz
MC68HC11K4VFN4
2 MHz
MC68HC11K4MFN2
3 MHz
MC68HC11K4MFN3
4 MHz
MC68HC11K4MFN4
2 MHz
MC68HC11K3CFN2
3 MHz
MC68HC11K3CFN3
4 MHz
MC68HC11K3CFN4
2 MHz
MC68HC11K3VFN2
3 MHz
MC68HC11K3VFN3
4 MHz
MC68HC11K3VFN4
2 MHz
MC68HC11K3MFN2
3 MHz
MC68HC11K3MFN3
4 MHz
MC68HC11K3MFN4
2 MHz
MC68HC11K4CFU2
3 MHz
MC68HC11K4CFU3
4 MHz
MC68HC11K4CFU4
2 MHz
MC68HC11K4VFU2
3 MHz
MC68HC11K4VFU3
4 MHz
MC68HC11K4VFU4
2 MHz
MC68HC11K3CFU2
3 MHz
MC68HC11K3CFU3
4 MHz
MC68HC11K3CFU4
2 MHz
MC68HC11K3VFU2
3 MHz
MC68HC11K3VFU3
4 MHz
MC68HC11K3VFU4
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M68HC11 K Series
MC68HC11KTS/D
PH0/PW1
PH1/PW2
PH2/PW3
PH3/PW4
PH4/CSIO
PH5/CSGP1
PH6/CSGP2
PH7/CSPROG
TEST161
XIRQ/VPPE2
TEST151
VDD
VSS
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
PD5/SS
PD4/SCK
PD3/MOSI
84
83
82
81
80
79
78
77
76
75
1
MC68HC11K SERIES
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
PD2/MISO
PD1/TxD
PD0/RxD
MODA/LIR
MODB/VSTBY
RESET
XTAL
EXTAL
XOUT
E
VDD
VSS
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
PC0/DATA0
IRQ
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0
PE7/AN7
PE6/AN6
PE5/AN5
PE4/AN4
PE3/AN3
PE2/AN2
PE1/AN1
PE0/AN0
VRL
VRH
AVSS
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
TEST141
PG7/R/W
PG6
PG5/XA18
PG4/XA17
PG3/XA16
PG2/XA15
PG1/XA14
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PG0/XA13
AVDD
Freescale Semiconductor, Inc...
11
10
9
8
7
6
5
4
3
2
PB0/ADDR8
PB1/ADDR9
PB2/ADDR10
PB3/ADDR11
PB4/ADDR12
PB5/ADDR13
PB6/ADDR14
PB7/ADDR15
VSS
VDD
Freescale Semiconductor, Inc.
1. Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry.
2. VPPE applies only to devices with EPROM.
Figure 1 Pin Assignments for 84-Pin PLCC/CLCC
M68HC11 K Series
MC68HC11KTS/D
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5
PD3/MOSI
PD4/SCK
PD5/SS
PA7/PAI/OC1
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
PA2/IC1
PA1/IC2
PA0/IC3
VDD
VSS
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
PC0/DATA0
IRQ
MC68HC11K SERIES
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PF0/ADDR0
PF1/ADDR1
PF2/ADDR2
PF3/ADDR3
PF4/ADDR4
PF5/ADDR5
PF6/ADDR6
PF7/ADDR7
AVSS
VRH
VRL
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
PE4/AN4
PE5/AN5
PE6/AN6
PE7/AN7
AVDD
PG7/R/W
PG6
PG5/XA18
PG4/XA17
PG3/XA16
PG2/XA15
PG1/XA14
PG0/XA13
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PB0/ADDR8
PH0/PW1
PH1/PW2
PH2/PW3
PH3/PW4
PH4/CSIO
PH5/CSGP1
PH6/CSGP2
PH7/CSPROG
XIRQ
VDD
VSS
Freescale Semiconductor, Inc...
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD2/MISO
PD1/TxD
PD0/RxD
MODA/LIR
MODB/VSTBY
RESET
XTAL
EXTAL
E
VDD
VSS
Freescale Semiconductor, Inc.
Figure 2 Pin Assignments for 80-Pin 14 mm X 14 mm TQFP
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
XTAL
EXTAL
IRQ
XIRQ/VPPE
RESET
INTERRUPT
LOGIC
OSCILLATOR
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
TIMER
SYSTEM
PERIODIC
INTERRUPT
CPU
768
BYTES
RAM
0
KBYTES
ROM/
EPROM
(K0, K1)
CSPROG
CSGP2
CSGP1
CSIO
640
BYTES
EEPROM
(K1, K4)
0
KBYTES
EEPROM
(K0, K3)
PW4
PW3
PWM PW2
PW1
SS
SCK
SPI
MOSI
MISO
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
R/W
DATA BUS
SCI
TxD
RxD
MEMORY
EXPANSION
XA18
XA17
XA16
XA15
XA14
XA13
VRH
VRL
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
AVDD
AVSS
VDD
VSS
CHIP
SELECTS
24
KBYTES
ROM/
EPROM
(K3, K4)
ADDRESS BUS
PORT A
PORT A DDR
PORT B
PORT B DDR
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
OC2/OC1
OC3/OC1
OC4/OC1
OC5/IC4/OC1
IC1
IC2
IC3
PORT F
PORT F DDR
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORT C
PORT C DDR
Freescale Semiconductor, Inc...
PA6
PA5
PA4
PA3
PA2
PA1
PA0
COP
PORT H DDR
PORT H
PULSE
PAI/OC1 ACCUMULATOR
PA7
CLOCK
LOGIC
PORT D DDR
PORT D
MODE
CONTROL
MODB/
VSTBY
A/D
CONVERTER
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PORT G DDR
PORT G
MODA/
LIR
PORT E
E
*XOUT
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PD5
PD4
PD3
PD2
PD1
PD0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
*XOUT pin omitted on 80-pin QFP.
Figure 3 M68HC11 K-Series Block Diagram
M68HC11 K Series
MC68HC11KTS/D
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TABLE OF CONTENTS
Section
1
2
Features
Operating Modes
2.1
2.2
2.3
2.4
2.5
3
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Page
3.1
3.2
3.3
3.4
3.5
3.6
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
5
6
7
8
9
10
1
11
Single-Chip Operating Mode .....................................................................................................11
Expanded Operating Mode .......................................................................................................11
Bootstrap Mode .........................................................................................................................11
Special Test Mode .....................................................................................................................11
Mode Selection ..........................................................................................................................11
On-Chip Memory
14
Memory Map and Register Block ..............................................................................................14
RAM ..........................................................................................................................................17
ROM/EPROM ............................................................................................................................18
EEPROM ...................................................................................................................................22
Configuration Control Register (CONFIG) .................................................................................24
Security Feature ........................................................................................................................25
Memory Expansion and Chip Selects
27
Memory Expansion ....................................................................................................................27
Overlap Guidelines ....................................................................................................................30
Chip Selects ..............................................................................................................................30
Program Chip Select (CSPROG) ...................................................................................31
I/O Chip Select (CSIO) ...................................................................................................31
General-Purpose Chip Selects (CSGP1, CSGP2) .........................................................32
Chip Select Priorities ......................................................................................................32
Chip Select Control Registers ........................................................................................32
Examples of Memory Expansion Using Chip Selects .....................................................35
Resets and Interrupts
Parallel Input/Output
Serial Communications Interface
Serial Peripheral Interface
Analog-to-Digital Converter
Main Timer
10.1
11
12
12.1
38
42
49
56
60
64
Real-Time Interrupt ...................................................................................................................70
Pulse Accumulator
71
Pulse-Width Modulation Timer
74
PWM Boundary Cases ..............................................................................................................78
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
REGISTER INDEX
C
CFORC
CONFIG
COPRST
CSCSTR
CSCTL
Timer Compare Force
System Configuration Register
Arm/Reset COP Timer Circuitry
Chip Select Clock Stretch
Chip Select Control
DDRA
DDRB
DDRF
DDRG
DDRH
Data Direction Register for Port A
Data Direction Register for Port B
Data Direction Register for Port F
Data Direction Register for Port G
Data Direction Register for Port H
EPROG
EPROM Programming Control
GPCS1A
GPCS1C
GPCS2A
GPCS2C
General-Purpose Chip Select 1 Address
General-Purpose Chip Select 1 Control
General-Purpose Chip Select 2 Address
General-Purpose Chip Select 2 Control
HPRIO
Highest Priority I-Bit Interrupt and Miscellaneous
INIT
INIT2
RAM and Register Mapping
EEPROM Mapping
MMSIZ
MMWBR
Memory Mapping Size
Memory Mapping Window Base
OC1D
OC1M
OPT2
OPTION
Output Compare 1 Data
Output Compare 1 Mask
System Configuration Options 2
System Configuration Options
PACNT
PACTL
PGAR
PORTA
PORTB
PORTC
PORTE
PORTF
PORTG
PORTH
PPAR
PPROG
PWCLK
Pulse Accumulator Counter
Pulse Accumulator Control
Port G Assignment
Port A Data
Port B Data
Port C Data
Port E Data
Port F Data
Port G Data
Port H Data
Port Pull-Up Assignment
EEPROM Programming Control
Pulse-Width Modulation Clock Select
$000B
$003F
$003A
$005A
$005B
66
25
40
33
32
$0001
$0002
$0003
$007F
$007D
42
43
46
47
46
$002B
19
$005C
$005D
$005E
$005F
33
34
34
34
$003C
11, 40
$003D
$0037
18
24
$0056
$0057
28
29
$000D
$000C
$0038
$0039
66
66
12, 44, 59
39
$0027
$0026
$002D
$0000
$0004
$0006
$000A
$0005
$007E
$007C
$002C
$003B
$0060
73
73
28, 47
42
43
43
46
46
47
46
48
22
62, 76
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D
E
G
H
I
M
O
P
M68HC11 K Series
MC68HC11KTS/D
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PWCNT[4:1]
PWDTY[4:1]
PWEN
PWPER[4:1]
PWPOL
PWSCAL
Pulse-Width Modulation Timer Counter 1 to 4
Pulse-Width Modulation Timer Duty Cycle 1 to 4
Pulse-Width Modulation Timer Enable
Pulse-Width Modulation Timer Period 1 to 4
Pulse-Width Modulation Timer Polarity
Pulse-Width Modulation Timer Prescaler
SCBDH/L
SCCR1
SCCR2
SCSR1
SCSR2
SPCR
SPCR
SPDR
SPSR
SCI Baud Rate Control High/Low
SCI Control 1
SCI Control 2
SCI Status Register 1
SCI Status Register 2
Serial Peripheral Control
Serial Peripheral Control Register
SPI Data
Serial Peripheral Status Register
TCNT
TCTL2
TFLG2
TI4/O5
TMSK1
TMSK2
TOC1–TOC4
Timer Count
Timer Control 2
Timer Interrupt Flag 2
Timer Input Capture 4/Output Compare 5
Timer Interrupt Mask 1
Timer Interrupt Mask 2
Timer Output Compare
$0064–$0067
$006C–$006F
$0063
$0068–$006B
$0061
$0062
77
78
77
78
62, 76
63, 77
$0070, $0071
$0072
$0073
$0074
$0075
$0028
$0028
$002A
$0029
52
45, 52
53
54
55
45
57
58
58
$000E, $000F
$0021
$0025
$001E–$001F
$0022
$0024
$0016–$001D
66
67
69, 72
67
68
68, 72
67
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S
T
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
2 Operating Modes
The M68HC11 K-series MCUs have four modes of operation that directly affect the address space.
These modes are described as follows.
2.1 Single-Chip Operating Mode
In single-chip operating mode, the M68HC11 K-series MCUs are stand-alone microcontrollers with no
external address or data bus. Addressing range is 64 Kbytes and is limited to on-chip resources. Refer
to the memory map diagram.
Freescale Semiconductor, Inc...
2.2 Expanded Operating Mode
In expanded operating mode, the MCU has a 64 Kbyte address range and, using the expansion bus,
can access external resources within the 64 Kbyte space. This space includes the same on-chip memory addresses used for single-chip mode, in addition to addressing capabilities for external peripheral
and memory devices. Addressing beyond 64 Kbytes is available only in expanded mode using the onchip, register-based memory mapping logic. The additional address lines for memory expansion
(XA[18:13]) are implemented as alternate functions of port G. The expansion bus (external address and
data buses) is made up of ports B, C, and F, and the R/W signal. In expanded operating mode, high
order address bits are output on the port B pins, low order address bits on the port F pins, and the data
bus on port C. Refer to the memory map diagram.
2.3 Bootstrap Mode
Bootstrap mode allows special-purpose programs to be loaded into internal RAM. The MCU contains
448 bytes of bootstrap ROM which is enabled and present in the memory map only when the device is
in bootstrap mode. The bootstrap ROM contains a program which initializes the SCI and allows the user
to download up to 768 bytes of code into on-chip RAM. After a four-character delay, or after receiving
the character for address $037F, control passes to the loaded program at $0080. Refer to the memory
map diagram. Refer also to Application Note M68HC11 Bootstrap Mode (AN1060/D).
2.4 Special Test Mode
Special test mode is used primarily for factory testing. In this operating mode, ROM/EPROM is removed
from the address space and interrupt vectors are accessed externally at $BFC0–$BFFF.
2.5 Mode Selection
Operating modes are selected by a combination of logic levels applied to two input pins (MODA and
MODB) during reset. The logic level present (at the rising edge of reset) on these inputs is reflected in
bits in the HPRIO register. After reset, the operating mode may be changed according to the table contained in the description of the HPRIO register.
The functions of two features that are enabled by bits in OPT2 register are dependent upon the operating mode. LIR driven is enabled with the LIRDV bit. Internal read visibility/not E is enabled with the
IRVNE bit. Refer to the OPT2 register description that follows HPRIO.
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
Bit 7
6
RBOOT* SMOD*
RESET:
5
4
3
MDA*
PSEL4
PSEL3
$003C
2
1
Bit 0
PSEL2 PSEL1 PSEL0
0
0
0
0
0
1
1
0
Single Chip
0
0
1
0
0
1
1
0
Expanded
1
1
0
0
0
1
1
0
Bootstrap
0
1
1
0
0
1
1
0
Special Test
*The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up.
M68HC11 K Series
MC68HC11KTS/D
For More Information On This Product,
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MOTOROLA
11
Freescale Semiconductor, Inc.
RBOOT — Read Bootstrap ROM/EPROM
Valid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes.
0 = Bootstrap ROM disabled and not in map
1 = Bootstrap ROM enabled and in map at $BE00–$BFFF
SMOD and MDA —Special Mode Select and Mode Select A
These two bits can be read at any time. They can be written anytime in special modes. MDA can only
be written once in normal modes. SMOD cannot be set once it has been cleared.
Freescale Semiconductor, Inc...
Inputs
MODB
MODA
1
0
1
1
0
0
0
1
Latched at Reset
SMOD
MDA
0
0
0
1
1
0
1
1
Mode
Single Chip
Expanded
Bootstrap
Special Test
PSEL[4:0] —Priority Select Bits [4:0]
Refer to 5 Resets and Interrupts.
OPT2 — System Configuration Options 2
$0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
—
IRVNE*
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
RESET:
*Can be written only once in normal modes. Can be written anytime in special modes.
LIRDV —LIR Driven
In single-chip and bootstrap modes, this bit has no meaning or effect. The LIR pin is normally configured
for wired-OR operation (only pulls low). In order to detect consecutive instructions in a high-speed application, this signal can be made to drive high for a short time to prevent false triggering.
0 = LIR not driven high out of reset
1 = LIR driven high for one quarter cycle to reduce transition time
CWOM —Port C Wired-OR Mode
Refer to 6 Parallel Input/Output.
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
IRVNE can be written only once in normal modes (SMOD = 0). In special modes IRVNE can be written
any time. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero.
In expanded modes this bit determines whether IRV is on or off.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
In single-chip modes this bit determines whether the E clock drives out from the chip.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Mode
Single Chip
Expanded
Boot
Special Test
MOTOROLA
12
IRVNE Out
of Reset
0
0
0
1
E Clock Out
of Reset
On
On
On
On
IRV Out of
Reset
Off
Off
Off
On
IRVNE
Affects Only
E
IRV
E
IRV
For More Information On This Product,
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IRVNE Can
Be Written
Once
Once
Anytime
Anytime
M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
LSBF —LSB First Enable
Refer to 8 Serial Peripheral Interface.
SPR2 —SPI Clock Rate Select
Refer to 8 Serial Peripheral Interface.
XDV[1:0] —XOUT Clock Divide Select
Controls the frequency of the clock driven out of the XOUT pin
XOUT = EXTAL
Divided By
1
4
6
8
Frequency at
EXTAL = 8 MHz
8 MHz
2 MHz
1.3 MHz
1 MHz
Frequency at
EXTAL = 12 MHz
12 MHz
3 MHz
2 MHz
1.5 MHz
Frequency at
EXTAL = 16 MHz
16 MHz
4 MHz
2.7 MHz
2 MHz
Freescale Semiconductor, Inc...
XDV
[1:0]
00
01
10
11
M68HC11 K Series
MC68HC11KTS/D
For More Information On This Product,
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MOTOROLA
13
Freescale Semiconductor, Inc.
3 On-Chip Memory
In general, K-series MCUs have 768 bytes RAM, 640 bytes EEPROM, and 24 Kbytes ROM/EPROM.
Some devices in the series have portions of their memory resources disabled. Some have ROM and
some have EPROM replacing ROM. The following paragraphs describe the memory systems of devices
in the series.
3.1 Memory Map and Register Block
The INIT, INIT2, and CONFIG registers control the presence and location of the registers, RAM, EEPROM, and ROM/EPROM in the 64 Kbyte CPU address space. The 128-byte register block originates
at $0000 after reset and can be placed at any 4 Kbyte boundary ($x000) after reset by writing an appropriate value to the INIT register. Refer to Figure 4.
Freescale Semiconductor, Inc...
$0000
x000
x07F
x080
EXT
EXT
x37F
$1000
EXT
xD00
xD7F
xD80
EXT
xFFF
$A000
A000
128-BYTE REGISTER BLOCK
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT REGISTER)
768 BYTES RAM
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT REGISTER)
RESERVED (SPECIAL TEST MODE ONLY)
640 BYTES EEPROM
(CAN BE REMAPPED TO ANY
4K PAGE BY THE INIT2 REGISTER)
BOOT ROM
BE00 (ONLY PRESENT IN
BOOTSTRAP MODE)
SPECIAL MODE
INTERRUPT
VECTORS
BFC0
BFFF
$FFFF
FFFF
SINGLE
CHIP
EXPANDED
BOOTSTRAP
24 KBYTES ROM/EPROM
(CAN BE REMAPPED TO $2000–$7FFF OR
$A000–$FFFF BY THE CONFIG REGISTER)
FFC0 NORMAL MODE
INTERRUPT
FFFF VECTORS
SPECIAL
TEST
NOTE: ROM/EPROM can be enabled in special test mode by setting ROMON bit in the config register after reset.
Figure 4 Memory Map
MOTOROLA
14
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M68HC11 K Series
MC6HC11KTS/D
Freescale Semiconductor, Inc.
INIT = $00
INIT = $10
INIT = $04
REG @ $0000
RAM @ $0080
REG @ $0000
RAM @ $1000
REG @ $4000
RAM @ $0000
$0000
$0000
$0000
REGISTER
BLOCK
REGISTER
BLOCK
RAM
A
$007F
$007F
$007F
$0080
$0080
$1000
RAM
A
RAM
B
RAM
B
Freescale Semiconductor, Inc...
$107F
$1080
$02FF
$02FF
$0300
RAM
B
RAM
A
$037F
$4000
REGISTER
BLOCK
$407F
$12FF
Figure 5 RAM and Register Mapping
Table 4 M68HC11 K Series Register and Control Bit Assignments
(Can be remapped to any 4-Kbyte boundary)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
Bit 7
PA7
DDA7
DDB7
DDF7
PB7
PF7
PC7
DDC7
0
0
PE7
FOC1
OC1M7
OC1D7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
M68HC11 K Series
MC6HC11KTS/D
6
PA6
DDA6
DDB6
DDF6
PB6
PF6
PC6
DDC6
0
0
PE6
FOC2
OC1M6
OC1D6
14
6
14
6
14
6
14
5
PA5
DDA5
DDB5
DDF5
PB5
PF5
PC5
DDC5
PD5
DDD5
PE5
FOC3
OC1M5
OC1D5
13
5
13
5
13
5
13
4
PA4
DDA4
DDB4
DDF4
PB4
PF4
PC4
DDC4
PD4
DDD4
PE4
FOC4
OC1M4
OC1D4
12
4
12
4
12
4
12
3
PA3
DDA3
DDB3
DDF3
PB3
PF3
PC3
DDC3
PD3
DDD3
PE3
FOC5
OC1M3
OC1D3
11
3
11
3
11
3
11
2
PA2
DDA2
DDB2
DDF2
PB2
PF2
PC2
DDC2
PD2
DDD2
PE2
0
0
0
10
2
10
2
10
2
10
1
PA1
DDA1
DDB1
DDF1
PB1
PF1
PC1
DDC1
PD1
DDD1
PE1
0
0
0
9
1
9
1
9
1
9
For More Information On This Product,
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Bit 0
PA0
DDA0
DDB0
DDF0
PB0
PF0
PC0
DDC0
PD0
DDD0
PE0
0
0
0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
PORTA
DDRA
DDRB
DDRF
PORTB
PORTF
PORTC
DDRC
PORTD
DDRD
PORTE
CFORC
OC1M
OC1D
TCNT (High)
TCNT (Low)
TIC1 (High)
TIC1 (Low)
TIC2 (High)
TIC2 (Low)
TIC3 (High)
MOTOROLA
15
Freescale Semiconductor, Inc.
Table 4 M68HC11 K Series Register and Control Bit Assignments (Continued)
Freescale Semiconductor, Inc...
(Can be remapped to any 4-Kbyte boundary)
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
$0040
to
$0055
$0056
$0057
Bit 7
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
Bit 15
Bit 7
OM2
EDG4B
OC1I
OC1F
TOI
TOF
0
Bit 7
SPIE
SPIF
Bit 7
MBE
0
0
6
6
14
6
14
6
14
6
14
6
14
6
OL2
EDG4A
OC2I
OC2F
RTII
RTIF
PAEN
6
SPE
WCOL
6
0
0
0
5
5
13
5
13
5
13
5
13
5
13
5
OM3
EDG1B
OC3I
OC3F
PAOVI
PAOVF
PAMOD
5
DWOM
0
5
ELAT
0
PGAR5
4
4
12
4
12
4
12
4
12
4
12
4
OL3
EDG1A
OC4I
OC4F
PAII
PAIF
PEDGE
4
MSTR
MODF
4
EXCOL
0
PGAR4
3
3
11
3
11
3
11
3
11
3
11
3
OM4
EDG2B
I4/O5I
I4/O5F
0
0
0
3
CPOL
0
3
EXROW
HPPUE
PGAR3
2
2
10
2
10
2
10
2
10
2
10
2
OL4
EDG2A
IC1I
IC1F
0
0
I4/O5
2
CPHA
0
2
T1
GPPUE
PGAR2
1
1
9
1
9
1
9
1
9
1
9
1
OM5
EDG3B
IC2I
IC2F
PR1
0
RTR1
1
SPR1
0
1
T0
FPPUE
PGAR1
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
OL5
EDG3A
IC3I
IC3F
PR0
0
RTR0
Bit 0
SPR0
Bit 0
Bit 0
EPGM
BPPUE
PGAR0
CCF
Bit 7
Bit 7
Bit 7
Bit 7
BULKP
0
6
6
6
6
LVPEN
SCAN
5
5
5
5
BPRT4
MULT
4
4
4
4
PTCON
CD
3
3
3
3
BPRT3
CC
2
2
2
2
BPRT2
CB
1
1
1
1
BPRT1
CA
Bit 0
Bit 0
Bit 0
Bit 0
BPRT0
EE3
LIRDV
ADPU
Bit 7
ODD
RBOOT
RAM3
TILOP
ROMAD
EE2
CWOM
CSEL
6
EVEN
SMOD
RAM2
0
1
EE1
0
IRQE
5
LVPI
MDA
RAM1
OCCR
CLKX
EE0
IRVNE
DLY
4
BYTE
PSEL4
RAM0
CBYP
PAREN
0
LSBF
CME
3
ROW
PSEL3
REG3
DISR
NOSEC
0
SPR2
FCME
2
ERASE
PSEL2
REG2
FCM
NOCOP
0
XDV1
CR1
1
EELAT
PSEL1
REG1
FCOP
ROMON
0
XDV0
CR0
Bit 0
EEPGM
PSEL0
REG0
0
EEON
MXGS2
W2A15
MXGS1
W2A14
W2SZ1
W2A13
W2SZ0
0
0
W1A15
0
W1A14
W1SZ1
W1A13
W1SZ0
0
MOTOROLA
16
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TIC3 (Low)
TOC1(High)
TOC1 (Low)
TOC2 (High)
TOC2 (Low)
TOC3 (High)
TOC3 (Low)
TOC4 (High)
TOC4 (Low)
TI4/O5 (High)
TI4/O5 (Low)
TCTL1
TCTL2
TMSK1
TFLG1
TMSK2
TFLG2
PACTL
PACNT
SPCR
SPSR
SPDR
EPROG*
PPAR
PGAR
Reserved
Reserved
ADCTL
ADR1
ADR2
ADR3
ADR4
BPROT
Reserved
INIT2
OPT2
OPTION
COPRST
PPROG
HPRIO
INIT
TEST1
CONFIG
Reserved
Reserved
MMSIZ
MMWBR
M68HC11 K Series
MC6HC11KTS/D
Freescale Semiconductor, Inc.
Table 4 M68HC11 K Series Register and Control Bit Assignments (Continued)
Freescale Semiconductor, Inc...
(Can be remapped to any 4-Kbyte boundary)
$0058
$0059
$005A
$005B
$005C
$005D
$005E
$005F
$0060
$0061
$0062
$0063
$0064
$0065
$0066
$0067
$0068
$0069
$006A
$006B
$006C
$006D
$006E
$006F
$0070
$0071
$0072
$0073
$0074
$0075
$0076
$0077
$0078
to
$007B
$007C
$007D
$007E
$007F
Bit 7
0
0
IOSA
IOEN
G1A18
G1DG2
G2A18
0
CON34
PCLK4
Bit 7
TPWSL
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
BTST
SBR7
LOOPS
TIE
TDRE
0
R8
R7/T7
6
X1A18
X2A18
IOSB
IOPL
G1A17
G1DPC
G2A17
G2DPC
CON12
PCLK3
6
DISCP
6
6
6
6
6
6
6
6
6
6
6
6
BSPL
SBR6
WOMS
TCIE
TC
0
T8
R6/T6
5
X1A17
X2A17
GP1SA
IOCSA
G1A16
G1POL
G2A16
G2POL
PCKA2
PCLK2
5
0
5
5
5
5
5
5
5
5
5
5
5
5
0
SBR5
0
RIE
RDRF
0
0
R5/T5
4
X1A16
X2A16
GP1SB
IOSZ
G1A15
G1AV
G2A15
G2AV
PCKA1
PCLK1
4
0
4
4
4
4
4
4
4
4
4
4
4
4
SBR12
SBR4
M
ILIE
IDLE
0
0
R4/T4
3
X1A15
X2A15
GP2SA
GCSPR
G1A14
G1SZA
G2A14
G2SZA
0
PPOL4
3
PWEN4
3
3
3
3
3
3
3
3
3
3
3
3
SBR11
SBR3
WAKE
TE
OR
0
0
R3/T3
2
X1A14
X2A14
GP2SB
PCSEN
G1A13
G1SZB
G2A13
G2SZB
PCKB3
PPOL3
2
PWEN3
2
2
2
2
2
2
2
2
2
2
2
2
SBR10
SBR2
ILT
RE
NF
0
0
R2/T2
1
X1A13
X2A13
PCSA
PCSZA
G1A12
G1SZC
G2A12
G2SZC
PCKB2
PPOL2
1
PWEN2
1
1
1
1
1
1
1
1
1
1
1
1
SBR9
SBR1
PE
RWU
FE
0
0
R1/T1
Bit 0
0
0
PCSB
PCSZB
G1A11
G1SZD
G2A11
G2SZD
PCKB1
PPOL1
Bit 0
PWEN1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
SBR8
SBR0
PT
SBK
PF
RAF
0
R0/T0
PH7
DDH7
PG7
DDG7
PH6
DDH6
PG6
DDG6
PH5
DDH5
PG5
DDG5
PH4
DDH4
PG4
DDG4
PH3
DDH3
PG3
DDG3
PH2
DDH2
PG2
DDG2
PH1
DDH1
PG1
DDG1
PH0
DDH0
PG0
DDG0
MM1CR
MM2CR
CSCSTR
CSCTL
GPCS1A
GPCS1C
GPCS2A
GPCS2C
PWCLK
PWPOL
PWSCAL
PWEN
PWCNT1
PWCNT2
PWCNT3
PWCNT4
PWPER1
PWPER2
PWPER3
PWPER4
PWDTY1
PWDTY2
PWDTY3
PWDTY4
SCBDH
SCBDL
SCCR1
SCCR2
SCSR1
SCSR2
SCDRH
SCDRL
Reserved
Reserved
PORTH
DDRH
PORTG
DDRG
*MC68HC711K4 only.
3.2 RAM
All members of the M68HC11 K series have 768 bytes of static RAM. The RAM can be mapped to any
4-Kbyte boundary. Upon reset, the RAM is mapped at $0080–$037F. The registers are also mapped to
this 4-Kbyte boundary. In previous versions of the M68HC11 devices the register block being mapped
to the same boundary would cause the portion of RAM overlapped by the register block to be lost. However, a new RAM remapping feature has been added which automatically allows all of the RAM to be
accessible even if the register block overlaps the RAM. Because the registers are located in the same
M68HC11 K Series
MC6HC11KTS/D
For More Information On This Product,
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MOTOROLA
17
Freescale Semiconductor, Inc.
4-Kbyte boundary after reset, 128 bytes of the RAM are located at $0300 to $037F. Remapping is accomplished by writing appropriate values to the INIT register. Refer to the register and RAM mapping
examples following the memory map diagram.
When power is removed from the MCU, RAM contents may be preserved using the MODB/VSTBY pin.
A power source (2.0 Vdc –VDD) applied to this pin protects all 768 bytes of RAM.
INIT — RAM and Register Mapping
RESET:
$003D
Bit 7
6
5
4
3
2
1
Bit 0
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc...
Can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode.
RAM[3:0] —Internal RAM Map Position
These bits determine the upper four bits of the RAM address. At reset RAM is mapped to $0000. Normally the RAM would be mapped at $0000–$02FF (768 bytes). However, the register block overlaps
the first 128 bytes of RAM, causing them to be remapped to $0300–$037F. Refer to Figure 4 and Figure 5.
REG[3:0] —128-Byte Register Block Map Position
These bits determine the upper four bits of the register block starting address. At reset registers are
mapped to $0000 and overlap the first 128 bytes of RAM, causing them to be remapped to $0300–
$037F. Refer to Figure 4 and Figure 5.
3.3 ROM/EPROM
Standard devices have 24 kbytes of EPROM (OTPROM in a non-windowed package). Custom ROM
devices have a 24-Kbyte ROM array that is mask programmed at the factory to customer specifications.
The MC68HC11K0, MC68HC11K1, MC68L11K0, and MC68L11K1 have no ROM/EPROM. Refer to
the ordering information tables.
The ROMAD and ROMON control bits in the CONFIG register control the position and presence of
ROM/EPROM in the memory map. The ROM/EPROM can be mapped at $2000–$7FFF or $A000–
$FFFF. If it is mapped to $A000–$FFFF, vector space is included. In single-chip mode the ROM/
EPROM is forced to $A000–$FFFF (ROMAD = 1) and enabled (ROMON = 1), regardless of the value
in the CONFIG register. This ensures that there will be ROM/EPROM at the vector space. In special
test mode, the ROMON bit is forced to zero so that the ROM/EPROM is removed from the memory map.
Refer to Figure 4.
Programming EPROM requires an external 12.25 volt nominal power supply (VPPE) that must be applied to the XIRQ/VPPE pin. Three methods are used to program and verify EPROM/OTPROM.
Normal EPROM/OTPROM programming can be accomplished in any operating mode. Normal programming is accomplished using the EPROM/OTPROM programming register (EPROG). The EPROG
register enables the EPROM programming voltage, controls the latching of data to be programmed, and
selects single- or multiple-byte programming.
To program the EPROM, complete the following steps using the EPROG register:
1. Set the ELAT bit in EPROG register. EELAT bit in PPROG must be cleared as it negates the
function of the ELAT bit.
2. Write data to the desired address.
3. Turn on programming voltage to the EPROM array by setting the EPGM bit in EPROG register.
4. Delay for 2 ms or more, as appropriate.
5. Clear the EPGM bit in EPROG to turn off the programming voltage.
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6. Clear the EPROG register to reconfigure the EPROM address and data buses for normal operation.
In EPROM emulation mode (PROG mode), the EPROM/OTPROM is programmed as a stand-alone
EPROM by adapting the MCU footprint to the 27C256-type EPROM and using an appropriate EPROM
programmer. To put the MCU in PROG mode, pull the following pins low: MODA/LIR, MODB/VSTBY,
RESET, PA[2:0]. Refer to Figure 6.
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In the third method, the EPROM is programmed by software while in the special test or bootstrap
modes. User-developed software can be uploaded through the SCI, or a ROM resident EPROM programming utility can be used. To use the resident utility, bootload a three-byte program consisting of a
single jump instruction to $BF00. $BF00 is the starting address of a resident EPROM programming utility. The utility program sets the X and Y index registers to default values, then receives programming
data from an external host and programs it into EPROM. The value in IX determines programming delay
time. The value in IY is a pointer to the first address in EPROM to be programmed (default = $A000).
When the utility program is ready to receive programming data, it sends the host the $FF character.
Then it waits. When the host sees the $FF character, the EPROM programming data is sent, starting
with the first location in the EPROM array. After the last byte to be programmed is sent and the corresponding verification data is returned, the programming operation is terminated by resetting the MCU.
Although the external 12.25 V programming voltage must be applied to the XIRQ/VPPE pin during
EPROM programming, it should be equal to VDD before verifying the data that was just programmed. It
should equal VDD during normal operation also. The XIRQ/VPPE pin has a high voltage detect circuit
that inhibits assertion of the ELAT bit when programming voltage is at low levels.
CAUTION
If the MCU is used in any operating mode while high voltage (12.25 V nominal) is
present on the XIRQ/VPPE pin, the IRQ/CE pin must be pulled high to avoid accidental programming or corruption of EPROM contents. After programming an
EPROM location, IRQ pin must also be pulled high before the address and data
are changed to program the next location.
EPROG — EPROM Programming Control
RESET:
$002B
Bit 7
6
5
4
3
2
1
Bit 0
MBE
—
ELAT
EXCOL
EXROW
—
—
EPGM
0
0
0
0
0
0
0
0
MBE —Multiple-Byte Programming Enable
0 = EPROM array configured for normal programming
1 = Program two bytes with the same data
When multiple-byte programming is enabled, address bit 5 is considered a don't care so that bytes with
address bit 5 = 0 and address bit 5 = 1 both get programmed. MBE can be read in any mode and always
reads zero in normal modes. MBE can only be written in special modes.
Bit 6 —Not implemented
Always reads zero
ELAT —EPROM Latch Control
ELAT can be read any time. ELAT can be written any time except when EPGM = 1, then the write to
ELAT will be disabled. When ELAT = 1, writes to EPROM cause address and data to be latched and
the EPROM cannot be read.
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming
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EXCOL —Select Extra Columns
0 = User array selected
1 = User array is disabled and extra columns are accessed at bits [7:0]. Addresses use bits [11:5]
and bits [4:0] are don't care. EXCOL can only be read in special modes and always returns zero
in normal modes. EXCOL can be written in special modes only.
EXROW —Select Extra Rows
0 = User array selected
1 = User array is disabled and two extra rows are available. Addresses use bits [5:0] and bits [11:6]
are don't care. EXROW can only be read in special modes and always returns zero in normal
modes. EXROW can be written in special modes only.
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Bits [2:1] —Not implemented
Always read zero
EPGM —EPROM Programming Voltage Enable
EPGM can be read any time and can only be written when ELAT = 1.
0 = Programming voltage to EPROM array disconnected
1 = Programming voltage to EPROM array connected
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EPROM MODE PIN CONNECTIONS
MCU PIN FUNCTIONS
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EPROM
PIN FUNCTIONS
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
NOTE 4
NOTE 1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PF0/ADDR0
PF1/ADDR1
PF2/ADDR2
PF3/ADDR3
PF4/ADDR4
PF5/ADDR5
PF6/ADDR6
PF7/ADDR7
PB0/ADDR8
PB1/ADDR9
PB2/ADDR10
PB3/ADDR11
PB4/ADDR12
PB5/ADDR13
PB6/ADDR14
PA0/IC3
PA1/IC2
PA2/IC1
PA3/IC4/OC5/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
PG0/XA13
PG1/XA14
PG2/XA15
PG3/XA16
PG4/XA17
PG5/XA18
PG6
PG7/R/W
PD0/RxD
PD1/TxD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
INTERNAL
24 KBYTE
EPROM
MC68HC711K4
O0
O1
O2
O3
O4
O5
O6
O7
PC0/DATA0
PC1/DATA1
PC2/DATA2
PC3/DATA3
PC4/DATA4
PC5/DATA5
PC6/DATA6
PC7/DATA7
O0
O1
O2
O3
O4
O5
O6
O7
OE
CE
VPP
VCC
VSS
PB7/ADDR15
IRQ
XIRQ/VPPE
VDD
VSS
OE
CE
VPP
VCC
VSS
PE0/AN0
PE1/AN1
PE2/AN2
PE3/AN3
PE4/AN4
PE5/AN5
PE6/AN6
PE7/AN7
UNUSED
INPUTS
PH0/PW1
PH1/PW2
PH2/PW3
PH3/PW4
PH4/CSIO
PH5/CSGP1
PH6/CSGP2
PH7/CSPROG
GND
GND
GND
GND
GND
GND
GND
GND
VRL
VRH
EXTAL
GND
GND
GND
NOTE 2
NOTE 1
XTAL
UNUSED
XOUT
OUTPUTS
E
TESTxx (3)
NOTE 3
MODA/LIR
MODB/VSTBY
RESET
NOTE 4
GND
GND
GND
NOTES:
1. Unused Inputs – grounding is recommended.
2. Unused Inputs – these pins may be left unterminated.
3. Unused Outputs – these pins should be left unconnected.
4. Grounding these six pins configures the MC68HC711K4 for EPROM emulation mode.
Figure 6 Pin Assignments of the MC68HC711K4 MCU in PROG Mode
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3.4 EEPROM
The 640-byte EEPROM is initially located at $0D80 after reset, assuming EEPROM is enabled in the
memory map by the EEON bit in the CONFIG register. EEPROM can be placed at any 4-Kbyte boundary ($xD80) by writing appropriate values to the INIT2 register. Note that EEPROM can be mapped so
that it contains the vector space. Refer to Figure 4. The MC68HC11K0, MC68HC11K3, MC68L11K0,
and MC68L11K3 have no EEPROM. Refer to the ordering information tables.
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Programming and erasing the EEPROM is controlled by the PPROG register, and dependent upon the
block protect (BPROT) register value. An on-chip charge pump develops the high voltage required for
programming and erasing. When the frequency of the E clock is less than 1 MHz, select the internal
clock source to drive the EEPROM charge pump by writing one to the CSEL bit in the OPTION register.
The CONFIG register consists of a single EEPROM byte. Although the byte is not included in the 640byte EEPROM array, programming the CONFIG register requires the same procedure as any byte in
the array. The erased state of bits in the CONFIG register is logic one. Refer to the CONFIG register
description that follows this section.
The erased state of an EEPROM byte is $FF (all ones).
To erase the EEPROM, ensure that the proper bits of the BPROT register are cleared, then complete
the following steps using the PPROG register:
1. Set the ERASE, EELAT, and appropriate BYTE and ROW bits in PPROG register.
2. Write to the appropriate EEPROM address with any data. Row erase only requires a write to
any location in the row. Bulk erase is done by writing to any location in the array.
3. Set the ERASE, EELAT, EEPGM, and appropriate BYTE and ROW bits in PPROG register.
4. Delay for 10 ms or more, as appropriate.
5. Clear the EEPGM bit in PPROG to turn off the programming voltage.
6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal operation.
To program the EEPROM, ensure the proper bits of the BPROT register are cleared and use the
PPROG register to complete the following steps:
1.
2.
3.
4.
5.
6.
Set the EELAT bit in PPROG register.
Write data to the desired address.
Set EEPGM bit in PPROG.
Delay for 10 ms or more, as appropriate.
Clear the EEPGM bit in PPROG to turn off the programming voltage.
Clear the PPROG register to reconfigure the EEPROM address and data buses for normal operation.
CAUTION
Since it is possible to perform other operations while the EEPROM programming/
erase operation is in progress, it is common to start the operation and then return
to the main program until the 10 ms is completed. When the EELAT bit is set at the
beginning of a program/erase operation, the EEPROM is electronically removed
from the memory map; thus, it is not accessible during the program/erase cycle.
Care must be taken to ensure that EEPROM resources will not be needed by any
routines in the code during the 10 ms program/erase time.
PPROG —EEPROM Programming Control
RESET:
MOTOROLA
22
$003B
Bit 7
6
5
4
3
2
1
Bit 0
ODD
EVEN
LVPI
BYTE
ROW
ERASE
EELAT
EEPGM
0
0
0
0
0
0
0
0
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ODD —Program Odd Rows in Half of EEPROM (TEST)
EVEN —Program Even Rows in Half of EEPROM (TEST)
LVPI —Low Voltage Programming Inhibit
LVPI can be read at any time and writes to LVPI have no meaning nor effect. LVPI is set if LVPEN bit
in BPROT register equals one and the LVPI circuit detects that VDD has fallen below a safe operating
voltage. Once set, LVPI is cleared when VDD returns to a safe operating voltage or if LVPEN bit in
BPROT register is cleared. If LVPEN equals zero, then LVPI is always zero and has no meaning nor
effect.
0 = EEPROM programming enabled
1 = EEPROM programming disabled
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BYTE —Byte/Other EEPROM Erase Mode
0 = Row or bulk erase mode used
1 = Erase only one byte of EEPROM
ROW —Row/All EEPROM Erase Mode (only valid when BYTE = 0)
0 = All 640 bytes of EEPROM erased
1 = Erase only one 16-byte row of EEPROM
BYTE
0
0
1
1
ROW
0
1
0
1
Action
Bulk Erase (All 640 Bytes)
Row Erase (16 Bytes)
Byte Erase
Byte Erase
ERASE —Erase/Normal Control for EEPROM
0 = Normal read or program mode
1 = Erase mode
EELAT —EEPROM Latch Control
0 = EEPROM address and data bus configured for normal reads
1 = EEPROM address and data bus configured for programming or erasing
EEPGM —EEPROM Program Command
0 = Program or erase voltage switched off to EEPROM array
1 = Program or erase voltage switched on to EEPROM array
BPROT — Block Protect
RESET:
$0035
Bit 7
6
5
4
3
2
1
Bit 0
BULKP
LVPEN
BPRT4
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
1
1
1
1
1
1
1
1
NOTE
Block protect register bits can be written to zero (protection disabled) only once
within 64 cycles of a reset in normal modes, or at any time in special modes. Block
protect register bits can be written to one (protection enabled) at any time.
BULKP —Bulk Erase of EEPROM Protect
0 = EEPROM can be bulk erased normally
1 = EEPROM cannot be bulk or row erased
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LVPEN —Low Voltage Programming Protect Enable
If LVPEN = 1, programming of the EEPROM is enabled unless the LVPI circuit detects that VDD has
fallen below a safe operating voltage, thus setting the low voltage programming inhibit bit in PPROG
register (LVPI = 1).
0 = Low voltage programming protect for EEPROM disabled
1 = Low voltage programming protect for EEPROM enabled
BPRT4 —Block Protect Bit for Upper 128 Bytes of EEPROM
Refer to description for BPRT[3:0].
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PTCON —Protect for CONFIG
0 = CONFIG register can be programmed or erased normally
1 = CONFIG register cannot be programmed or erased
BPRT[3:0] —Block Protect Bits for EEPROM
0 = Protection disabled
1 = Protection enabled
Bit Name
BPRT4
BPRT3
BPRT2
BPRT1
BPRT0
Block Protected
$xF80–$xFFF
$xE60–$xF7F
$xDE0–$xE5F
$xDA0–$xDDF
$xD80–$xD9F
Block Size
128 Bytes
288 Bytes
128 Bytes
64 Bytes
32 Bytes
INIT2 —EEPROM Mapping
RESET:
$0037
Bit 7
6
5
4
3
2
1
Bit 0
EE3
EE2
EE1
EE0
0
0
0
0
0
0
0
0
0
0
0
0
INIT2 can be written only once in normal modes, any time in special modes.
EE[3:0] —EEPROM Map Position
EEPROM is at $xD80–$xFFF, where x is the hexadecimal digit represented by EE[3:0].
Bits [3:0] —Not implemented
Always read zero
3.5 Configuration Control Register (CONFIG)
The CONFIG register is used to define several system functions. Although the CONFIG register is an
address within the register block, it is actually an EEPROM byte with the address of $x03F. CONFIG is
made up of EEPROM cells and static latches. The operation of the MCU is controlled directly by these
latches and not the actual EEPROM byte. When programming the CONFIG register, the EEPROM byte
is being accessed. When the CONFIG register is being read, the static latches are being accessed.
The CONFIG register can be read at any time. The value read is the one latched from the EEPROM
cells during the last reset sequence. A new value programmed into this register cannot be read until a
subsequent reset occurs. Unused bits always read as ones.
In normal modes (SMOD = 0), CONFIG bits can only be written using the EEPROM programming sequence, and are neither readable nor active until latched via the next reset. In special modes (SMOD =
1), CONFIG bits can be written at any time.
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CONFIG —System Configuration Register
RESET:
$003F
Bit 7
6
5
4
3
2
1
Bit 0
ROMAD
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
—
1
—
—
—
—
—
—
ROMAD —ROM/EPROM Mapping Control
In single-chip mode ROMAD is forced to one out of reset.
0 = ROM/EPROM located at $2000–$7FFF
1 = ROM/EPROM located at $A000–$FFFF
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Bit 6 —Not implemented
Always reads one
CLKX —XOUT Clock Enable
0 = XOUT pin disabled
1 = Buffered XTAL signal (four times E frequency) driven out on the XOUT pin
PAREN —Pull-Up Assignment Register Enable
0 = Pull-ups always disabled regardless of state of bits in PPAR
1 = Pull-ups either enabled or disabled through PPAR
NOSEC —Security Disable
NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If security mask option is omitted NOSEC always reads one. Refer to 3.6 Security Feature.
0 = Security enabled
1 = Security disabled
NOCOP —COP System Disable
Resets to programmed value
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
ROMON —ROM/EPROM Enable
In single-chip mode, ROMON is forced to one out of reset. In special test mode, ROMON is forced to
zero out of reset.
0 = ROM/EPROM removed from memory map
1 = ROM/EPROM present in memory map
EEON —EEPROM Enable
0 = EEPROM disabled from memory map
1 = EEPROM present in memory map with location depending on value specified in EE[3:0] in INIT2
3.6 Security Feature
The security feature protects memory contents from unauthorized access. Although many devices in
the M68HC11 family support the security feature, an enhancement has been added to the MC68S11K4
that protects the contents of EPROM/OTPROM.
The security feature affects how the MCU behaves in certain modes. When the optional security feature
has been specified prior to manufacture and enabled via the NOSEC bit in CONFIG, the MCU is restricted to operation in single-chip modes only. When the NOSEC bit equals zero, the MCU ignores the
state of the MODA pin during reset. This allows the MCU to be operated in single-chip and bootstrap
modes only. These modes of operation do not allow external visibility of the internal address and data
buses. Although the security feature can easily be disabled when in bootstrap mode, the bootloader
firmware residing in bootstrap ROM checks to see if the NOSEC bit is clear. If NOSEC is clear (security
enabled), the bootloader program performs the following:
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• Output $FF on SCI transmitter.
• Erase EEPROM array.
• Verify that EEPROM has been erased. If it has not, repeat erase procedure.
• Write $FF to every location in RAM.
• Check EPROM for data. If data is present, stay in loop. Otherwise proceed.
• Erase the CONFIG register.
• Continue executing bootloader routine.
Notice that the bootloader routine checks the EPROM to see if it contains any data. The presence of
data causes the routine to stay in a loop. At this time, devices with the security enhancement are only
available as one-time-programmable (OTP) MCUs in non-windowed packages. Once they have been
programmed and secured, they will not function in bootstrap mode.
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For more information refer to M68HC11 Reference Manual (M68HC11RM/AD).
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4 Memory Expansion and Chip Selects
Two additional on-chip blocks are provided with the M68HC11 K-series MCUs. The first block implements additional address lines that become active only when required by the CPU. The second block
provides chip-select signals that simplify the interface to external peripheral devices. Both of these
blocks are fully programmable by values written to associated control registers.
4.1 Memory Expansion
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New to the M68HC11 family of microcontrollers is the ability of the M68HC11 K-series MCUs to extend
the address range of the M68HC11 CPU beyond the physical 64 Kbyte limit of the 16 CPU address
lines. The following is a brief description of how the extended addressing is achieved. For a more detailed discussion refer to application note Using the MC68HC11K4 Memory Mapping Logic (AN452/D).
Memory expansion is achieved by manipulating the CPU address lines such that, even though the CPU
cannot distinguish more than 64 Kbytes of physical memory, up to 1 Mbyte can be accessed through a
paged memory scheme. Additional address lines XA[18:13] are provided as alternate functions of port
G pins. Bits in the port G assignment register (PGAR) define which port G pins are to be used for memory expansion address lines and which are to be used for general-purpose I/O.
In order to access expanded memory, the user must first allocate a range of the 64 Kbyte address space
to be used for the window(s) through which external expanded memory is viewed by the CPU. The size
and placement of the window(s) depend upon values written to the MMSIZ and MMWBR registers, respectively. Which bank or page of the expanded memory that is present in the window(s) at a given time
is dependent upon values written to the MM1CR and MM2CR registers.
Up to two windows can be designated and each can be programmed to 0 (disabled), 8, 16, or 32 Kbytes.
The base address for each window must be an integer multiple of the window size. When the window
size is 32 Kbytes, the base address can be at $0000, $4000, or $8000.
If the windows are defined in such a way that they overlap, bank window 1 has priority and the part of
window 2 that is not overlapped by bank window 1 remains active. If a window is defined such that it
overlaps any internal registers, RAM, or EEPROM, the portion of the registers, RAM, or EEPROM that
is overlapped is repeated in all banks associated with that window. However, if ROM/EPROM is enabled and overlapped by a window, the ROM/EPROM is present only in banks with XA[18:16] = 0:0:0.
Expanded memory is addressed by using a combination of the CPU's normal address lines ADDR[15:0]
and the expansion address lines XA[18:13]. Window size and the number of banks associated with the
window determine exactly which address lines are used. The additional address lines (XA[18:13]) determine which bank is present in a window at a given time. The lower three expansion address lines
(XA[15:13]) are used only when needed by the CPU and replace the CPU's equivalent address lines
(ADDR[15:13]). The following tables show which address lines are used for various configurations of
expanded memory.
Five registers control operation of the memory expansion function. MM1CR and MM2CR registers indicate which bank of a window is active. Each contains the value to be output when the CPU selects
addresses within the memory expansion window. PGAR selects which pins are used for I/O or memory
expansion address lines, defining which extended address lines are used. The MMWBR register defines the starting address of each of the two windows within the CPU 64-Kbyte address range. The MMSIZ register sets the size of the windows in use and selects whether the on-board general-purpose chip
selects are active for CPU addresses or for expansion addresses.
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Table 5 CPU Address and Address Expansion Signals
Number of Banks
8 Kbytes
2
ADDR[12:0]
XA13
ADDR[12:0]
XA[14:13]
ADDR[12:0]
XA[15:13]
ADDR[12:0]
XA[16:13]
ADDR[12:0]
XA[17:13]
ADDR[12:0]
XA[18:13]
4
8
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16
32
64
Window Size
16 Kbytes
32 Kbytes
ADDR[13:0]
XA14
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
—
ADDR[14:0]
XA15
ADDR[14:0]
XA[16:15]
ADDR[14:0]
XA[17:15]
ADDR[14:0]
XA[18:15]
—
—
—
—
PGAR — Port G Assignment
RESET:
32 Kbytes
(Window Based at
$4000)
ADDR[13:0]
XA[15:14]
ADDR[13:0]
XA[16:14]
ADDR[13:0]
XA[17:14]
ADDR[13:0]
XA[18:14]
—
—
—
—
$002D
Bit 7
6
5
4
3
2
1
Bit 0
—
—
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
0
0
0
0
0
0
0
0
Bits [7:6] — Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is address line, XA[18:13]
NOTE
A special case exists for expansion address lines XA[15:13] that overlap the CPU
address lines ADDR[15:13]. If these lines are selected as expansion address lines
in PGAR, but are not used in either window, the corresponding CPU address line
is output on the appropriate port G pin.
MMSIZ — Memory Mapping Size
$0056
Bit 7
6
5
4
3
2
1
Bit 0
MXGS2
MXGS1
W2SZ1
W2SZ0
—
—
W1SZ1
W1SZ0
0
0
0
0
0
0
0
0
RESET:
MXGS[2:1] — Memory Expansion Select for General-Purpose Chip Select 2 or 1
0 = General-purpose chip select 2 or 1 based on 64 Kbyte CPU address
1 = General-purpose chip select 2 or 1 based on expansion address
W2SZ[1:0] — Window 2 Size
These bits select the size of memory expansion window 2. Refer to the table following W1SZ[1:0].
Bits [3:2] — Not implemented
Always read zero
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W1SZ[1:0] —Window 1 Size
These bits select the size of memory expansion window 1.
WxSZ[1:0]
0 0
0 1
1 0
1 1
Window Size
Window disabled
8 K —Window can have up to 64 8-Kbyte banks
16 K —Window can have up to 32 16-Kbyte banks
32 K —Window can have up to 16 32-Kbyte banks
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MMWBR — Memory Mapping Window Base
$0057
Bit 7
6
5
4
3
2
1
Bit 0
$0057
W2A15
W2A14
W2A13
—
W1A15
W1A14
W1A13
—
RESET:
0
0
0
0
0
0
0
0
W2A[15:13] —Window 2 Base Address
Selects the three most significant bit (MSB) of the base address for memory mapping window 2. Refer
to the table following W1A[15:13].
Bit 4 —Not implemented
Always reads zero
W1A[15:13] —Window Base 1 Address
Selects the three MSB of the base address for memory mapping window 1. Refer to the following table
for additional information.
MSB Bits
WxA[15:13]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
8K
$0000
$2000
$4000
$6000
$8000
$A000
$C000
$E000
Window Base Address
16 K
$0000
$0000
$4000
$4000
$8000
$8000
$C000
$C000
32 K
$0000
$0000
$4000
$4000
$8000
$8000
$8000
$8000
Bit 0 —Not implemented
Always reads zero
NOTE
A special case exists when the bank size is 32 Kbytes and the window base address is $4000. The XA14 signal connected to the ADDR14 pin of the memory device automatically drives an inverted CPU ADDR14 signal onto the XA14 pin when
the window is active. The effect occurs while the CPU address is in the $4000–
$BFFF range, the XA pins and external physical memory range is $0000–$7FFF.
MM1CR–MM2CR —Memory Mapping Window 1 and 2 Control
$0058–$0059
Bit 7
6
5
4
3
2
1
Bit 0
$0058
—
X1A18
X1A17
X1A16
X1A15
X1A14
X1A13
—
MM1CR
$0059
—
X2A18
X2A17
X2A16
X2A15
X2A14
X2A13
—
MM2CR
RESET:
0
0
0
0
0
0
0
0
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Bit 7 — Not implemented
Always reads zero
MM1CR — Memory Mapping Window 1 Control Register
When a 64 Kbyte CPU address falls within window 1, the value in MM1CR is driven out from the corresponding expansion address lines to enable the specified bank in the window.
MM2CR — Memory Mapping Window 2 Control Register
When a 64 Kbyte CPU address falls within window 2, the value in MM2CR is driven out from the corresponding expansion address lines to enable the specified bank in the window.
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Bit 0 — Not implemented
Always reads zero
4.2 Overlap Guidelines
• On-chip registers, RAM, and EEPROM are higher priority than expansion windows. If a window
overlaps RAM, registers, or EEPROM, they appear in all banks at their CPU address.
• If a window overlaps on-chip ROM/EPROM, the ROM/EPROM appears only in banks with
XA[18:16] = 0:0:0.
• Window 1 is higher priority than window 2, therefore any overlapped portion of window 2 is inaccessible.
4.3 Chip Selects
M68HC11 K-series MCUs have four software configured chip selects that are enabled in expanded
modes. The chip select for I/O (CSIO) is used for I/O expansion. The program chip select (CSPROG)
is used with an external memory that contains the reset vectors and program. The two general-purpose
chip selects, CSGP1 and CSGP2, are used to enable external devices. These external devices can be
in the 64 Kbyte memory space or in the expanded memory space. Chip select signals are a shared function of port H. When an MCU pin is not used for chip select functions it can be used for general-purpose
I/O. The following table contains a summary of the attributes of each chip select that can be controlled
by user software.
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CSIO
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CSPROG
Enable
Valid
Polarity
Size
Start Address
Stretch
IOEN in CSCTL —1 = On, off at reset (0)
IOCSA in CSCTL —1 = Address valid, 0 = E valid
IOPL in CSCTL —1 = Active high, 0 = Active low
IOSZ in CSCTL —1 = 4K ($1000–$1FFF), 0 = 8K ($0000–$1FFF)
Fixed (see Size)
IO1SA:IO1SB in CSCSTR —0, 1, 2, or 3 E clocks
Enable
Valid
Polarity
Size
PSCEN in CSCTL —1 = On, ON at reset
Fixed (Address valid)
Fixed (Active low)
PCSZA:PCSZB in CSCTL — 0:0 = 64K ($0000–$FFFF)
0:1 = 32K ($8000–$FFFF)
1:0 = 16K ($C000–$FFFF)
1:1 = 8K ($E000–$FFFF)
Fixed (see Size)
PCSA:PCSB in CSCSTR —0, 1, 2, or 3 E clocks
GCSPR in CSCTL —
1 = CSGPx above CSPROG
0 = CSPROG above CSGPx
Start Address
Stretch
Priority
CSGP1,
CSGP2
Enable
Valid
Polarity
Size
Start Address
Stretch
Other
Set size to 0K to disable
GxPOL in GPCS1C (GPCS2C) —1 = Address valid, 0 = E valid
GxAV in GPCS1C (GPCS2C) —1 = Active high, 0 = Active low
Refer to GPCS1C (GPCS2C) —2K to 512K in nine steps, 0K = disable, can also follow memory expansion window 1 or window 2
Refer to GPCS1A (GPCS2A)
Refer to CSCSTR —0, 1, 2, or 3 E clocks
G1DG2 in GPCS1C allows CSGP1 and CSGP2 to be connected to
an internal OR gate and driven out the CSGP2 pin.
G1DPC in GPCS1C allows CSGP1 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
G2DPC in GPCS2C allows CSGP2 and CSPROG to be connected to
an internal OR gate and driven out the CSPROG pin.
MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses
or 512K expansion addresses.
MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses
or 512K expansion addresses.
4.3.1 Program Chip Select (CSPROG)
The program chip select (CSPROG) is active in the range of memory where the main program exists.
CSPROG is enabled out of reset in all modes. After reset in normal mode, the PCS stretch select bit is
set to provide one cycle of stretch so that slow memory devices can be used.
4.3.2 I/O Chip Select (CSIO)
The I/O chip select (CSIO) is programmable for a four Kbyte size located at addresses $1000 to $1FFF
or eight Kbyte size located at addresses $0000 to $1FFF. Polarity of the active state is programmable
for active high or active low. Clock stretching can be set from zero to three cycles.
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4.3.3 General-Purpose Chip Selects (CSGP1, CSGP2)
The general-purpose chip selects are the most flexible and programmable and have the most control
bits. Polarity of active state, E valid or address valid, size, and starting address are all programmable.
Clock stretching can be set from zero to three cycles. Each chip select can be programmed to become
active whenever the CPU address enters a memory expansion window regardless of the actual bank
selected. This is known as following a window.
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Each general purpose chip select can be configured to drive the program chip select. CSGP1 can be
configured to drive CSGP2 or the program chip select. Using one chip select to drive another allows the
same device to cover the address space defined by both chip selects. The two chip selects are connected to an internal OR gate. The output of the OR gate is then driven onto the pin corresponding to
the driven chip select. For example, this is useful when the same external device is used with both bank
windows but the windows are opened independently. In cases where one chip select drives another,
determine the priority from the following table.
Condition
GPCS1 drives GPCS2
GPCS1 drives PCS
GPCS2 drives PCS
GPCS1 and GPCS2 drive PCS
Priority
GPCS1
GPCS1
GPCS2
GPCS1
4.3.4 Chip Select Priorities
To minimize chip select conflicts (with one another or with internal memory and registers), the priority
is determined by the GCSPR bit in the CSCTL register. Refer to the following table.
GCSPR = 0
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
Program Chip Select
GP Chip Select 1
GP Chip Select 2
GCSPR = 1
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
GP Chip Select 1
GP Chip Select 2
Program Chip Select
4.3.5 Chip Select Control Registers
There are six chip select control registers. Chip select functions are enabled by control bits in CSCTL
register. Chip selects are configured by bits in CSCSTR, IOEN, IOPL, IOCSA, and IOSZ registers.
CSCTL — Chip Select Control
RESET:
$005B
Bit 7
6
5
4
3
2
1
Bit 0
IOEN
IOPL
IOCSA
IOSZ
GCSPR
PCSEN
PCSZA
PCSZB
0
0
0
0
0
1
0
0
IOEN —I/O Chip Select Enable
0 = CSIO disabled
1 = CSIO enabled
IOPL —I/O Chip Select Polarity Select
0 = CSIO active low
1 = CSIO active high
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IOCSA —I/O Chip Select Address Valid
0 = Valid during E-clock high time
1 = Valid during address valid time
IOSZ —I/O Chip Select Size Select
0 = $1000–$1FFF (4 Kbyte)
1 = $0000–$1FFF (8 Kbyte)
GCSPR —General-Purpose Chip Select Priority
0 = Program chip select has priority over general-purpose chip selects
1 = General-purpose chip selects have priority over program chip select
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PCSEN —Program Chip Select Enable
0 = CSPROG disabled
1 = CSPROG enabled
PCSZA, PCSZB —Program Chip Select Size (A or B)
PCSZA
0
0
1
1
PCSZB
0
1
0
1
Size (Bytes)
64 K
32 K
16 K
8K
Address Range
$0000–$FFFF
$8000–$FFFF
$C000–$FFFF
$E000–$FFFF
CSCSTR —Chip Select Clock Stretch
RESET:
$005A
Bit 7
6
5
4
3
2
1
Bit 0
IOSA
IOSB
GP1SA
GP1SB
GP2SA
0
0
0
0
0
0
0
1
Normal Modes
0
0
0
0
0
0
0
0
Special Modes
GP2SB PCSA PCSB
IOSA, IOSB —CSIO Stretch Select
GP1SA, GP1SB —CSGP1 Stretch Select
GP2SA, GP2SB —CSGP2 Stretch Select
PCSA, PCSB —CSPROG Stretch Select
Bit [A:B]
00
01
10
11
Clock Stretch
None
1 Cycle
2 Cycles
3 Cycles
GPCS1A —General-Purpose Chip Select 1 Address
RESET:
$005C
Bit 7
6
5
4
3
2
1
Bit 0
G1A18
G1A17
G1A16
G1A15
G1A14
G1A13
G1A12
G1A11
0
0
0
0
0
0
0
0
G1A[18:11] —General-Purpose Chip Select 1 Address
Selects the starting address of general-purpose chip select 1 range. Refer to the G1SZA–G1SZD table.
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GPCS1C —General-Purpose Chip Select 1 Control
$005D
Bit 7
6
5
4
3
2
1
Bit 0
G1DG2
G1DPC
G1POL
G1AV
G1SZA
G1SZB
G1SZC
G1SZD
0
0
0
0
0
0
0
0
RESET:
G1DG2 —General-Purpose Chip Select 1 Drives General-Purpose Chip Select 2
0 = CSGP1 does not affect CSGP2
1 = CSGP1 and CSGP2 are connected to an OR gate and driven out CSGP2
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G1DPC —General-Purpose Chip Select 1 Drives Program Chip Select
0 = CSGP1 does not affect CSPROG
1 = CSGP1 and CSPROG are connected to an OR gate and driven out CSPROG
G1POL —General-Purpose Chip Select 1 Polarity Select
0 = CSGP1 active low
1 = CSGP1 active high
G1AV —General-Purpose Chip Select 1 Address Valid Select
0 = CSGP1 active during E high time
1 = CSGP1 active during address valid time
G1SZA–G1SZD —General-Purpose Chip Select 1 Size
G1SZx
B
C
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1100–1111
A
0
0
0
0
0
0
0
0
1
1
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
Size (Bytes)
Disabled
2K
4K
8K
16 K
32 K
64 K
128 K
256 K
512 K
Follow Window 1
Follow Window 2
Default to 512 K
Valid Bits
(MXGS1 = 0)
None
ADDR[15:11]
ADDR[15:12]
ADDR[15:13]
ADDR[15:14]
ADDR15
None
None
None
None
None
None
None
GPCS2A —General-Purpose Chip Select 2 Address
Valid Bits
(MXGS1 = 1)
None
G1A[18:11]
G1A[18:12]
G1A[18:13]
G1A[18:14]
G1A[18:15]
G1A[18:16]
G1A[18:17]
G1A18
None
None
None
None
$005E
Bit 7
6
5
4
3
2
1
Bit 0
G2A18
G2A17
G2A16
G2A15
G2A14
G2A13
G2A12
G2A11
0
0
0
0
0
0
0
0
RESET:
G2A[18:11] —General-Purpose Chip Select 2 Address
Selects the Starting Address of General-Purpose Chip Select 2 Range. Refer to G2SZA–G2SZD table.
GPCS2C —General-Purpose Chip Select 2 Control
RESET:
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$005F
Bit 7
6
5
4
3
2
1
Bit 0
—
G2DPC
G2POL
G2AV
G2SZA
G2SZB
G2SZC
G2SZD
0
0
0
0
0
0
0
0
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Bit 7 — Not implemented
Always reads zero
G2DPC — General-Purpose Chip Select 2 Drives Program Chip Select
0 = CSGP2 does not affect CSPROG
1 = CSGP2 and CSPROG are connected to an OR gate and driven out CSPROG
G2POL — General-Purpose Chip Select 2 Polarity Select
0 = CSGP2 active low
1 = CSGP2 active high
G2AV — General-Purpose Chip Select 2 Address Valid Select
0 = Active during E high time
1 = Active during address valid time
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G2SZA–G2SZD — General-Purpose Chip Select 2 Size
A
0
0
0
0
0
0
0
0
1
1
1
1
G2SZx
B
C
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1100–1111
D
0
1
0
1
0
1
0
1
0
1
0
1
Size (Bytes)
Disabled
2K
4K
8K
16 K
32 K
64 K
128 K
256 K
512 K
Follow Window 1
Follow Window 2
Default to 512 K
Valid Bits
(MXGS2 = 0)
None
ADDR[15:11]
ADDR[15:12]
ADDR[15:13]
ADDR[15:14]
ADDR15
None
None
None
None
None
None
None
Valid Bits
(MXGS2 = 1)
None
G2A[18:11]
G2A[18:12]
G2A[18:13]
G2A[18:14]
G2A[18:15]
G2A[18:16]
G2A[18:17]
G2A18
None
None
None
None
4.3.6 Examples of Memory Expansion Using Chip Selects
On the following two pages are examples of memory expansion schemes that use chip select signals
to simplify the interface to the external memory devices. Although schematics are not provided, careful
study of the memory map diagram for each example will reveal the simplicity with which an expanded
system can be created. Both examples require a minimum of external circuitry as well as very little program code.
This example is a system consisting of the MCU and a single 27C512-type memory device. This system
uses one chip select and has one window containing eight banks of eight Kbytes each. In this example,
a total of 64 Kbytes is added to the address range of the MCU. Three of the expansion address lines
(XA[15:13]) are used. Register values particular to this example are given below the diagram.
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$0000
WINDOW 1
$1000
$4000
CHIP SELECT 1
$6000
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$A000
INTERNAL
EPROM
$FFFF
$00000
$02000
$04000
$06000
$08000
$0A000
$0C000
$0E000
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
XA[15:13]=
0:0:0
XA[15:13]=
0:0:1
XA[15:13]=
0:1:0
XA[15:13]=
0:1:1
XA[15:13]=
1:0:0
XA[15:13]=
1:0:1
XA[15:13]=
1:1:0
XA[15:13]=
1:1:1
$01FFF
$03FFF
$05FFF
$07FFF
$09FFF
$0BFFF
$0DFFF
$0FFFF
PGAR = $07 XA[15:13]
MMWBR = $04 WINDOW 1 @ $4000,
WINDOW 2 DISABLED
MMSIZ = $41 WINDOW 1 = 8 KBYTES,
WINDOW 2 DISABLED
CSCTL = $00 NO I/O OR PROGRAM CHIP SELECTS
GPCS1A = $00 GEN. PURPOSE CHIP SELECT 1 FROM $00000
GPSC1C = $06 64 KBYTE RANGE (8 X 8K)
GPCS2A = $00 N/A
GPCS2C = $00 GEN. PURPOSE CHIP SELECT 2 DISABLED
Figure 7 Memory Expansion Example 1
This example is a system consisting of the MCU, a single 27C512-type memory device as in the previous example, and two 6226-type memory devices as well. This system uses two chip selects and has
two windows. For purposes of explanation, the setup of the first window is identical to the previous example. In addition, a second window consisting of 16 banks of 16 Kbytes each uses the second chip
select signal. Window 1 contains 64 Kbytes of expanded memory pages, window 2 contains a total of
256 Kbytes of expanded memory. A total of five expansion address lines are used. Register values particular to this example are given below the diagram.
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WINDOW 1
$00000
$02000
$04000
$06000
$08000
$0A000
$0C000
$0E000
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
XA[15:13]=
0:0:0
XA[15:13]=
0:0:1
XA[15:13]=
0:1:0
XA[15:13]=
0:1:1
XA[15:13]=
1:0:0
XA[15:13]=
1:0:1
XA[15:13]=
1:1:0
XA[15:13]=
1:1:1
$01FFF
$03FFF
$05FFF
$07FFF
$09FFF
$0BFFF
$0DFFF
$0FFFF
$0000 EE/REG/RAM
$1000
$4000
CHIP SELECT 1
$6000
$8000
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WINDOW 2
CHIP SELECT 2
$00000
$04000
$08000
$0C000
$10000
$3C000
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
XA[17:14]=
0:0:0:0
XA[17:14]=
0:0:0:1
XA[17:14]=
0:0:1:0
XA[17:14]=
0:0:1:1
XA[17:14]=
0:1:0:0
XA[17:14]=
1:1:1:1
$03FFF
$07FFF
$0BFFF
$0FFFF
$13FFF
$3FFFF
$A000
$C000
INTERNAL
EPROM
$FFFF
PGAR = $1F XA[17:13]
MMWBR = $84 WINDOW 1 @ $4000,
WINDOW 2 @ $8000
MMSIZ = $E1 WINDOW 1 = 8 KBYTES,
WINDOW 2 = 16 KBYTES
CSCTL = $00
GPCS1A = $00
GPSC1C = $06
GPCS2A = $00
GPCS2C = $08
• • • • • • •
BANK 15
NO I/O OR PROGRAM CHIP SELECTS
GEN. PURPOSE CHIP SELECT 1 FROM $00000
64 KBYTE RANGE (8 X 8K)
GEN. PURPOSE CHIP SELECT 2 FROM $00000
256 KBYTE RANGE (16 X 16K)
Figure 8 Memory Expansion Example 2
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5 Resets and Interrupts
All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
• RESET, or Power-On Reset
• Clock Monitor Fail
• COP Failure
The 18 interrupt vectors service 22 interrupt sources (three nonmaskable, 19 maskable). The three nonmaskable interrupt sources are as follows:
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• XIRQ Pin (X-Bit Interrupt)
• Illegal Opcode Trap
• Software Interrupt
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized according to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register (HPRIO). The HPRIO register can be written at any
time, provided bit I in the CCR is set.
Nineteen interrupt sources in the M68HC11 K series devices are subject to masking by the global interrupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external
interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in
M68HC11 devices have separate interrupt vectors; therefore, there is usually no need for software to
poll control registers to determine the cause of an interrupt.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system
is cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any
special instructions.
Refer to the following table for a list of interrupt and reset vector assignments.
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Vector Address
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FFC0, C1 —FFD4, D5
FFD6, D7
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
Interrupt Source
Reserved
SCI Serial System
• SCI Receive Data Register Full
• SCI Receiver Overrun
• SCI Transmit Data Register Empty
• SCI Transmit Complete
• SCI Idle Line Detect
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real Time Interrupt
IRQ
XIRQ Pin
Software Interrupt
Illegal Opcode Trap
COP Failure
Clock Monitor Fail
RESET
CCR Mask
Bit
—
I
Local Mask
I
I
I
I
I
I
I
I
I
I
I
I
I
I
X
None
None
None
None
None
—
Priority
(1 = High)
—
RIE
RIE
TIE
TCIE
ILIE
SPIE
PAII
PAOVI
TOI
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
IC2I
IC1I
RTII
None
None
None
None
NOCOP
CME
None
19
20
21
22
23
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
*
*
3
2
1
*Same level as an instruction
OPTION —System Configuration Options
RESET:
$0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
0
0
0
1
0
0
0
0
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU —A/D Converter Power up
Refer to 9 Analog-to-Digital Converter.
CSEL —Clock Select
Refer to 9 Analog-to-Digital Converter.
IRQE —IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
DLY —Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
M68HC11 K Series
MC68HC11KTS/D
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CME —Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME —Force Clock Monitor Enable
0 = Clock monitor follows the state of the CME bit
1 = Clock monitor circuit is enabled until next reset
CR[1:0] —COP Timer Rate Select
Refer to NOCOP bit in CONFIG register.
Freescale Semiconductor, Inc...
Table 6 COP Timer Rate Select (Timeout Period Length)
CR[1:0]
Rate
Selected
215
XTAL = 8.0 MHz
Timeout
–0 ms, +16.4 ms
16.384 ms
XTAL = 12.0 MHz
Timeout
–0 ms, +10.9 ms
10.923 ms
XTAL = 16.0 MHz
Timeout
–0 ms, +8.2 ms
8.192 ms
00
01
217
65.536 ms
43.691 ms
32.768 ms
10
19
262.14 ms
174.76 ms
131.07 ms
21
1.049 sec
699.05 ms
524.29 ms
2.0 MHz
3.0 MHz
4.0 MHz
2
11
2
E=
COPRST —Arm/Reset COP Timer Circuitry
RESET:
$003A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Write $55 (%01010101) to COPRST to arm COP watchdog clearing mechanism. Write $AA
(%10101010) to COPRST to reset COP watchdog. Refer to NOCOP bit in CONFIG register.
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
$003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT*
SMOD*
MDA*
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
—
—
—
0
0
1
1
0
RESET:
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
RBOOT —Read Bootstrap ROM
Refer to 2 Operating Modes.
SMOD —Special Mode Select
Refer to 2 Operating Modes.
MDA —Mode Select A
Refer to 2 Operating Modes.
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PSEL[4:0] —Priority Select Bit 4 through Bit 0
Can be written only while the I-bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to be elevated above all other I-bit related sources.
4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
M68HC11 K Series
MC68HC11KTS/D
3
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
PSELx
2
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Interrupt Source Promoted
Reserved (Default to IRQ)
Reserved (Default to IRQ)
Reserved (Default to IRQ)
IRQ
Real-Time Interrupt
Timer Input Capture 1
Timer Input Capture 2
Timer Input Capture 3
Timer Output Compare 1
Timer Output Compare 2
Timer Output Compare 3
Timer Output Compare 4
Timer Output Compare 5/Input Capture 4
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input Edge
SPI Serial Transfer Complete
SCI Serial System
Reserved (Default to IRQ)
Reserved (Default to IRQ)
Reserved (Default to IRQ)
Reserved (Default to IRQ)
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6 Parallel Input/Output
Freescale Semiconductor, Inc...
M68HC11 K-series MCUs have up to 62 input/output lines, depending on the operating mode. To enhance the I/O functions, the data bus of this microcontroller is nonmultiplexed. The following table is a
summary of the configuration and features of each port.
Port
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Input Pins
—
—
—
—
8
—
—
—
Output Pins
—
—
—
—
—
—
—
—
Bidirectional Pins
8
8
8
6
—
8
8
8
Shared Functions
Timer
High Order Address
Data Bus
SCI and SPI
A/D Converter
Low Order Address
Memory Expansion
PWM, Chip Select
NOTE
Port pin function is mode dependent. Do not confuse pin function with the electrical
state of the pin at reset. Port pins are either driven to a specified logic level or are
configured as high impedance inputs. I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the corresponding latches are dependent upon the electrical state of the pins during reset. In port
descriptions, an "I" indicates this condition. Port pins that are driven to a known logic level during reset are shown with a value of either one or zero. Some control bits
are unaffected by reset. Reset states for these bits are indicated with a "U".
PORTA —Port A Data
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
—
—
—
NOTE
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being
cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled,
writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5
has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse accumulator input but also can be configured for general-purpose I/O or output compare. Note that even when PA7 is configured as an output, the pin still drives the
pulse accumulator input.
DDRA —Data Direction Register for Port A
RESET:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
0
0
0
0
0
0
0
0
DDA[7:0] —Data Direction for Port A
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
PORTB —Port B Data
$0004
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
S. Chip or
Boot:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
I
I
I
I
I
I
I
I
Expan. or
Test:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
Freescale Semiconductor, Inc...
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high-impedance inputs with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order address outputs and PORTB is not in the memory map.
DDRB —Data Direction Register for Port B
RESET:
$0002
Bit 7
6
5
4
3
2
1
Bit 0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
0
0
0
0
0
0
0
0
DDB[7:0] —Data Direction for Port B
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTC —Port C Data
$0006
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
S. Chip or
Boot:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
RESET:
0
0
0
0
0
0
0
0
Expan. or
Test:
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Reset state is mode dependent. In single-chip or bootstrap modes, port C pins are high-impedance inputs with selectable internal pull-up resistors. In expanded or test modes, port C pins are data bus inputs
and outputs and PORTC is not in the memory map. Refer to CWOM bit in OPT2 register description
that follows.
DDRC —Data Direction Register for Port C
RESET:
$0007
Bit 7
6
5
4
3
2
1
Bit 0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
0
0
0
0
0
0
0
0
DDC[7:0] —Data Direction for Port C. Refer to CWOM bit in OPT2 register description that follows.
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
M68HC11 K Series
MC68HC11KTS/D
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OPT2 —System Configuration Options 2
$0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
—
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
RESET:
LIRDV—LIR Driven
Refer to 2 Operating Modes.
CWOM —Port C Wired-OR Mode
0 = Port C operates normally.
1 = Port C outputs are open-drain.
Freescale Semiconductor, Inc...
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
Refer to 2 Operating Modes.
LSBF —SPI LSB First Enable
Refer to 8 Serial Peripheral Interface.
SPR2 —SPI Clock (SCK) Rate Select
Refer to 8 Serial Peripheral Interface.
XDV[1:0] —XOUT Clock Divide Select
Refer to 2 Operating Modes.
PORTD —Port D Data
$0008
Bit 7
6
5
4
3
2
1
Bit 0
—
—
PD5
PD4
PD3
PD2
PD1
PD0
RESET:
0
0
I
I
I
I
I
I
Alt. Pin
Func.:
—
—
SS
SCK
MOSI
MISO
TxD
RxD
DDRD —Data Direction Register for Port D
RESET:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
—
—
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
0
0
0
0
0
0
0
0
Bits [7:6] — Not implemented
Always read zero
DDD[5:0] — Data Direction for Port D
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
NOTE
When the SPI system is in slave mode, DDD5 has no meaning nor effect. When
the SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an
error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI
system is enabled and expects any of bits [4:2] to be an input that bit will be an input
regardless of the state of the associated DDR bit. If any of bits [4:2] are expected
to be outputs that bit will be an output only if the associated DDR bit is set.
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
SPCR —Serial Peripheral Control
RESET:
$0028
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
1
0
0
0
0
0
Boot Mode
0
0
0
0
0
0
0
0
Other Modes
SPIE —SPI Interrupt Enable
Refer to 8 Serial Peripheral Interface.
Freescale Semiconductor, Inc...
SPE —SPI System Enable
Refer to 8 Serial Peripheral Interface.
DWOM —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also WOMS bit in SCCR1)
0 = PD[5:2] are normal CMOS outputs
1 = PD[5:2] are open-drain outputs
MSTR —Master/Slave Mode Select
Refer to 8 Serial Peripheral Interface.
CPOL —Clock Polarity
Refer to 8 Serial Peripheral Interface.
CPHA —Clock Phase
Refer to 8 Serial Peripheral Interface.
SPR[1:0] —SPI Clock Rate Selects
Refer to 8 Serial Peripheral Interface.
SCCR1 —SCI Control 1
RESET:
$0072
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
WOMS
—
M
WAKE
ILT
PE
PT
0
1
0
0
0
0
0
0
Boot Mode
0
0
0
0
0
0
0
0
Other Modes
LOOPS —SCI LOOP Mode Enable
Refer to 7 Serial Communications Interface.
WOMS —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also DWOM bit in SPCR.)
0 = TxD and RxD operate normally
1 = TxD and RxD are open drains if operating as an output
Bit 5 —Not implemented
Always reads zero
M —Mode (Select Character Format)
Refer to 7 Serial Communications Interface.
WAKE —Wakeup by Address Mark/Idle
Refer to 7 Serial Communications Interface.
ILT —Idle Line Type
Refer to 7 Serial Communications Interface.
PE —Parity Enable
Refer to 7 Serial Communications Interface.
M68HC11 K Series
MC68HC11KTS/D
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PT —Parity Type
Refer to 7 Serial Communications Interface.
PORTE —Port E Data
$000A
Bit 7
6
5
4
3
2
1
Bit 0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Freescale Semiconductor, Inc...
DDRF —Data Direction Register for Port F
RESET:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
0
0
0
0
0
0
0
0
DDF[7:0] —Data Direction for Port F
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
PORTF —Port F Data
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
S. Chip or
Boot:
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
I
I
I
I
I
I
I
I
Expan. or
Test:
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
Reset state is mode dependent. In single-chip or bootstrap modes, port F is high-impedance input with
selectable internal pull-up resistors. In expanded or test modes, port F pins are low order address outputs and PORTF is not in the memory map.
PORTH —Port H Data
$007C
Bit 7
6
5
4
3
2
1
Bit 0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
CSPROG
CSGP2
CSGP1
CSIO
PW4
PW3
PW2
PW1
Port H pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes, reset also causes PH7 to be configured as CSPROG.
DDRH —Data Direction Register for Port H
RESET:
$007D
Bit 7
6
5
4
3
2
1
Bit 0
DDH7
DDH6
DDH5
DDH4
DDH3
DDH2
DDH1
DDH0
0
0
0
0
0
0
0
0
DDH[7:0] —Data Direction for Port H
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
NOTE
In expanded and special test modes, chip-select circuitry forces the I/O state to be
an output for each port H pin associated with an enabled chip select. In any mode,
PWM circuitry forces the I/O state to be an output for each port H line associated
with an enabled pulse width modulator channel. In these cases, data direction bits
are not changed and have no effect on these lines. DDRH reverts to controlling the
I/O state of a pin when the associated function is disabled. Refer to 4.3 Memory
Expansion and Chip Selects and 12 Pulse-Width Modulation Timer for further
information.
Freescale Semiconductor, Inc...
PORTG —Port G Data
$007E
Bit 7
6
5
4
3
2
1
Bit 0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
RESET:
I
I
I
I
I
I
I
I
Alt. Pin
Func.:
R/W
—
XA18
XA17
XA16
XA15
XA14
XA13
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and
special test modes PG7 becomes R/W. Refer to PGAR register description.
DDRG —Data Direction Register for Port G
RESET:
$007F
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
0
0
0
0
0
0
0
0
DDG[7:0] —Data Direction for Port G
0 = Configure corresponding I/O pin for input only
1 = Configure corresponding I/O pin for output
In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output
although the DDRG value remains zero. Refer to PGAR register description.
PGAR — Port G Assignment
$002D
Bit 7
6
5
4
3
2
1
Bit 0
$002D
—
—
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
RESET:
0
0
0
0
0
0
0
0
Bits [7:6] —Not implemented
Always read zero
PGAR[5:0] —Port G Pin Assignment Bits [5:0]
0 = Corresponding port G pin is general-purpose I/O
1 = Corresponding port G pin is memory expansion address line (XA[18:13])
NOTE
Each PGAR bit forces the I/O state to be an output for each port G pin associated
with an enabled expansion address line. In this case, data direction bits are not
changed and have no effect on these lines. DDRG reverts to controlling the I/O
state of a pin when the associated function is disabled. Refer to 4.1 Memory Expansion for further information.
M68HC11 K Series
MC68HC11KTS/D
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PPAR —Port Pull-Up Assignment
RESET:
$002C
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
HPPUE
GPPUE
FPPUE
BPPUE
0
0
0
0
1
1
1
1
Bits [7:4] —Not implemented
Always read zero
xPPUE —Port x Pin Pull-Up Enable
Valid only when PAREN = 1. Refer to PAREN bit in the CONFIG register description.
0 = Port x pin on-chip pull-up devices disabled
1 = Port x pin on-chip pull-up devices enabled
Freescale Semiconductor, Inc...
NOTE
FPPUE and BPPUE have no effect in expanded mode because port F and port B
are address outputs.
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
7 Serial Communications Interface
The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one
of two independent serial I/O subsystems in M68HC11 K-series MCUs. Rearranging registers and control bits used in previous M68HC11 family devices has enhanced the existing SCI system and added
new features, which include the following:
•
•
•
•
A 13-bit modulus prescaler that allows greater baud rate control
A new idle mode detect, independent of preceding serial data
A receiver active flag
Hardware parity for both transmitter and receiver
Freescale Semiconductor, Inc...
The enhanced baud rate generator is shown in the following diagram. Refer to Table 7 for standard values.
13-BIT COUNTER
EXTAL
INTERNAL
PHASE 2 CLOCK
RESET
13-BIT COMPARE
=
÷2
RECEIVER
BAUD RATE
CLOCK
SYNCH
SCBDH/L SCI BAUD CONTROL
÷ 16
TRANSMITTER
BAUD RATE
CLOCK
Figure 9 SCI Baud Generator Circuit Diagram
M68HC11 K Series
MC68HC11KTS/D
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Freescale Semiconductor, Inc.
TRANSMITTER
BAUD RATE
CLOCK
(WRITE ONLY)
SCDR Tx BUFFER
DDD1
10 (11) - BIT Tx SHIFT REGISTER
2
1
0
PIN BUFFER
AND CONTROL
L
BREAK—JAM 0s
3
JAM ENABLE
4
PREAMBLE—JAM 1s
5
SHIFT ENABLE
6
PD1
TxD
8
FORCE PIN
DIRECTION (OUT)
TRANSMITTER
CONTROL LOGIC
SCCR1 SCI CONTROL 1
OR
NF
FE
TC
RDRF
IDLE
TDRE
WAKE
M
8
R8
T8
SCSR INTERRUPT STATUS
8
TDRE
TIE
TC
TCIE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Freescale Semiconductor, Inc...
SIZE 8/9
TRANSFER Tx BUFFER
H (8) 7
SCCR2 SCI CONTROL 2
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 10 SCI Transmitter Block Diagram
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
RECEIVER
BAUD RATE
CLOCK
PIN BUFFER
AND CONTROL
PD0/
RxD
DATA
RECOVERY
START
÷16
STOP
DDD0
10 (11) - BIT
Rx SHIFT REGISTER
(8) 7
6
5
4
3
MSB
DISABLE
DRIVER
2
1
0
ALL ONES
PARITY
DETECT
SCSR2 SCI STATUS 2
M
WAKE-UP
LOGIC
RWU
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
M
WAKE
ILT
PE
PT
LOOPS
WOMS
SCCR1 SCI CONTROL 1
R8 T8 – – – – – –
SCDRH Tx/Rx DATA HIGH
7
SCSR1 SCI STATUS 1
6 5 4 3 2 1 0
SCDRL Tx/Rx DATA LOW
$x076
$x077
(READ-ONLY)
RDRF
RIE
IDLE
ILIE
OR
RIE
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Freescale Semiconductor, Inc...
RAF
RE
SCCR2 SCI CONTROL 2
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 11 SCI Receiver Block Diagram
M68HC11 K Series
MC68HC11KTS/D
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SCBDH/L —SCI Baud Rate Control High/Low
$0070, $0071
Bit 7
6
5
4
3
2
1
Bit 0
$0070
BTST
BSPL
—
SBR12
SBR11
SBR10
SBR9
SBR8
RESET:
0
0
0
0
0
0
0
0
$0071
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
RESET:
0
0
0
0
0
1
0
0
High
Low
BTST —Baud Register Test (TEST)
Factory test only
Freescale Semiconductor, Inc...
BSPL —Baud Rate Counter Split (TEST)
Factory test only
Bit 5 —Not implemented
Always reads zero
SBR[12:0] —SCI Baud Rate Selects
Use the following formula to calculate SCI baud rate. Refer to the table of baud rate control values for
example rates.
SCI baud rate = EXTAL ÷[16 ∗ (2 ∗ BR)]
Where BR is the contents of SCBDH/L (BR = 1, 2, 3 ... 8191).
BR = 0 disables the baud rate generator.
Table 7 SCI Baud Rate Control Values
Target
Crystal Frequency (EXTAL)
Baud
8 MHz
12 MHz
Dec Value
16 MHz
Rate
Dec Value
Hex Value
Hex Value
Dec Value
110
2272
$08E0
3409
$0D51
4545
$11C1
150
1666
$0682
2500
$09C4
3333
$0D05
300
833
$0341
1250
$04E2
1666
$0682
600
416
$01A0
625
$0271
833
$0341
1200
208
$00D0
312
$0138
416
$01A0
2400
104
$0068
156
$009C
208
$00D0
4800
52
$0034
78
$004E
104
$0068
9600
26
$001A
39
$0027
52
$0034
19.2 K
13
$000D
20
$0014
26
$001A
38.4 K
—
—
—
—
13
$000D
SCCR1 —SCI Control 1
$0072
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
WOMS
—
M
WAKE
ILT
PE
PT
0
1
0
0
0
0
0
0
Bootstrap
Mode
0
0
0
0
0
0
0
0
Other Modes
RESET:
MOTOROLA
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Hex Value
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
LOOPS —SCI LOOP Mode Enable
0 = SCI transmit and receive operate normally
1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is
fed back into the receiver input
WOMS —Wired-OR Mode Option for PD[1:0] (See also DWOM bit in SPCR.)
0 = TxD and RxD operate normally
1 = TxD and RxD are open drains if operating as an output
Bit 5 —Not implemented
Always reads zero
Freescale Semiconductor, Inc...
M —Mode (Select Character Format)
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE —Wakeup by Address Mark/Idle
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
ILT —Idle Line Type
0 = Short (SCI counts consecutive ones after start bit)
1 = Long (SCI counts ones only after stop bit)
PE —Parity Enable
0 = Parity disabled
1 = Parity enabled
PT —Parity Type
0 = Parity even (even number of ones causes parity bit to be zero, odd number of ones causes parity bit to be one)
1 = Parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity
bit to be one)
SCCR2 —SCI Control 2
RESET:
$0073
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
TIE —Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE —Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE —Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
ILIE —Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE —Transmitter Enable
0 = Transmitter disabled
1 = Transmitter enabled
M68HC11 K Series
MC68HC11KTS/D
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RE —Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
RWU —Receiver Wakeup Control
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK —Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
Freescale Semiconductor, Inc...
SCSR1 —SCI Status Register 1
RESET:
$0074
Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
TDRE —Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR1 and then writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC —Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR1 and then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF —Receive Data Register Full Flag
RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR1 and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE —Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1
and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR —Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. Clear
the OR flag by reading SCSR1 and then reading SCDR.
0 = No overrun
1 = Overrun detected
NF —Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR1 and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE —Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1
and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
PF —Parity Error Flag
PF is set if received data has incorrect parity. Clear PF by reading SCSR1 and then reading SCDR.
0 = Parity correct
1 = Incorrect parity detected
SCSR2 —SCI Status Register 2
RESET:
$0075
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
—
—
—
RAF
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc...
Bits [7:1] —Not implemented
Always read zero
RAF —Receiver Active Flag (Read Only)
0 = A character is not being received
1 = A character is being received
SCDRH, SCDRL —SCI Data Register High/Low
$0076, $0077
Bit 7
6
5
4
3
2
1
Bit 0
$0076
R8
T8
—
—
—
—
—
—
SCDRH
(High)
$0077
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
SCDRL
(Low)
R8 —Receiver Bit 8
Ninth serial data bit received when SCI is configured for nine-data-bit operation.
T8 —Transmitter Bit 8
Ninth serial data bit transmitted when SCI is configured for nine-data-bit operation.
Bits [5:0] —Not implemented
Always read zero
R/T[7:0] —Receiver/Transmitter Data Bits [7:0]
SCI data is double buffered in both directions.
M68HC11 K Series
MC68HC11KTS/D
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8 Serial Peripheral Interface
The SPI allows the MCU to communicate synchronously with peripheral devices and other microprocessors. Data rates can be as high as 2 Mbits per second when configured as a master and 4 Mbits per
second when configured as a slave (assuming 4 MHz bus speed).
Two control bits in OPT2 allow the transfer of data either MSB or LSB first and select an additional divide
by four stage to be inserted before the SPI baud rate clock divider.
M
MSB
LSB
÷2 ÷4 ÷16 ÷32 ÷8 ÷16 ÷64 ÷128
LSBF
READ DATA BUFFER
CLOCK
PIN
CONTROL
LOGIC
SPI CLOCK (MASTER)
SELECT
S
M
SPE
LSBF
DWOM
SS/
PD5
MSTR
SPR1
SCK/
PD4
SPR0
CLOCK
LOGIC
SPR2
MOSI/
PD3
M
S
8-BIT SHIFT REGISTER
DIVIDER
OPTIONS REGISTER 2
MSTR
SPE
SPI CONTROL
SPSR SPI STATUS REGISTER
SPR1
SPR0
CPOL
CPHA
MSTR
DWOM
SPE
SPIE
MODF
WCOL
SPIE
SPIF
Freescale Semiconductor, Inc...
MISO/
PD2
S
INTERNAL
MCU CLOCK
SPCR SPI CONTROL REGISTER
8
8
SPI INTERRUPT
REQUEST
8
INTERNAL
DATA BUS
Figure 12 SPI Block Diagram
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
SPCR —Serial Peripheral Control Register
RESET:
$0028
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
0
0
1
U
U
SPIE —Serial Peripheral Interrupt Enable
0 = SPI interrupts disabled
1 = SPI interrupts enabled
Freescale Semiconductor, Inc...
SPE —Serial Peripheral System Enable
0 = SPI off
1 = SPI on
DWOM —Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also WOMS bit in SCCR1.)
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR —Master Mode Select
0 = Slave mode
1 = Master mode
CPOL, CPHA —Clock Polarity, Clock Phase
Refer to the following figure, SPI Transfer Format.
SCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE)
Figure 13 SPI Transfer Format
NOTE
This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is
transferred in reverse order (LSB first).
M68HC11 K Series
MC68HC11KTS/D
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SPR[2:0] —SPI Clock Rate Selects (SPR2 is located in OPT2 register)
Freescale Semiconductor, Inc...
Table 8 SPI Clock Rate Selects
SPR[2:0]
Divide
E Clock By
Frequency at
E = 2 MHz (Baud)
Frequency at
E = 3 MHz (Baud)
Frequency at
E = 4 MHz (Baud)
000
2
1.0 MHz
3.0 MHz
4.0 MHz
001
4
500 kHz
750 kHz
1.0 MHz
010
16
125 kHz
187.5 kHz
250 kHz
011
32
62.5 kHz
93.75 kHz
125 kHz
100
8
250 kHz
375 kHz
500 kHz
101
16
125 kHz
187.5 kHz
250 kHz
110
64
31.25 kHz
46.875 kHz
62.5 kHz
111
128
15.625 kHz
23.438 kHz
31.25 kHz
SPSR —Serial Peripheral Status Register
$0029
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
—
MODF
—
—
—
—
0
0
0
0
0
0
0
0
RESET:
SPIF —SPI Transfer Complete Flag
This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this
flag by reading SPSR, then access SPDR.
0 = No SPI transfer complete or SPI transfer still in progress
1 = SPI transfer complete
WCOL —Write Collision Error Flag
This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear
this flag by reading SPSR, then access SPDR.
0 = No write collision error
1 = SPDR written while SPI transfer in progress
Bit 5 —Not implemented
Always reads zero
MODF —Mode Fault (Mode fault terminates SPI operation)
Set when SS is pulled low while MSTR = 1. Cleared by SPSR read followed by SPCR write.
0 = No mode fault error
1 = SS pulled low in master mode
Bits [3:0] —Not implemented
Always read zero
SPDR —SPI Data
$002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
SPI is double buffered in, single buffered out.
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
OPT2 —System Configuration Options 2
RESET:
$0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
—
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
LIRDV—LIR Driven
Refer to 2 Operating Modes.
CWOM —Port C Wired-OR Mode
Refer to 6 Parallel Input/Output.
Freescale Semiconductor, Inc...
Bit 5 —Not implemented
Always read zero
IRVNE —Internal Read Visibility/Not E
Refer to 2 Operating Modes.
LSBF —SPI LSB First Enable
0 = SPI data transferred MSB first
1 = SPI data transferred LSB first
SPR2 —SPI Clock (SCK) Rate Select
Adds a divide by four prescaler to SPI clock chain. Refer to SPCR register.
XDV[1:0] —XOUT Clock Divide Select
Refer to 2 Operating Modes.
M68HC11 K Series
MC68HC11KTS/D
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9 Analog-to-Digital Converter
The analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to
convert analog signals to digital values. The A/D converter system contained in M68HC11 K-series
MCUs is an 8-channel,8-bit, multiplexed-input, successive-approximation converter. It does not require
external sample and hold circuits.
PE0/
AN0
VRH
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
PE1/
AN1
VRL
PE2/
AN2
PE3/
AN3
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
RESULT
ANALOG
MUX
PE4/
AN4
PE5/
AN5
INTERNAL
DATA BUS
PE7/
AN7
SCAN
MULT
CD
CC
CB
CA
PE6/
AN6
CCF
Freescale Semiconductor, Inc...
The clock source for the A/D converter’s charge pump, like the clock source for the EEPROM charge
pump, is selected with the CSEL bit in the OPTION register. When the E clock is slower than 1 MHz,
the CSEL bit must be set to ensure that the successive approximation sequence for the A/D converter
will be completed before any charge loss occurs. In the case of the EEPROM, it is the efficiency of the
charge pump that is affected.
ADCTL A/D CONTROL
RESULT REGISTER INTERFACE
ADDR 1 A/D RESULT 1
ADDR 2 A/D RESULT 2
ADDR 3 A/D RESULT 3
ADDR 4 A/D RESULT 4
Figure 14 A/D Converter Block Diagram
The A/D converter can operate in single or multiple conversion modes. Multiple conversions are performed in sequences of four. Sequences can be performed on a single channel or an a group of channels.
Dedicated lines VRH and VRL provide the reference supply voltage inputs.
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
A multiplexer allows the single A/D converter to select one of 16 analog input signals.
The A/D converter control logic implements automatic conversion sequences on a selected channel
four times or on four channels once each. A write to the ADCTL register initiates conversions and, if
made while a conversion is in progress, a write to ADCTL also halts that conversion operation, sets
CCF, and proceeds to the next instruction.
When the SCAN bit is zero, four requested conversions are performed, once each, to fill the four result
registers. When SCAN is one, conversions continue in a round-robin fashion with the result registers
being updated as new data becomes available. When the MULT bit is zero, the A/D converter system
is configured to perform conversions on each channel in the group of four channels specified by the CD
and CC channel select bits.
Freescale Semiconductor, Inc...
E CLOCK
WRITE
TO
ADCTL
MSB
4
CYCLES
12 E CYCLES
SAMPLE ANALOG INPUT
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
2
CYC
END
SUCCESSIVE APPROXIMATION SEQUENCE
REPEAT
SEQUENCE
IF
SCAN = 1
SET
CCF
FLAG
0
CONVERT FIRST
CHANNEL
AND UPDATE ADDR1
32
CONVERT SECOND
CHANNEL
AND UPDATE ADDR2
64
CONVERT THIRD
CHANNEL
AND UPDATE ADDR3
96
CONVERT FOURTH
CHANNEL
AND UPDATE ADDR4
128
E
CYCLES
Figure 15 Timing Diagram for a Sequence of Four A/D Conversions
INPUT
PROTECTION
DEVICE
ANALOG
INPUT
PIN
DIFFUSION AND
POLY COUPLER
≤ 4 kΩ
< 2 pF
+ ~ 20 V
– ~ 0.7 V
*
~ 20 pF
400 nA
JUNCTION
LEAKAGE
DAC
CAPACITANCE
VRL
* This analog switch is closed only during the 12-cycle sample time.
Figure 16 Electrical Model of an Analog Input Pin (Sample Mode)
M68HC11 K Series
MC68HC11KTS/D
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ADCTL —A/D Control/Status
$0030
Bit 7
6
5
4
3
2
1
Bit 0
CCF
—
SCAN
MULT
CD
CC
CB
CA
0
0
0
0
0
0
0
0
RESET:
CCF — Conversions Complete Flag
0 = Write to ADCTL is complete
1 = A/D conversion cycle is complete
Freescale Semiconductor, Inc...
Bit 6 — Not implemented
Always reads zero
SCAN —Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
MULT —Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CD:CA —Channel Select D through A
Table 9 A/D Converter Channel Assignments
Channel Select Control Bits
Channel Signal
Result in ADRx if
MULT = 1
CD
CC
CB
CA
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
AN0
AN1
AN2
AN3
ADR1
ADR2
ADR3
ADR4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
AN4
AN5
AN6
AN7
ADR1
ADR2
ADR3
ADR4
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
—
—
—
—
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
VRH*
VRL*
(VRH)/2*
Reserved*
ADR1
ADR2
ADR3
ADR4
*Used for factory testing
ADR[4:1] —A/D Results
$0031 – $0034
$0031
Bit 7
6
5
4
3
2
1
Bit 0
ADR1
$0032
Bit 7
6
5
4
3
2
1
Bit 0
ADR2
$0033
Bit 7
6
5
4
3
2
1
Bit 0
ADR3
$0034
Bit 7
6
5
4
3
2
1
Bit 0
ADR4
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
OPTION —System Configuration Options
RESET:
$0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
0
0
0
1
0
0
0
0
ADPU —A/D Converter Power-Up
0 = A/D converter powered down
1 = A/D converter powered up
Freescale Semiconductor, Inc...
CSEL — Clock Select
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock source
IRQE —IRQ Select Edge Sensitive Only
Refer to 5 Resets and Interrupts
DLY —Enable Oscillator Startup Delay on Exit from Stop
Refer to 5 Resets and Interrupts
CME —Clock Monitor Enable
Refer to 5 Resets and Interrupts
FCME —Force Clock Monitor Enable
Refer to 5 Resets and Interrupts
CR[1:0] —COP Timer Rate Select
Refer to 10 Main Timer
M68HC11 K Series
MC68HC11KTS/D
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10 Main Timer
The timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler.
A timer overflow function allows software to extend the timing capability of the system beyond the 16bit range of the counter.
The timer has three channels for input capture, four channels for output compare, and one channel that
can be configured as a fourth input capture or a fifth output compare. In addition, the timing system includes pulse accumulator and real-time interrupt (RTI) functions, as well as a clock monitor function,
which can be used to detect clock failures that are not detected by the COP.
Refer to 11 Pulse Accumulator and 10.1 Real-Time Interrupt for further information about these functions. Refer to the following table for a summary of the crystal-related frequencies and periods.
Freescale Semiconductor, Inc...
Table 10 Timer Summary
Control Bits
PR[1:0]
Common System Frequencies
Definition
8.0 MHz
12.0 MHz
16.0 MHz
XTAL
2.0 MHz
3.0 MHz
4.0 MHz
E
Main Timer Count Rates (Period Length)
00
1 count —
overflow —
500 ns
32.768 ms
333 ns
21.845 ms
250 ns
16.384 ms
1/E
216/E
01
1 count —
overflow —
2.0 µs
131.07 ms
1.333 µs
87.381 ms
1.0 µs
65.536 ms
4/E
218/E
10
1 count —
overflow —
4.0 µs
262.14 ms
2.667 µs
174.76 ms
2.0 µs
131.07 ms
8/E
219/E
11
1 count —
overflow —
8.0 µs
524.29 ms
5.333 µs
349.52 ms
4.0 µs
262.14 ms
16/E
220/E
RTR[1:0]
00
01
10
11
CR[1:0]
Periodic (RTI) Interrupt Rates (Period Length)
4.096 ms
8.192 ms
16.384 ms
32.768 ms
2.731 ms
5.461 ms
10.923 ms
21.845 ms
2.048 ms
4.096 ms
8.192 ms
16.384 ms
213/E
214/E
215/E
216/E
COP Watchdog Timeout Rates (Period Length)
00
01
10
11
16.384 ms
65.536 ms
262.14 ms
1.049 s
10.923 ms
43.691 ms
174.76 ms
699.05 ms
8.192 ms
32.768 ms
131.07 ms
524.28 ms
215/E
217/E
219/E
221/E
Timeout Tolerance
(–0 ms/+...)
16.4 ms
10.9 ms
8.192 ms
215/E
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
TCNT (HI)
PRESCALER–DIVIDE BY
MCU
ECLK
1, 4, 8, OR 16
PR1
TCNT (LO)
16-BIT FREE-RUNNING
COUNTER
PR0
TOI
TAPS FOR RTI, COP
WATCHDOG AND
PULSE ACCUMULATOR
16-BIT TIMER BUS
9
TOF
TO
PULSE
ACCUMULATOR
INTERRUPT REQUESTS
(FURTHER QUALIFIED
BY I-BIT IN CCR)
TMSK1
OC1I
TFLG1
16-BIT COMPARATOR =
TOC1 (HI)
TOC1 (LO)
PIN
FUNCTIONS
8
BIT-7
PA7/
OC1/
PAI
BIT-6
PA6/
OC2/
OC1
BIT-5
PA5/
OC3/
OC1
BIT-4
PA4/
OC4/
OC1
BIT-3
PA3
OC5/
IC4/
OC1
3
BIT-2
PA2/
IC1
2
BIT-1
PA1/
IC2
1
BIT-0
PA0/
IC3
CFORC
OC1F
FOC1
16-BIT COMPARATOR =
TOC2 (HI)
TOC2 (LO)
7
OC2F
FOC2
OC3I
16-BIT COMPARATOR =
TOC3 (HI)
TOC3 (LO)
6
OC3F
FOC3
OC4I
16-BIT TIMER BUS
Freescale Semiconductor, Inc...
OC2I
16-BIT COMPARATOR =
TOC4 (HI)
TOC4 (LO)
5
OC4F
FOC4
I4/O5I
16-BIT COMPARATOR =
TI4/O5 (HI) TI4/O5 (LO)
16-BIT LATCH CLK
4
OC5
I4/O5F
FOC5
IC4
FORCE
OUTPUT
COMPARE
I4/O5
16-BIT LATCH CLK
TIC1 (HI)
TIC1 (LO)
IC1I
IC1F
IC2I
16-BIT LATCH CLK
TIC2 (HI)
TIC2 (LO)
IC2F
IC3I
16-BIT LATCH CLK
TIC3 (HI)
TIC3 (LO)
IC3F
STATUS
FLAGS
INTERRUPT
ENABLES
PORT A
PIN
CONTROL
Figure 17 Timer Block Diagram
M68HC11 K Series
MC68HC11KTS/D
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MOTOROLA
65
Freescale Semiconductor, Inc.
CFORC —Timer Compare Force
$000B
Bit 7
6
5
4
3
2
1
Bit 0
FOC1
FOC2
FOC3
FOC4
FOC5
—
—
—
0
0
0
0
0
0
0
0
RESET:
FOC[5:1] —Force Output Compare
Write ones to force compare(s)
0 = Not affected
1 = Output x action occurs
Bits [2:0] —Not implemented
Always read zero
Freescale Semiconductor, Inc...
OC1M —Output Compare 1 Mask
$000C
Bit 7
6
5
4
3
2
1
Bit 0
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
—
—
—
0
0
0
0
0
0
0
0
RESET:
Set bit(s) to enable OC1 to control corresponding pin(s) of port A
Bits [2:0] —Not implemented
Always read zero
OC1D —Output Compare 1 Data
$000D
Bit 7
6
5
4
3
2
1
Bit 0
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
—
—
—
0
0
0
0
0
0
0
0
RESET:
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
Bits [2:0] —Not implemented
Always read zero
TCNT —Timer Count
$000E, $000F
$000E
Bit 15
14
13
12
11
10
9
Bit 8
High
$000F
Bit 7
6
5
4
3
2
1
Bit 0
Low
TCNT
TCNT resets to $0000. In normal modes, TCNT is read only.
TIC1–TIC3 —Timer Input Capture
$0010–$0015
$0010
Bit 15
14
13
12
11
10
9
Bit 8
High
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Low
$0012
Bit 15
14
13
12
11
10
9
Bit 8
High
$0013
Bit 7
6
5
4
3
2
1
Bit 0
Low
$0014
Bit 15
14
13
12
11
10
9
Bit 8
High
$0015
Bit 7
6
5
4
3
2
1
Bit 0
Low
TIC1
TIC2
TIC3
TICx not affected by reset
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
TOC1–TOC4 —Timer Output Compare
$0016–$001D
$0016
Bit 15
14
13
12
11
10
9
Bit 8
High
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Low
$0018
Bit 15
14
13
12
11
10
9
Bit 8
High
$0019
Bit 7
6
5
4
3
2
1
Bit 0
Low
$001A
Bit 15
14
13
12
11
10
9
Bit 8
High
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Low
$001C
Bit 15
14
13
12
11
10
9
Bit 8
High
$001D
Bit 7
6
5
4
3
2
1
Bit 0
Low
TOC1
TOC2
TOC3
TOC4
Freescale Semiconductor, Inc...
All TOCx register pairs reset to ones ($FFFF).
TI4/O5 —Timer Input Capture 4/Output Compare 5
$001E–$001F
$001E
Bit 15
14
13
12
11
10
9
Bit 8
High
$001F
Bit 7
6
5
4
3
2
1
Bit 0
Low
This is a shared register and is either input capture 4 or output compare 5 depending on the state of bit
I4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. The
TI4/O5 register pair resets to ones ($FFFF).
TCTL1 —Timer Control 1
$0020
Bit 7
6
5
4
3
2
1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0
0
0
0
0
0
0
0
RESET:
OM[5:2] —Output Mode
OL[5:2] —Output Level
OMx
0
0
1
1
OLx
0
1
0
1
Action Taken on Successful Compare
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
TCTL2 —Timer Control 2
RESET:
$0021
Bit 7
6
5
4
3
2
1
Bit 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
0
0
0
0
0
0
0
0
Table 11 Timer Control Configuration
EDGxB
0
0
1
1
M68HC11 K Series
MC68HC11KTS/D
EDGxA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge
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MOTOROLA
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Freescale Semiconductor, Inc.
TMSK1 —Timer Interrupt Mask 1
$0022
Bit 7
6
5
4
3
2
1
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
RESET:
OC1I–OC4I —Output Compare x Interrupt Enable
If the OCxF flag bit is set while the OCxI enable bit is set, a hardware interrupt sequence is requested.
I4/O5I —Input Capture 4 or Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt bit. When I4/O5 in PACTL is zero,
I4/O5I is the output compare 5 interrupt control bit.
Freescale Semiconductor, Inc...
IC1I–IC3I —Input Capture x Interrupt Enable
If the ICxF flag bit is set while the ICxI enable bit is set, a hardware interrupt sequence is requested.
TFLG1 —Timer Interrupt Flag 1
RESET:
$0023
Bit 7
6
5
4
3
2
1
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
OC1F–OC5F —Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F —Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL
IC1F–IC3F —Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
NOTE
Control bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1
enable the corresponding interrupt sources.
TMSK2 —Timer Interrupt Mask 2
RESET:
$0024
Bit 7
6
5
4
3
2
1
Bit 0
TOI
RTII
PAOVI
PAII
—
—
PR1
PR0
0
0
0
0
0
0
0
0
TOI —Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Timer overflow interrupt enabled
RTII —Real-Time Interrupt Enable
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to one.
PAOVI —Pulse Accumulator Overflow Interrupt Enable
Refer to 11 Pulse Accumulator.
PAII —Pulse Accumulator Interrupt Enable
Refer to 11 Pulse Accumulator.
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
NOTE
Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones
in TMSK2 enable the corresponding interrupt sources.
Bits [3:2] —Not implemented
Always read zero
Freescale Semiconductor, Inc...
PR[1:0] —Timer Prescaler Select
In normal modes, PR1 and PR0 can only be written once, and the write must occur within 64 cycles
after reset. Refer to Table 10 for specific timing values.
PR[1:0]
00
01
10
11
Prescaler
1
4
8
16
TFLG2 —Timer Interrupt Flag 2
RESET:
$0025
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
PAOVF
PAIF
—
—
—
—
0
0
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
TOF —Timer Overflow Flag
Set when TCNT changes from $FFFF to $0000
RTIF —Real-Time (Periodic) Interrupt Flag
0 = No RTI interrupt
1 = RTI interrupt request pending
PAOVF —Pulse Accumulator Overflow Flag
Refer to 11 Pulse Accumulator.
PAIF —Pulse Accumulator Input Edge Flag
Refer to 11 Pulse Accumulator.
Bits [3:0] —Not implemented
Always read zero
PACTL —Pulse Accumulator Control
RESET:
$0026
Bit 7
6
5
4
3
2
1
Bit 0
—
PAEN
PAMOD
PEDGE
—
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Bit 7 —Not implemented
Always read zero
PAEN —Pulse Accumulator System Enable
Refer to 11 Pulse Accumulator.
PAMOD —Pulse Accumulator Mode
Refer to 11 Pulse Accumulator.
M68HC11 K Series
MC68HC11KTS/D
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PEDGE —Pulse Accumulator Edge Control
Refer to 11 Pulse Accumulator.
Bit 3 —Not implemented
Always reads zero
I4/O5 —Input Capture 4/Output Compare 5
Configure TI4/O5 for input capture or output compare
0 = OC5 enabled
1 = IC4 enabled
RTR[1:0] —Real-Time Interrupt (RTI) Rate
Refer to 10.1 Real-Time Interrupt.
Freescale Semiconductor, Inc...
10.1 Real-Time Interrupt
These rates are a function of the MCU oscillator frequency and the value of the software-accessible
control bits, RTR1 and RTR0. These bits determine the rate at which interrupts are requested by the
RTI system. The RTI system is driven by an E divided by 213 rate clock compensated so that it is independent of the timer prescaler. The RTR1 and RTR0 control bits select an additional division factor. RTI
is set to its fastest rate by default out of reset and can be changed at any time.
Table 12 Real-Time Interrupt Rates (Period Length)
Period Length
RTR[1:0]
Selected
Period Length
E = 2.0 MHz
E = 3.0 MHz
E = 4.0 MHz
00
13 ÷E
2
4.096 ms
2.731 ms
2.048 ms
01
214 ÷Ε
8.192 ms
5.461 ms
4.096 ms
10
215 ÷Ε
16.384 ms
10.923 ms
8.192 ms
11
216 ÷Ε
32.768 ms
21.845 ms
16.383 ms
Table 13 Real-Time Interrupt Rates (Frequency)
Frequency
RTR[1:0]
Rate Selected
E = 2.0 MHz
E = 3.0 MHz
E = 4.0 MHz
00
E ÷213
244.141 Hz
366.211 Hz
488.281 Hz
01
E ÷214
122.070 Hz
183.105 Hz
244.141 Hz
10
E ÷215
61.035 Hz
91.553 Hz
122.070 Hz
11
E ÷216
30.518 Hz
45.776 Hz
61.035 Hz
MOTOROLA
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
11 Pulse Accumulator
M68HC11 K-series MCUs have an 8-bit counter that can be configured as a simple event counter or for
gated time accumulation. The counter can be read or written at any time.
The port A bit 7 I/O pin can be configured to act as a clock in event counting mode, or as a gate signal
to enable a free-running clock (E divided by 64) to the 8-bit counter in gated time accumulation mode.
Common XTAL Frequencies
8.0 MHz
12.0 MHz
(E)
2.0 MHz
3.0 MHz
(1/E)
500 ns
333 ns
Pulse Accumulator (Gated Mode)
32.0 µs
21.33 µs
(26/E)
14
8.192 ms
5.461 ms
(2 /E)
CPU Clock
Cycle Time
Overflow —
16.0 µs
4.096 ms
PAOVI
PAOVF
1
INTERRUPT
REQUESTS
PAII
PAIF
PAOVF
PAIF
PAOVI
PAII
E ÷ 64 CLOCK
(FROM MAIN TIMER)
2
TFLG2 INTERRUPT STATUS
TMSK2 INT ENABLES
PAI EDGE
PAEN
DISABLE
FLAG SETTING
OVERFLOW
PIN
PA7/
PAI/
OC1
2:1
MUX
INPUT BUFFER
AND
EDGE DETECTOR
FROM
DDRA7
PACNT 8-BIT COUNTER
ENABLE
DATA BUS
OUTPUT
BUFFER
FROM
MAIN TIMER
OC1
CLOCK
PAEN
PAEN
PAMOD
PEDGE
Freescale Semiconductor, Inc...
1 Count —
16.0 MHz
4.0 MHz
250 ns
PACTL CONTROL
INTERNAL
DATA BUS
Figure 18 Pulse Accumulator System Block Diagram
M68HC11 K Series
MC68HC11KTS/D
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TMSK2 —Timer Interrupt Mask 2
RESET:
$0024
Bit 7
6
5
4
3
2
1
Bit 0
TOI
RTII
PAOVI
PAII
—
—
PR1
PR0
0
0
0
0
0
0
0
0
TOI —Timer Overflow Interrupt Enable
Refer to 10 Main Timer.
RTII —Real-Time Interrupt Enable
Refer to 10 Main Timer.
Freescale Semiconductor, Inc...
PAOVI —Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Pulse accumulator overflow interrupt enabled
PAII —Pulse Accumulator Input Interrupt Enable
0 = Pulse accumulator input interrupt disabled
1 = Pulse accumulator input interrupt enabled if PAIF bit in TFLG2 register is set
Bits [3:2] —Not implemented
Always read zero
PR[1:0] —Timer Prescaler Select
Refer to 10 Main Timer.
NOTE
Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones
in TMSK2 enable the corresponding interrupt sources.
TFLG2 —Timer Interrupt Flag 2
RESET:
$0025
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
PAOVF
PAIF
—
—
—
—
0
0
0
0
0
0
0
0
Clear flags by writing a one to the corresponding bit position(s).
TOF —Timer Overflow Enable
Refer to 10 Main Timer.
RTIF —Real-Time Interrupt Flag
Refer to 10 Main Timer.
PAOVF —Pulse Accumulator Overflow Flag
Set when PACNT changes from $FF to $00
PAIF —Pulse Accumulator Input Edge Flag
Set each time a selected active edge is detected on the PAI input line
Bits [3:0] —Not implemented
Always read zero
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M68HC11 K Series
MC68HC11KTS/D
Freescale Semiconductor, Inc.
PACTL —Pulse Accumulator Control
RESET:
$0026
Bit 7
6
5
4
3
2
1
Bit 0
—
PAEN
PAMOD
PEDGE
—
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Bit 7 —Not implemented
Always reads zero
Freescale Semiconductor, Inc...
PAEN —Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD —Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE —Pulse Accumulator Edge Control
0 = In event mode, falling edges increment counter. In gated accumulation mode, high level enables
accumulator and falling edge sets PAIF.
1 = In event mode, rising edges increment counter. In gated accumulation mode, low level enables
accumulator and rising edge sets PAIF.
I4/O5 —Input Capture 4/Output Compare 5
Refer to 10 Main Timer.
RTR[1:0] —Real-Time Interrupt Rate
Refer to 10 Main Timer.
PACNT —Pulse Accumulator Counter
$0027
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Can be read and written.
M68HC11 K Series
MC68HC11KTS/D
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Freescale Semiconductor, Inc.
12 Pulse-Width Modulation Timer
M68HC11 K-series MCUs contains a PWM timer that is composed of a four-channel 8-bit modulator.
Each of the modulators can create independent continuous waveforms with software-selectable duty
rates from 0% to 100%.
The PWM provides up to four pulse-width modulated waveforms on port H pins. Each channel has its
own counter. Pairs of counters can be concatenated to create 16-bit PWM outputs based on 16-bit
counts. Three clock sources (A, B, and S) and a flexible clock select scheme give the PWM system a
wide range of frequencies.
Freescale Semiconductor, Inc...
Four control registers configure the PWM outputs —PWCLK, PWPOL, PWSCAL, and PWEN. The PWCLK register selects the prescale value for the PWM clock sources and enables the 16-bit PWM functions. The PWPOL register determines each channel's polarity and selects the clock source for each
channel. The PWSCAL register derives a user-scaled clock based on the A clock source, and the
PWEN register enables the PWM channels.
Each channel has a separate 8-bit counter, period register, and duty cycle register. The period and duty
cycle registers are double buffered so that if they are changed while the channel is enabled, the change
does not take effect until the counter rolls over or the channel is disabled. A new period or duty cycle
can be forced into effect immediately by writing to the period or duty cycle register and then writing to
the counter.
With channels configured for 8-bit mode and E = 4 MHz, PWM signals of 40 kHz (1% duty cycle resolution) to less than 10 Hz (approximately 0.4% duty cycle resolution) can be produced. By configuring
the channels for 16-bit mode with E = 4 MHz, PWM periods greater than one minute are possible.
In 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a PWM frequency of about 60 Hz). In the same system, a PWM frequency of 1 kHz corresponds to a duty cycle resolution of 0.025%.
MOTOROLA
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M68HC11 K Series
MC68HC11TS/D
Freescale Semiconductor, Inc.
MCU
E CLOCK
÷1
÷2
÷4
÷8
÷ 16
÷ 32
÷ 64
÷ 128
Freescale Semiconductor, Inc...
PCKB1
PCKB2
PCKB3
CLOCK S
÷2
8-BIT COMPARE =
PWSCAL
8
SELECT
RESET
8-BIT COUNTER
CLOCK A
PCKA1 PCKA2
CLOCK B
SELECT
PWEN3
PWEN4
CON34
CLOCK
SELECT
PCLK3
PCLK4
CNT3
PWCNT1
CNT4
PWCNT2
CNT1
CARRY
S
8
8
8-BIT COMPARE =
8-BIT COMPARE =
PWPER1
PWPER2
8-BIT COMPARE =
8-BIT COMPARE =
PWDTY1
PWDTY2
CNT2
PPOL1
CON12
RESET
RESET
PWEN1
PWEN2
CON12
CLOCK
SELECT
PCLK1
PCLK2
16-BIT
PWM
CONTROL
Q
R
Q
S
Q
MUX
BIT 0
PH0/
PW1
MUX
BIT 1
PH1/
PW2
Q
R
PPOL2
PWCNT3
PWCNT4
CARRY
RESET
RESET
PORT H
PIN
CONTROL
PPOL3
CON34
S
8
8
8-BIT COMPARE =
8-BIT COMPARE =
PWPER3
PWPER4
8-BIT COMPARE =
8-BIT COMPARE =
PWDTY3
PWDTY4
16-BIT
PWM
CONTROL
Q
R
Q
S
Q
R
MUX
BIT 2
PH2/
PW3
MUX
BIT 3
PH3/
PW4
Q
PPOL4
PWM
OUTPUT
PWDTY
PWPER
Figure 19 Pulse-Width Modulation Block Diagram
M68HC11 K Series
MC68HC11TS/D
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PWCLK —Pulse-Width Modulation Clock Select
$0060
Bit 7
6
5
4
3
2
1
Bit 0
CON34
CON12
PCKA2
PCKA1
—
PCKB3
PCKB2
PCKB1
0
0
0
0
0
0
0
0
RESET:
Freescale Semiconductor, Inc...
CON34 —Concatenate Channels 3 and 4
Channel 3 is high-order byte, and channel 4 is the low-order byte. The resulting output is available on
port H, pin 3. Clock source is determined by PCLK4.
0 = Channels 3 and 4 are separate 8-bit PWMs.
1 = Channels 3 and 4 are concatenated to create one 16-bit PWM channel.
CON12 —Concatenate Channels One and Two
Channel 1 is high-order byte, and channel 2 is the low-order byte. The resulting output is available on
port H, pin 1. Clock source is determined by PCLK2.
0 = Channels 1 and 2 are separate 8-bit PWMs.
1 = Channels 1 and 2 are concatenated to create one 16-bit PWM channel.
PCKA[2:1] —Prescaler for Clock A (See also PWSCAL register)
Determines the rate of clock A
PCKA[2:1]
00
01
10
11
Value of Clock A
E
E/2
E/4
E/8
PCKB[3:1]
000
001
010
011
100
101
110
111
Value of Clock B
E
E/2
E/4
E/8
E/16
E/32
E/64
E/128
Bit 3 —Not implemented
Always reads zero
PCKB[3:1] —Prescaler for Clock B
Determines the rate for clock B
PWPOL —Pulse-Width Modulation Timer Polarity
$0061
Bit 7
6
5
4
3
2
1
Bit 0
PCLK4
PCLK3
PCLK2
PCLK1
PPOL4
PPOL3
PPOL2
PPOL1
0
0
0
0
0
0
0
0
RESET:
PCLK4 —Pulse-Width Channel 4 Clock Select
0 = Clock B is source
1 = Clock S is source
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PCLK3 —Pulse-Width Channel 3 Clock Select
0 = Clock B is source
1 = Clock S is source
PCLK2 —Pulse-Width Channel 2 Clock Select
0 = Clock A is source
1 = Clock S is source
Freescale Semiconductor, Inc...
PCLK1 —Pulse-Width Channel 1 Clock Select
0 = Clock A is source
1 = Clock S is source
PPOL[4:1] —Pulse-Width Channel x Polarity
0 = PWM channel x output is low at the beginning of the clock cycle and goes high when duty count
is reached
1 = PWM channel x output is high at the beginning of the clock cycle and goes low when duty count
is reached
PWSCAL —Pulse-Width Modulation Timer Prescaler
RESET:
$0062
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by 2.
If PWSCAL = $00, divide clock A by 256, then divide the result by 2.
PWEN —Pulse-Width Modulation Timer Enable
RESET:
$0063
Bit 7
6
5
4
3
2
1
Bit 0
TPWSL
DISCP
—
—
PWEN4
PWEN3
PWEN2
PWEN1
0
0
0
0
0
0
0
0
TPWSL —PWM Scaled Clock Test Bit (TEST)
Factory test only
DISCP —Disable Compare Scaled E Clock (TEST)
Factory test only
Bits [5:4] —Not implemented
Always read zero
PWEN[4:1] —Pulse-Width Channel 4–1
0 = Channel disabled
1 = Channel enabled
PWCNT1–PWCNT4 —Pulse-Width Modulation Timer Counter 1 to 4
$0064–$0067
$0064
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT1
$0065
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT2
$0066
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT3
$0067
Bit 7
6
5
4
3
2
1
Bit 0
PWCNT4
RESET:
0
0
0
0
0
0
0
0
PWCNT1–PWCNT4
Begins count using whichever clock was selected
M68HC11 K Series
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PWPER1–PWPER4 —Pulse-Width Modulation Timer Period 1 to 4
$0068–$006B
$0068
Bit 7
6
5
4
3
2
1
Bit 0
PWPER1
$0069
Bit 7
6
5
4
3
2
1
Bit 0
PWPER2
$006A
Bit 7
6
5
4
3
2
1
Bit 0
PWPER3
$006B
Bit 7
6
5
4
3
2
1
Bit 0
PWPER4
RESET:
1
1
1
1
1
1
1
1
PWPER1–PWPER4
Determines period of associated PWM channel
Freescale Semiconductor, Inc...
PWDTY1–4 —Pulse-Width Modulation Timer Duty Cycle 1 to 4
$006C–$006F
Bit 7
6
5
4
3
2
1
Bit 0
$006C
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY1
$006D
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY2
$006E
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY3
$006F
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY4
RESET:
1
1
1
1
1
1
1
1
PWDTY1–4
Determines duty cycle of associated PWM channel
12.1 PWM Boundary Cases
Certain values written to PWM control registers, counters, etc. can cause outputs that are not what the
user might expect. These are referred to as boundary cases. Boundary cases occur when the user
specifies a value that is either a maximum or a minimum. This value combined with other conditions
causes unexpected behavior of the PWM system.
The following conditions always cause the corresponding output to be high:
PWDTYx = $00, PWPERx > $00, and PPOLx = 0
PWDTYx ≥PWPERx, and PPOLx = 1
PWPERx = $00 and PPOLx = 1
The following conditions always cause the corresponding output to be low:
PWDTYx = $00, PWPERx > $00, and PPOLx = 1
PWDTYx ≥PWPERx, and PPOLx = 0
PWPERx = $00 and PPOLx = 0
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M68HC11 K Series
MC68HC11TS/D
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
M68HC11 K Series
MC68HC11KTS/D
For More Information On This Product,
Go to: www.freescale.com
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MC68HC11KTS/D
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