Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit Analog-to-Digital Converters (ADCs) n n n 13-bit resolution The CDK1307 is a high performance ultra low power Analog-to-Digital Converter (ADC). The ADC employs internal reference circuitry, a CMOS control interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the complete full scale range. 10/20/40/65/80/100MSPS max sampling rate Ultra-Low Power Dissipation: 17/19/33/50/60/75mW n 72.4dB SNR at 80MSPS and 8MHz FIN n Internal reference circuitry n 1.8V core supply voltage n 1.7 – 3.6V I/O supply voltage n Parallel CMOS output n 40-pin QFN package n Pin compatible with CDK1308 Two idle modes with fast startup times exist. The entire chip can either be put in Standby Mode or Power Down mode. The two modes are optimized to allow the user to select the mode resulting in the smallest possible energy consumption during idle mode and startup. The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. APPLICATIONS n Medical Imaging n Portable Test Equipment n Digital Oscilloscopes n IF Communication Functional Block Diagram Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK1307ILP40 10MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307AILP40 20MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307BILP40 40MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307CILP40 65MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307DILP40 80MSPS QFN-40 Yes Yes -40°C to +85°C Tray CDK1307EILP40 100MSPS QFN-40 Yes Yes -40°C to +85°C Tray Moisture sensitivity level for all parts is MSL-2A. ©2009 CADEKA Microcircuits LLC www.cadeka.com Rev 1A Ordering Information CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs General Description FEATURES Data Sheet Pin Configuration SLP_N CM_EXTBC_0 CM_EXTBC_1 OVDD OVDD D_12 D_11 D_10 D_9 D_8 39 38 37 36 35 34 33 32 31 DVDD 1 30 D_7 CM_EXT 2 29 D_6 AVDD 3 28 D_5 AVDD 4 27 CLK_EXT IP 5 26 OVDD IN 6 25 OVDD AVDD 7 24 ORNG DVDDCLK 8 23 D_4 CLKP 9 22 D_3 CLKN 10 21 D_2 CDK1307 11 12 13 14 15 16 17 18 19 20 DVDD CLK_EXT_EN DFRMT PD_N OE_N DVDD OVDD OVDD D_0 D_1 QFN-40 CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs 40 QFN-40 Pin Assignments Pin No. Pin Name 0 VSS 1, 11, 16 DVDD 2 CM_EXT 3, 4, 7 AVDD Analog supply voltage, 1.8V 5, 6 IP, IN Analog input (non-inverting, inverting) 8 DVDDCLK 9 CLKP Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave) 10 CLKN Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground 12 CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high. 13 DFRMT Data format selection. 0: Offset Binary, 1: Two's Complement 14 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always apply Power Down mode before using Active Mode to reset chip. 15 OE_N Output Enable. Tristate when high 17, 18, 25, 26, 36, 37 OVDD I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V 19 D_0 Output Data (LSB, 13-bit output or 1Vpp full scale range) 20 D_1 Output Data (LSB, 12-bit output 2Vpp full scale range) 21 D_2 Output Data 22 D_3 Output Data Ground connection for all power domains. Exposed pad Digital and I/O-ring pre driver supply voltage, 1.8V Common Mode voltage output Clock circuitry supply voltage, 1.8V Rev 1A ©2009 CADEKA Microcircuits LLC Description www.cadeka.com 2 Data Sheet Pin Assignments (Continued) Pin No. Description 23 D_4 Output Data 24 ORNG Out of Range flag. High when input signal is out of range 27 CLK_EXT Output clock signal for data synchronization. CMOS levels 28 D_5 Output Data 29 D_6 Output Data 30 D_7 Output Data 31 D_8 Output Data 32 D_9 Output Data 33 D_10 Output Data 34 D_11 Output Data (MSB for 1Vpp full scale range, see Reference Voltages section) 35 D_12 Output Data (MSB for 2Vpp full scale range) 38, 39 CM_EXTBC_1, CM_EXTBC_0 40 SLP_N CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Pin Name Bias control bits for the buffer driving pin CM_EXT 00: OFF 01: 50μA 10: 500μA 11: 1mA Sleep Mode when low Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Min Max Unit AVDD DVDD AVSS, DVSSCK, DVSS, OVSS OVDD, OVSS CLKP, CLKN Analog inputs and outpts (IPx, INx) Digital inputs Digital outputs -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +2.3 +2.3 +0.3 +3.9 +3.9 +2.3 +3.9 +3.9 V V V V V V V V CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Parameter Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Min Typ -60 Max Unit TBD +150 °C °C J-STD-020 ESD Protection Product QFN-40 Human Body Model (HBM) 2kV Recommended Operating Conditions Parameter Min Operating Temperature Range -40 Typ Max Unit +85 °C Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units DC Accuracy Guaranteed Offset Error Midscale offset 1 -6 mV Gain Error Full scale range deviation from typical DNL Differential Non-Linearity 12-bit level ±0.2 6 %FS LSB INL Integral Non-Linearity 12-bit level ±0.6 LSB VCMO Common Mode Voltage Output VAVDD/2 V Analog Input VCMI Input Common Mode Analog input common mode voltage Full Scale Range, Normal Differential input voltage range, 2.0 Vpp Full Scale Range, Option Differential input voltage range, 1V (see section Reference Voltages) 1.0 Vpp Input Capacitance Differential input capacitance Bandwidth Input bandwidth, full power 500 AVDD, DVDD Core Supply Voltage Supply voltage to all 1.8V domain pins. See Pin Configuration and Description 1.7 1.8 2.0 V 2.5 3.6 V I/O Supply Voltage Output driver supply voltage (OVDD). Must be higher than or equal to Core Supply Voltage (VOVDD ≥ VOCVDD) 1.7 OVDD VFSR VCM -0.1 VCM +0.2 V 2 pF MHz Power Supply CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs No Missing Codes Rev 1A ©2009 CADEKA Microcircuits LLC www.cadeka.com 5 Data Sheet Electrical Characteristics - CDK1307A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR SINAD Signal to Noise Ratio Signal to Noise and Distortion Ratio 72.5 dBFS 72.2 dBFS FIN ≃ FS/2 72.1 dBFS FIN = 20MHz 71.6 dBFS FIN = 2MHz 72.4 dBFS FIN = 8MHz FIN = 8MHz 71.5 72.0 dBFS FIN ≃ FS/2 71 71.7 dBFS FIN = 20MHz 71.3 dBFS 87 dBc 85 dBc 80 dBc FIN = 20MHz 80 dBc FIN = 2MHz -90 dBc -95 dBc FIN ≃ FS/2 -95 dBc FIN = 20MHz -95 dBc FIN = 2MHz -87 dBc -85 dBc FIN ≃ FS/2 -80 dBc FIN = 20MHz -80 dBc FIN = 2MHz 11.7 bits FIN = 2MHz SFDR HD2 HD3 ENOB Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits FIN = 8MHz 75 FIN ≃ FS/2 FIN = 8MHz FIN = 8MHz FIN = 8MHz -85 -75 11.7 bits FIN ≃ FS/2 11.5 11.6 bits FIN = 20MHz 11.6 bits 7.8 mA Digital core supply 1.0 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 1.7 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 1.3 mA Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD Output Driver Supply Analog Power Dissipation mW Digital Power Dissipation 5.1 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 19.1 mW Power Down Dissipation Sleep Mode Power Dissipation, Sleep mode 9.9 µW 9.2 mW Rev 1A 14.0 OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC 20 MSPS 15 MSPS www.cadeka.com CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs FIN = 2MHz 6 Data Sheet Electrical Characteristics - CDK1307B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units Performance SNR SINAD Signal to Noise Ratio Signal to Noise and Distortion Ratio FIN = 8MHz 71.9 FIN ≃ FS/2 HD2 HD3 ENOB Spurious Free Dynamic Range Second order Harmonic Distortion Third order Harmonic Distortion Effective number of Bits dBFS 72.7 dBFS 72 dBFS FIN = 30MHz 70.8 dBFS FIN = 2MHz 71.7 dBFS FIN = 8MHz 72.1 dBFS FIN ≃ FS/2 71 71.5 dBFS FIN = 30MHz 71.2 dBFS 81 dBc 81 dBc 80 dBc FIN = 30MHz 80 dBc FIN = 2MHz -90 dBc -95 dBc FIN ≃ FS/2 -95 dBc FIN = 30MHz -90 dBc FIN = 2MHz -81 dBc FIN = 8MHz -81 dBc FIN = 2MHz SFDR 72.5 FIN = 8MHz 75 FIN ≃ FS/2 FIN = 8MHz FIN ≃ FS/2 -85 -80 dBc FIN = 30MHz -80 dBc FIN = 2MHz 11.6 bits FIN = 8MHz -75 11.7 bits FIN ≃ FS/2 11.5 11.6 bits FIN = 30MHz 11.4 bits Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD Output Driver Supply 13.4 mA Digital core supply 1.7 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 3.3 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 2.4 mA Analog Power Dissipation mW Digital Power Dissipation 9.1 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 33.2 mW 9.7 µW Power Dissipation, Sleep mode 14.2 mW Power Down Dissipation Sleep Mode Rev 1A 24.1 OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC 40 MSPS 20 MSPS www.cadeka.com CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs FIN = 2MHz 7 Data Sheet Electrical Characteristics - CDK1307C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min Typ FIN = 8MHz 71.6 Max Units Performance Signal to Noise Ratio dBFS 71.8 dBFS FIN ≃ FS/2 71.5 dBFS FIN = 40MHz 70.4 dBFS 71.7 dBFS FIN = 20MHz 71.7 dBFS FIN ≃ FS/2 71.1 dBFS 70 dBFS FIN = 8MHz SINAD Signal to Noise and Distortion Ratio 70.5 FIN = 40MHz FIN = 8MHz SFDR Spurious Free Dynamic Range 81 dBc FIN = 20MHz 75 84 dBc FIN ≃ FS/2 79 dBc FIN = 40MHz 77 dBc -95 dBc FIN = 20MHz -95 dBc FIN ≃ FS/2 -95 dBc FIN = 40MHz -95 dBc -81 dBc FIN = 20MHz -84 dBc FIN ≃ FS/2 -79 dBc FIN = 40MHz -79 dBc 11.6 bits FIN = 20MHz 11.6 bits FIN ≃ FS/2 11.5 bits FIN = 40MHz 11.3 bits FIN = 8MHz HD2 Second order Harmonic Distortion FIN = 8MHz HD3 Third order Harmonic Distortion FIN = 8MHz ENOB Effective number of Bits -85 -75 11.4 Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD mA 2.3 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 5.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 3.5 mA 36.7 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 12.9 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 49.6 mW 9.3 µW Power Dissipation, Sleep mode 20.4 mW Output Driver Supply Analog Power Dissipation Power Down Dissipation Sleep Mode Rev 1A 20.4 Digital core supply Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC 65 MSPS 40 MSPS www.cadeka.com CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs SNR 72.6 FIN = 20MHz 8 Data Sheet Electrical Characteristics - CDK1307D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Conditions Min FIN = 8MHz 70.4 Typ Max Units Performance Signal to Noise Ratio dBFS 71.7 dBFS FIN = 30MHz 71.2 dBFS FIN ≃ FS/2 70.7 dBFS 70.5 dBFS FIN = 20MHz 70.5 dBFS FIN = 30MHz 70.5 dBFS FIN ≃ FS/2 70.3 dBFS FIN = 8MHz SINAD Signal to Noise and Distortion Ratio FIN = 8MHz SFDR Spurious Free Dynamic Range 69.5 77 dBc FIN = 20MHz 74 78 dBc FIN = 30MHz 78 dBc FIN ≃ FS/2 78 dBc -95 dBc FIN = 20MHz -90 dBc FIN = 30MHz -90 dBc FIN ≃ FS/2 -85 dBc -77 dBc FIN = 20MHz -78 dBc FIN = 30MHz -78 dBc FIN ≃ FS/2 -78 dBc 11.4 bits FIN = 20MHz 11.4 bits FIN = 30MHz 11.4 bits FIN ≃ FS/2 11.4 bits FIN = 8MHz HD2 Second order Harmonic Distortion FIN = 8MHz HD3 Third order Harmonic Distortion FIN = 8MHz ENOB Effective number of Bits -80 -74 11.3 Power Supply AIDD Analog Supply Current DIDD Digital Supply Current OIDD mA 2.9 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT enabled 6.1 mA 2.5V output driver supply, sine wave input, FIN = 1MHz, CLK_EXT disabled 4.1 mA 44.1 mW Digital Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 15.5 mW Total Power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1MHz, CLK_EXT disabled 59.6 mW 9.1 µW Power Dissipation, Sleep mode 24.1 mW Output Driver Supply Analog Power Dissipation Power Down Dissipation Sleep Mode Rev 1A 24.5 Digital core supply Clock Inputs Max. Conversion Rate Min. Conversion Rate ©2009 CADEKA Microcircuits LLC 80 MSPS 65 MSPS www.cadeka.com CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs SNR 72 FIN = 20MHz 9 Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 80 % high Clock Inputs 20 Compliance Input Range CMOS, LVDS, LVPECL, Sine Wave Differential input swing 400 Differential input swing, sine wave clock input 1.6 Input Common Mode Voltage Keep voltages within ground and voltage of OVDD Input Capacitance Differential TPD Start Up Time from Power Down From Power Down Mode to Active Mode TSLP Start Up Time from Sleep From Sleep Mode to Active Mode TOVR Out Of Range Recovery Time TAP εRMS mVpp Vpp 0.3 VOVDD -0.3 V 2 pF Timing 900 20 clk cycles clk cycles 1 clk cycles Aperture Delay 0.8 ns Aperture Jitter <0.5 ps TLAT Pipeline Delay 12 clk cycles TD Output Delay TDC Output Delay Relative to CLK_EXT 5pF load on output bits (see timing diagram) 3 10 ns See timing diagram 1 6 ns Logic Inputs VIH High Level Input Voltage VOVDD ≥ 3.0V VOVDD = 1.7V – 3.0V VOVDD ≥ 3.0V 2 V 0.8 • VOVDD V 0 0.8 V VIL Low Level Input Voltage 0 0.2 • VOVDD V IIH High Level Input Leakage Current -10 10 μA IIL Low Level Input Leakage Current -10 10 μA CI Input Capacitance VOVDD = 1.7V – 3.0V 3 pF Logic Outputs VOH High Level Output Voltage VOL Low Level Output Voltage CL Max Capacitive Load -0.1 +VOVDD V Post-driver supply voltage equal to pre-driver supply voltage VOVDD = VVDVDD Post-driver supply voltage above 2.25V (1) 0.1 V 5 pF 10 pF Note: ©2009 CADEKA Microcircuits LLC www.cadeka.com Rev 1A (1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Duty Cycle 10 Data Sheet N+3 N+4 N+5 N+2 N N+1 CLK_EXT Figure 1. Timing Diagram Recommended Usage DC-Coupling Analog Input Figure 3 shows a recommended configuration for DCcoupling. Note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_EXT output should be used as a reference to set the common mode voltage. The analog inputs to the CDK1307 is a switched capacitor track-and-hold amplifier optimized for differential operation. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The CM_EXT pin provides a voltage suitable as common mode voltage reference. The internal buffer for the CM_EXT voltage can be switched off, and driving capabilities can be changed by using the CM_EXTBC control input. 43Ω 33pF 43Ω Rev 1A Figure 2 shows a simplified drawing of the input network. The signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22Ω) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. The resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. The input amplifier could be inside a companion chip or it could be a dedicated amplifier. Several suitable single ended to differential driver amplifiers exist in the market. The system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with the CDK1307 input specifications. Figure 3. DC-Coupled Input Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in Figure 3 must be varied according to the recommendations for the driver. AC-Coupling Figure 2. Input Configuration ©2009 CADEKA Microcircuits LLC CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs N-13 A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 4 shows www.cadeka.com 11 Data Sheet 33Ω RT 47Ω Note that startup time from Sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. If the input signal has a long traveling distance, and the kick-backs from the ADC not are effectively terminated at the signal source, the input network of Figure 6 can be used. The configuration is designed to attenuate the kickback from the ADC and to provide an input impedance that looks as resistive as possible for frequencies below Nyquist. Values of the series inductor will however depend on board design and conversion rate. In some instances a shunt capacitor in parallel with the termination resistor (e.g. 33pF) may improve ADC performance further. This capacitor attenuate the ADC kick-back even more, and minimize the kicks traveling towards the source. However, the impedance match seen into the transformer becomes worse. 120nH 33Ω 1:1 optional RT 68Ω 220Ω pF 120nH 33Ω Figure 4. Transformer-Coupled Input Ω pF Ω Figure 5. AC-Coupled Input ©2009 CADEKA Microcircuits LLC Figure 6. Alternative Input Network Clock Input And Jitter Considerations Typically high-speed ADCs use both clock edges to generate internal timing signals. In the CDK1307 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, and hence a wide common mode voltage range is accepted. Differential clock sources as LVDS, LVPECL or differential sine wave can be connected directly to the input pins. For CMOS inputs, the CLKN pin should be connected to ground, and the CMOS clock signal should be connected to CLKP. For differential sine wave clock input the amplitude must be at least ±800mVpp. www.cadeka.com 12 Rev 1A Figure 5 shows AC-coupling using capacitors. Resistors from the CM_EXT output, RCM, should be used to bias the differential input signals to the correct voltage. The series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. 33Ω CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. The bandwidth should exceed the sampling rate of the ADC with at least a factor of 10. It is also important to keep phase mismatch between the differential ADC inputs small for good HD2 performance. This type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kickbacks from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. This could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. If this problem could not be avoided, the circuit in Figure 6 can be used. Data Sheet The quality of the input clock is extremely important for high-speed, high-resolution ADCs. The contribution to SNR from clock jitter with a full scale signal at a given frequency is shown in the equation below: • π • FIN • εt) where FIN is the signal frequency, and εt is the total rms jitter measured in seconds. The rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. This can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. The jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LVDS or LVPECL clock with fast edges. CMOS and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be retimed with a low jitter master clock as the last operation before it is applied to the ADC clock input. Digital Outputs ©2009 CADEKA Microcircuits LLC The CDK1307 employs digital offset correction. This means that the output code will be 4096 with shorted inputs. However, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also results in possible loss of codes at the edges of the full scale range. With no offset correction, the ADC would clip in one end before the other, in practice resulting in code loss at the opposite end. With the output being centered digitally, the output will clip, and the out of range flags will be set, before max code is reached. When out of range flags are set, the code is forced to all ones for over-range and all zeros for under-range. Data Format Selection The output data are presented on offset binary form when DFRMT is low (connect to OVSS). Setting DFRMT high (connect to OVDD) results in 2’s complement output format. Details are shown in Table 1 on page 14. The data outputs can be used in three different configurations. Normal mode: All 13-bits are used. MSB is D_12 and LSB is D_0. This mode gives optimum performance due to reduced quantization noise. 12-bit mode: The LSB is left unconnected such that only 12 bits are used. MSB is D_12 and LSB is D_1. This mode gives slightly reduced performance, due to increased quantization noise. Reduced full scale range mode: The full scale range is reduced from 2Vpp to 1Vpp which is equivalent to 6dB gain in the ADC frontend. MSB is D_11 and LSB is D_0. Note that the codes will wrap around when exceeding the full scale range, and that out of range bits should be used to clamp output data. See section Reference Voltages for details. This mode gives slightly reduced performance. www.cadeka.com 13 Rev 1A Digital output data are presented on parallel CMOS form. The voltage on the OVDD pin set the levels of the CMOS outputs. The output drivers are dimensioned to drive a wide range of loads for OVDD above 2.25V, but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. In applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the ADC chip. The digital outputs can be set in tristate mode by setting the OE_N signal high. CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs SNRjitter = 20 • log (2 The timing is described in the Timing Diagram section. Note that the load or equivalent delay on CK_EXT always should be lower than the load on data outputs to ensure sufficient timing margins. Data Sheet Table 1: Data Format Description for 2Vpp Full Scale Range Output Data: D_12 : D_0 (DFRMT = 0, offset binary) (DFRMT = 1, 2’s complement) 1.0 V 1 1111 1111 1111 0 1111 1111 1111 +0.24mV 1 0000 0000 0000 0 0000 0000 0000 -0.24mV 0 1111 1111 1111 1 1111 1111 1111 -1.0V 0 0000 0000 0000 1 0000 0000 0000 Reference Voltages Operational Modes The reference voltages are internally generated and buffered based on a bandgap voltage reference. No external decoupling is necessary, and the reference voltages are not available externally. This simplifies usage of the ADC since two extremely sensitive pins, otherwise needed, are removed from the interface. The operational modes are controlled with the PD_N and SLP_N pins. If PD_N is set low, all other control pins are overridden and the chip is set in Power Down mode. In this mode all circuitry is completely turned off and the internal clock is disabled. Hence, only leakage current contributes to the Power Down Dissipation. The startup time from this mode is longer than for other idle modes as all references need to settle to their final values before normal operation can resume. If a lower full scale range is required the 13-bit output word provides sufficient resolution to perform digital scaling with an equivalent impact on noise compared to adjusting the reference voltages. A simple way to obtain 1.0Vpp input range with a 12-bit output word is shown in the Table 2 below. Note that only 2‘s complement output data are available in this mode and that out of range conditions must be determined based on a two bit output. The output code will wrap around when the code goes outside the full scale range. The out of range bits should be used to clamp the output data for overrange conditions. The SLP_N bus can be used to power down each channel independently, or to set the full chip in Sleep Mode. In this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. However, Sleep Mode represents a significant reduction in supply current, and it can be used to save power even for short idle periods. The input clock could be kept running in all idle modes. However, even lower power dissipation is possible in Power Down mode if the input clock is stopped. In this case it is important to start the input clock prior to enabling active mode. Table 2: Data Format Description for 1Vpp Full Scale Range Output data: D_11: D_0 (DFRMT = 0) > 0.5V 0111 1111 1111 0.5V 0111 1111 1111 0111 1111 1111 +0.24mV 0000 0000 0000 0000 0000 0000 -0.24mV 1111 1111 1111 1111 1111 1111 -0.5V 1000 0000 0000 1000 0000 0000 < -0.5V 1000 0000 0000 (2’s Complement) ©2009 CADEKA Microcircuits LLC Out of Range (Use Logical AND Function for &) D_12 = 1 & D_11 = 1 D_12 = 0 & D_11 = 0 Output Data: D_11: D_0 (DFRMT = 1) (2’s Complement) 0111 1111 1111 1000 0000 0000 Out of Range (Use Logical AND Function for &) D_12 = 0 & D_11 = 1 D_12 = 1 & D_11 = 0 www.cadeka.com 14 Rev 1A Differential Input Voltage (IP - IN) CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Output data: D_12 : D_0 Differential Input Voltage (IP - IN) Data Sheet Mechanical Dimensions QFN-40 Package D D2 1.14 Pin 1 ID - Dia. R F A G A3 0.45 A1 Pin 0 Exposed Pad Min – 0.001 – 0.008 0.156 0.012 0° 0.008 0.0096 0.004 Inches Typ – 0.0004 0.023 0.008 REF 0.010 0.236 BSC 0.226 BSC 0.162 0.016 0.020 BSC – – 0.0168 0.008 Max 0.035 0.002 0.028 Min – 0.00 – 0.013 0.2 0.167 0.020 3.95 0.3 12° – 0.024 – 0° 0.2 0.24 0.1 Millimeters Typ – 0.01 0.65 0.2 REF 0.25 6.00 BSC 5.75 BSC 4.10 0.4 0.50 BSC – – 0.42 0.2 Max 0.9 0.05 0.7 0.32 4.25 0.5 12° – 0.6 – NOTE: D D2 D1 Package dimensions in millimeter unless otherwise noted. θ1 L e b A2 CDK1307 Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs Pin 1 ID - Dia. 0.5 (Top Side) Symbol A A1 A2 A3 b D D1 D2 L e θ1 F G R Rev 1A For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e