Micrel MIC3002 Fom management ic with internal calibration Datasheet

MIC3002
FOM Management IC with Internal
Calibration
General Description
Features
The MIC3002 is a fiber optic module controller which enables
the implementation of sophisticated, hot-pluggable fiber optic
transceivers with intelligent laser control and an internally
calibrated Digital Diagnostic Monitoring Interface per SFF8472. It essentially integrates all non-datapath functions of an
SFP transceiver into a tiny (4mm x 4mm) QFN package. It
also works well as a microcontroller peripheral in
transponders or 10Gbps transceivers.
A highly configurable automatic power control (APC) circuit
controls laser bias. Bias and modulation are temperature
compensated using dual DACs, an on-chip temperature
sensor, and NVRAM look-up tables. A programmable
internal feedback resistor provides a wide dynamic range for
the APC. Controlled laser turn-on facilitates hot plugging.
An analog-to-digital converter converts the measured
temperature, voltage, bias current, transmit power, and
received power from analog to digital. An EEPOT provides
front-end adjustment of RX power. Each parameter is
compared against user-programmed warning and alarm
thresholds. Analog comparators and DACs provide highspeed monitoring of received power and critical laser
operating parameters. Data can be reported as either
internally calibrated or externally calibrated.
An interrupt output, power-on hour meter, and data-ready
bits add user friendliness beyond SFF-8472. The interrupt
output and data-ready bits reduce overhead in the host
system. The power-on hour meter logs operating hours using
an internal real-time clock and stores the result in NVRAM.
In addition to the features listed above which are already
implemented in the previous controller MIC3001, the
MIC3002 features an extensive temperature range, options
to mask alarms and warnings interrupt and TXFAULT, and
ability to support up to four chips with the same address on
the serial interface.
Communication with the MIC3002 is via an industry standard
2-wire serial interface. Nonvolatile memory is provided for
serial ID, configuration, and separate OEM and user
scratchpad spaces. Two-level password protection guards
against data corruption.
• Extensive temperature range
• Alarms and Warnings interrupt and TXFAULT masks
• Capability to support up to four chips on the serial
interface
• LUT to compensate for chip-FOM case temperature
difference
• APC or constant-current laser bias
• Turbo mode for APC loop start-up and shorter laser turn
on time
• Supports multiple laser types and bias circuit topologies
• Integrated digital temperature sensor
• Temperature compensation of modulation, bias, and
fault levels via NVRAM look-up tables
• NVRAM to support GBIC/SFP serial ID function
• User writable EEPROM scratchpad
• Diagnostic monitoring interface per SFF-8472
– Monitors and reports critical parameters:
temperature, bias current, TX and RX optical power,
and supply voltage
– S/W control and monitoring of TXFAULT, RXLOS,
RATESELECT, and TXDISABLE
– Internal or external calibration
– EEPOT for adjusting RX power measurement
• Power-on hour meter
• Interrupt capability
• Extensive test and calibration features
• 2-wire SMBus-compatible serial interface
• SFP/SFP+ MSA and SFF-8472 compliant
• 3.0V to 3.6V power supply range
• 5V-tolerant I/O
• Available in (4mm x 4mm) 24-pin QFN package
Applications
•
•
•
•
•
•
SFP/SFP+ optical transceivers
SONET/SDH transceivers and transponders
Fibre Channel transceivers
10Gbps transceivers
Free space optical communications
Proprietary optical links
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 2007
M9999-073107-B
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Micrel, Inc.
MIC3002
Ordering Information
Part Number
Package Type
Junction Temp. Range
Package Marking
Lead Finish
24-pin QFN
–45°C to +105°C
3002
Sn-Pb
MIC3002BMLTR
24-pin QFN
–45°C to +105°C
3002
Sn-Pb
MIC3002GML
24-pin QFN
–45°C to +105°C
3002
with Pb-Free bar-line indicator
Pb-Free
NiPdAu
24-pin QFN
–45°C to +105°C
3002
with Pb-Free bar-line indicator
Pb-Free
NiPdAu
MIC3002BML
(1)
(1)
MIC3002GMLTR
1. Note:
2. Tape and Reel.
July 2007
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MIC3002
Contents
Pin Configuration ............................................................................................................................................................. 7
Pin Description ................................................................................................................................................................ 7
Absolute Maximum Ratings ............................................................................................................................................ 9
Operating Ratings ........................................................................................................................................................... 9
Electrical Characteristics ................................................................................................................................................. 9
Timing Diagram ............................................................................................................................................................. 14
Address Map ................................................................................................................................................................. 15
Block Diagram ............................................................................................................................................................... 18
Analog-to-Digital Converter/Signal Monitoring .............................................................................................................. 18
Temperature Reading Compensation ........................................................................................................................... 19
Alarms and Warnings Interrupt Source Masking .......................................................................................................... 20
Alarms and Warnings as TXFAULT Source ................................................................................................................. 21
Alarms and Warnings Latch .......................................................................................................................................... 21
SMBus Multipart Support .............................................................................................................................................. 21
Calibration Modes ......................................................................................................................................................... 22
A/ External Calibration ............................................................................................................................................ 22
Voltage .................................................................................................................................................................... 22
Temperature ........................................................................................................................................................... 22
Bias Current ............................................................................................................................................................ 22
TX Power ................................................................................................................................................................ 22
RX Power ................................................................................................................................................................ 23
B/ Internal Calibration ............................................................................................................................................. 23
Temperature Offset................................................................................................................................................. 25
C/ ADC Result Registers Reading .......................................................................................................................... 25
RXPOT ......................................................................................................................................................................... 25
Laser Diode Bias Control .............................................................................................................................................. 25
Laser Modulation Control .............................................................................................................................................. 26
Power ON and Laser Start-Up ...................................................................................................................................... 27
Fault Comparators ........................................................................................................................................................ 28
SHDN and TXFIN .......................................................................................................................................................... 29
Temperature Measurement........................................................................................................................................... 29
Diode Faults .................................................................................................................................................................. 29
Temperature Compensation ......................................................................................................................................... 29
Alarms and Warning Flags ............................................................................................................................................ 32
Control and Status I/O ................................................................................................................................................... 32
System Timing............................................................................................................................................................... 34
Warm Resets................................................................................................................................................................. 36
Power-On Hour Meter ................................................................................................................................................... 36
Test and Calibration Features ....................................................................................................................................... 37
Serial Port Operation ..................................................................................................................................................... 38
Page Writes ................................................................................................................................................................... 38
Acknowledge Polling ....................................................................................................................................................... 39
Write Protection and Data Security .................................................................................................................................. 39
OEM Password ........................................................................................................................................................ 39
User Password......................................................................................................................................................... 39
July 2007
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MIC3002
Detailed Register Descriptions ...................................................................................................................................... 40
Alarm Threshold Registers ............................................................................................................................................ 40
Warning Threshold Registers........................................................................................................................................ 43
ADC Result Registers ................................................................................................................................................... 45
Alarm Flags ................................................................................................................................................................... 48
Warning Flags ............................................................................................................................................................... 49
Warning Status Register 0 (WARN0) ............................................................................................................................ 49
Warning Status Register 1 (WARN1) ............................................................................................................................ 49
OEM Password Entry (OEMPW) .................................................................................................................................. 50
USER Password Setting (USRPWSET) ....................................................................................................................... 50
USER Password (USRPW)........................................................................................................................................... 51
Power-On Hours ........................................................................................................................................................... 51
Data Ready Flags (DATARDY) ..................................................................................................................................... 51
USER Control Register (USRCTL) ............................................................................................................................... 52
OEM Configuration Register 0 (OEMCFG0) ................................................................................................................. 52
OEM Configuration Register 1 (OEMCFG1) ................................................................................................................. 53
OEM Configuration Register 2 (OEMCFG2) ................................................................................................................. 54
APC Setpoint x ............................................................................................................................................................. 54
Modulation Setpoint x ................................................................................................................................................... 54
IBIAS Fault Threshold (IBFLT)......................................................................................................................................... 55
Transmit Power Fault Threshold (TXFLT) .................................................................................................................... 55
Loss-Of-Signal Threshold (LOSFLT) ............................................................................................................................ 55
Fault Suppression Timer (FLTTMR) ............................................................................................................................. 55
Fault Mask (FLTMSK) ................................................................................................................................................... 56
OEM Password Setting (OEMPWSET) ........................................................................................................................ 56
OEM Calibration 0 (OEMCAL0) .................................................................................................................................... 57
OEM Calibration 1 (OEMCAL1) .................................................................................................................................... 57
OEM Calibration 1 (LUT Index) ..................................................................................................................................... 58
OEM Configuration 3 (OEMCFG3) ............................................................................................................................... 58
BIAS DAC Setting (APCDAC) Current VBIAS Setting .................................................................................................. 58
Modulation DAC Setting (MODDAC) Current VMOD Setting ....................................................................................... 59
OEM Readback Register (OEMRD) ............................................................................................................................. 59
Signal Detect Threshold (LOSFLTn) ............................................................................................................................. 59
RX EEPOT Tap Selection (RXPOT) ............................................................................................................................. 60
OEM Configuration 4 (OEMCFG4) ............................................................................................................................... 60
OEM Configuration 5 (OEMCFG5) ............................................................................................................................... 61
OEM Configuration 6 (OEMCFG6) ............................................................................................................................... 62
Power-On Hour Meter Data (POHDATA) ..................................................................................................................... 62
OEM Scratchpad Registers (SCRATCHn) .................................................................................................................... 63
RX Power Look-up Table (RXLUTn) ............................................................................................................................. 63
Calibration Constants (CALn) ....................................................................................................................................... 63
Manufacturer ID Register .............................................................................................................................................. 64
Device ID Register ....................................................................................................................................................... 64
Package Information ..................................................................................................................................................... 65
July 2007
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MIC3002
List of Figures
Figure 1. MIC3002 Block Diagram ................................................................................................................................ 18
Figure 2. Analog-to-Digital Converter Block Diagram ................................................................................................... 18
Figure 3. Internal Calibration RX Power Linear Approximation .................................................................................... 25
Figure 4. RXPOT Block Diagram .................................................................................................................................. 25
Figure 5. MIC3002 APC and Modulation Control Block Diagram ................................................................................ 26
Figure 6. Programmable Feedback Resistor ................................................................................................................ 26
Figure 7. Transmitter Configurations Supported by MIC3002 ..................................................................................... 26
Figure 8. VMOD Configured as Voltage Output with Gain .......................................................................................... 27
Figure 9. MIC3002 Power-ON Timing .......................................................................................................................... 28
Figure 10. Fault Comparator Logic ............................................................................................................................... 28
Figure 11. Saturation Detector ...................................................................................................................................... 29
Figure 12. RXLOS Comparator Logic ........................................................................................................................... 29
Figure 13. Control and Status I/O Logic ........................................................................................................................ 33
Figure 14. Transmitter ON-OFF Timing ....................................................................................................................... 34
Figure 15. Initialization Timing with TXDISABLE Asserted .......................................................................................... 34
Figure 16. Initialization Timing with TXDISABLE Not Asserted .................................................................................. 34
Figure 17. Loss-of-Signal (LOS) Timing ...................................................................................................................... 35
Figure 18. Transmit Fault Timing .................................................................................................................................. 28
Figure 19. Successfully Clearing a Fault Condition ..................................................................................................... 36
Figure 20. Unsuccessful Attempt to Clear a Fault ....................................................................................................... 36
Figure 21. Write Byte Protocol ..................................................................................................................................... 38
Figure 22. Read Byte Protocol ..................................................................................................................................... 38
Figure 23. Read_Word Protocol................................................................................................................................... 38
Figure 24. Four-Byte Page_White Protocol ................................................................................................................. 39
July 2007
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MIC3002
List of Tables
Table 1. MIC3002 Address Map, Serial Address = A0h ................................................................................................ 15
Table 2. MIC3002 Address Map, Serial Address = A2h ................................................................................................ 15
Table 3. Temperature Compensation Tables, Serial Address = A4h ............................................................................ 16
Table 4. OEM Configuration Registers, Serial Address = A6h ...................................................................................... 17
Table 5. A/D Input Signal Ranges and Resolutions ...................................................................................................... 19
Table 6. VAUX Input Signal Ranges and Resolutions .................................................................................................... 19
Table 7. LUT for Temperature Reading Compensation ................................................................................................ 20
Table 8. Alarms Interrupt Sources Masking Bits ........................................................................................................... 20
Table 9. Warnings Interrupt Sources Masking Bits ....................................................................................................... 21
Table 10. LSB Values of Offset Coefficients ................................................................................................................. 23
Table 11. Internal Calibration Coefficient Memory Map – Part I ................................................................................... 24
Table 12. Internal Calibration Coefficient Memory Map – Part II .................................................................................. 24
Table 13. Shutdown State of SHDN vs. Configuration Bits ......................................................................................... 27
Table 14. Shutdown State of VBIAS vs. Configuration Bits ............................................................................................ 27
Table 15. Shutdown State of VMOD vs. Configuration Bits ............................................................................................ 27
Table 16. Temperature Compensation Look-up Tables ............................................................................................... 30
Table 17. APC Temperature Compensation Look-Up Table ....................................................................................... 31
Table 18. VMOD Temperature Compensation Look-Up Table....................................................................................... 31
Table 19. IBIAS Comparator Temperature Compensation Look-Up Table ..................................................................... 31
Table 20. BIAS Current High Alarm Temperature Compensation Table ...................................................................... 31
Table 22. MIC3002 Events ............................................................................................................................................ 33
Table 23. Power-On Hour Meter Result Format .......................................................................................................... 36
Table 24. Test and Diagnostic Features ...................................................................................................................... 37
July 2007
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MIC3002
Pin Configuration
24-Pin QFN
Pin Description
Pin Number
Pin Name
1
FB
2
VMPD
Analog Input. Multiplexed A/D converter input for monitoring transmitted optical power via a
monitor photodiode. In most applications, VMPD will be connected directly to FB. The input range
is 0 - VREF or 0 - VREF/4 depending on the setting of the APC configuration bits
3
GNDA
Ground return for analog functions.
4
VDDA
Power supply input for analog functions.
5
VILD–
Analog Input. Reference terminal for the multiplexed pseudo-differential A/D converter inputs for
monitoring laser bias current via a sense resistor (VILD+ is the sensing input). Tie to VDD or GND
to reference the voltage sensed on VILD+ to VDD or GND, respectively. Limited common-mode
voltage range, see “Applications Information” section for more details.
6
VILD+
Analog Input. Multiplexed A/D input for monitoring laser bias current via a sense resistor (signal
input); accommodates inputs referenced to VDD or GND (see pin 5 description). Limited commonmode voltage range, see “Applications Information” section for more details.
7
SHDN/TXFIN
Digital output/Input; programmable polarity. When used as shutdown output (SHDN), OEMCFG3-2
set to 0, SHDN is asserted at the detection of a fault condition if OEMCFG4-7 is set to 0. If the
latter bit is set to 1, a fault condition will not assert SHDN. When programmed as TXFIN, it is an
input for external fault signals to be ORed with the internal fault sources to drive TXFAULT.
8
VRX
Analog Input. Multiplexed A/D converter input for monitoring received optical power. The input
range is 0 to VREF. A 5-bit programmable EEPOT on this pin provides for coarse calibration and
ranging of the RX power measurement.
9
XPN
Analog Input/Output. Optional connection to an external PN junction for sensing temperature at a
remote location. The Zone bit in OEMCFG1 determines whether temperature is measured using
the on-chip sensor or the remote PN junction.
10
TXFAULT
Digital Output; Open-Drain, programmable polarity. If OEMCFG5-4 is set to 0, a high level
indicates a hardware fault impeding transmitter operation. The state of this pin is always reflected
in the TXFLT bit.
July 2007
Pin Function
Analog Input. Feedback voltage for the APC loop op-amp. Polarity and scale are programmable
via the APC configuration bits. Connect to VBIAS if APC is not used.
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MIC3002
Pin Description
Pin Number
Pin Name
11
TXDISABLE
12
DATA
13
CLK
14
VIN/INT
15
RSIN
Digital Input; Rate Select Input; ORed with rate select bit to determine the state of the RSOUT pin.
The state of this pin is always reflected in the RSEL bit.
16
GNDD
Ground return for digital functions.
17
NC
18
VDDD
Power supply input for digital functions.
19
RXLOS
Digital Output; programmable polarity Open-Drain. Indicates the loss of the received signal as
indicated by a level of received optical power below the programmed RXLOS comparator
threshold; may be wire-ORed with external signals. Normal operation is indicated by a Low level
when OEMCFG6-3 is set to 0 and a high level when OEMCFG6-3 is set to 1. RXLOS is deasserted when VRX > LOSFLTn. The LOS bit reflects the state of RXLOS whether driven by the
MIC3002 or an external circuit.
20
RS0/GPO
Digital Output. Open-Drain or push-pull. When used as rate select output, it represents the
receiver rate select as per SFF. This output is controlled by the SRSEL bit ORed with RSIN input
and is open drain only. When used as a general-purpose, non-volatile output, it is controlled by
the GPO configuration bits in OEMCFG3.
21
COMP
Analog Output, compensation terminal. Connect a capacitor between this pin and GNDA or VDDA
with appropriate value to tune the APC loop time constant to a desirable value.
22
VBIAS
Analog Output. Buffered DAC output capable of sourcing or sinking up to 10mA under control of
the APC function to drive an external transistor for laser diode D.C. bias. The output and
feedback polarity are programmable to accommodate either a NPN or a PNP transistor to drive a
common-anode or common-cathode laser diode.
23
VMOD–
Analog Input. Inverting terminal of VMOD buffer op-amp. Connect to VMOD+ (gain = 1) or
feedback resistors network to set a different gain
24
VMOD+
Analog Output. Buffered DAC output to set the modulation current on the laser driver IC. Operates
with either a 0– VREF or a (VDD–VREF) – VDD output swing so as to generate either a groundreferenced or a VDD referenced programmed voltage. A simple external circuit can be used to
generate a programmable current for those drivers that require a current rather than a voltage
input. See “Applications Information” section for more details.
July 2007
Pin Function
Digital Input; Active High. The transmitter is disabled when this line is high or the STXDIS bit is
set. The state of this input is always reflected in the TXDIS bit.
Digital I/O; Open-drain. Bi-directional serial data input/output.
Digital Input; Serial clock input.
If bit 4 (IE) in USRCTL register is set to 0 (default), this pin is configured as analog input. If IE bit
is set to 1, this pin is configured as open-drain output. Analog Input: Multiplexed A/D input for
monitoring supply voltage. 0V to 5.5V input range. Open-drain output: outputs the internally
generated interrupt signal /INT.
No connection. This pin is used for test purposes and must be left unconnected.
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MIC3002
Absolute Maximum Ratings(1)
Operating Ratings(2)
Power Supply Voltage, VDD ................................. +3.8V
Voltage on CLK, DATA, TXFAULT, VIN, RXLOS,
DISABLE, RSIN ..................................–0.3V to +6.0V
Voltage On Any Other Pin ............... –0.3V to VDD+0.3V
Power Dissipation, TA = 85°C ............................... 1.5W
Junction Temperature (TJ) .................................. 150°C
Storage Temperature (TS) ................. –65°C to +150°C
Power Supply Voltage, VDDA/VDDD ..... +3.0V to +3.6V
Ambient Temperature Range (TA) ... –40°C to +105°C
Package Thermal Resistance
QFN (θJA) ............................................... 43°C/W
ESD Ratings(3)
Human Body Model ............................................. 2kV
Machine Model .................................................. 300V
Soldering (20sec) .................................................260ºC
Electrical Characteristics
For typical values, TA = 25°C, VDDA = VDDD = +3.3V, unless otherwise noted. Bold values are guaranteed for +3.0V ≤
(VDDA = VDDD) ≤ 3.6V, T(min) ≤ TA ≤ T(max)(8)
Symbol
Parameter
Condition
Min
Typ
Max
Units
CLK = DATA = VDDD = VDDA;
TXDISABLE low; all DACs at fullscale; all A/D inputs at full-scale; all
other pins open.
2.3
3.5
mA
CLK = DATA = VDDD = VDDA;
TXDISABLE high; FLTDAC at fullscale; all A/D inputs at full-scale; all
other pins open.
2.3
3.5
mA
2.9
2.98
V
Power Supply
IDD
Supply Current
VPOR
Power-on Reset Voltage
All registers reset to default values;
A/D conversions initiated.
VUVLO
Under-Voltage Lockout Threshold
Note 5
VHYST
Power-on Reset Hysteresis Voltage
tPOR
Power-on Reset Time
VREF
Reference Voltage
∆VREF/∆VDDA
Voltage Reference Line Regulation
2.5
VDD > VPOR(4)
1.210
2.73
V
170
mV
50
µs
1.225
1.240
1.7
V
mV/V
Temperature-to-Digital Converter Characteristics
Local Temperature Measurement
Error
–40°C ≤ TA ≤ +105°C(6)
±1
±3
°C
Remote Temperature
Measurement Error
–40°C ≤ TA ≤ +105°C(6)
±1
±3
°C
tCONV
Conversion Time
Note 4
60
ms
tSAMPLE
Sample Period
100
ms
Remote Temperature Input, XPN
IF
Current to External Diode(4)
XPN at high level, clamped to 0.6V.
XPN at low level, clamped to 0.6V.
July 2007
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192
7
12
400
µA
µA
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MIC3002
Voltage-to-Digital Converter Characteristics (VRX, VAUX, VBIAS, VMPD, VILD±)
Symbol
Parameter
Condition
Voltage Measurement Error
–40°C ≤ TA ≤ +105°C(6)
Min
Typ
Max
Units
±1
±2.0
%fs
tCONV
Conversion Time
Note 4
10
ms
tSAMPLE
Sample Period
Note 4
100
ms
5.5
V
Voltage Input, VIN (Pin 14 used as an ADC Input)
VIN
Input Voltage Range
–0.3 ≤ VDD ≤ 3.6V
ILEAK
Input Current
VIN = VDD or GND; VAUX = VIN
CIN
nput Capacitance
GNDA
55
µA
10
pF
Digital-to-Voltage Converter Characteristics (VMOD, VBIAS)
Accuracy
–40°C ≤ TA ≤ +105°C(6)
tCONV
Conversion Time
Note 4
DNL
Differential Non-linearity Error
Note 4
±1
±0.5
2.0
%fs
20
ms
±1
LSB
VREF/4
mV
±1
µA
Bias Current Sense Inputs, VILD+, VILD–
VILD
Differential Input Signal Range,
| VILD+ – VILD– |
IIN+
VILD+ input current
IIN–
VILD– input current
VILD– referred to VDDA
+150
µA
| VILD+ – VILD– | = 0.3V
VILD– referred to GND
-150
µA
10
pF
1
MHz
1
µV/°C
CIN
0
Input Capacitance
APC Op Amp, FB, VBIAS, COMP
GBW
Gain Bandwidth Product
TCVOS
Input Offset Voltage Temperature
Coefficient(4)
VOUT
Output Voltage Swing
CCOMP = 20pF; Gain = 1
IOUT = 10mA, SRCE bit = 1
GNDA
1.25
V
IOUT = -10mA, SRCE bit = 0
VDDA -1.25
VDDA
V
ISC
Output Short-Circuit Current
tSC
Short Circuit Withstand Time
TJ ≤ 150°C(4)
PSRR
Power Supply Rejection Ratio
CCOMP = 20pF; Gain = 1, to GND
55
CCOMP = 20pF; Gain = 1, to VDD
40
AMIN
Minimum Stable Gain
CCOMP = 20pF, Note 4
∆V/∆t
Slew Rate
CCOMP = 20pF; Gain = 1
∆RFB
55
mA
sec
dB
1
V/V
3
V/µs
Internal Feedback Resistor Tolerance
±20
%
∆RFB/∆t
Internal Feedback Resistor
Temperature Coefficient
25
ppm/C
ISTART
Laser Start-up Current Magnitude
START = 01h
0.375
mA
START = 02h
0.750
mA
START = 04h
1.500
mA
START = 08h
3.000
mA
10
pF
CIN
July 2007
Pin Capacitance
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Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
VMOD Buffer Op-Amp, VMOD+, VMOD–
GBW
Gain Bandwidth
TCVOS
Input Offset Voltage
Temperature Coefficient
IBIAS
VMOD– Input Current
VOUT
Output Voltage Swing
ISC
Output Short-Circuit Current
CCOMP = 20pF; Gain = 1
1
MHz
1
µV/°C
±0.1
IOUT = ±1mA
GNDA+75
±1
µA
VDDA-75
mV
35
mA
150°C(4)
tSC
Short Circuit Withstand Time
TJ ≤
PSRR
Power Supply Rejection Ratio
CCOMP = 20pF; Gain = 1, to GND
65
dB
CCOMP = 20pF; Gain = 1, to VDD
44
dB
sec
AMIN
Minimum Stable Gain
CCOMP = 20pF
∆V/∆T
Slew Rate
CCOMP = 20pF; Gain = 1
CIN
Pin Capacitance
1
V/V
1
V/µs
10
pF
Control and Status I/O, TXDISABLE, TXFAULT, RSIN, RSOUT(GPO), SHDN(TXFIN), RXLOS, /INT
VIL
Low Input Voltage
VIH
High Input Voltage
VOL
Low Output Voltage
IOL ≤ 3mA
0.3
V
VOH
High Output Voltage
(applies to SHDN only)
IOH ≤ 3mA
VDDD–0.3
V
ILEAK
Input Current
±1
µA
CIN
Input Capacitance
0.8
2.0
V
V
10
pF
Transmit Optical Power Input, VMPD
VIN
Input Voltage Range
Note 4
VRX
Input Signal Range
BIASREF=0
GNDA
VDDA–VREF
BIASREF=1
CIN
Input Capacitance
ILEAK
Input Current
Note 4
VDDA
V
VREF
V
VDDA
V
10
pF
±1
µA
GNDA
VDDA
V
0
VREF
V
Received Optical Power Input, VRX, RXPOT
Input Voltage Range
VRX
Valid Input Signal Range
(ADC Input Range)
RRXPOT(32)
End-to-End Resistance
∆RXPOT
Note 4
RXPOT = 1Fh
32
KΩ
Resistor Tolerance
±20
%
∆RXPOT/∆T
Resistor Temperature
Coefficient
25
ppm/C
∆VRX/VRXPOT
Divider Ratio Accuracy
00 ≤ RXPOT ≤ 1Fh
ILEAK
Input Current
RXPOT = 0 (disconnected)
CIN
Input Capacitance
Note 4
ILEAK
Input Current
July 2007
-5
+5
%
±1
µA
10
pF
±1
11
µA
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MIC3002
Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Control and Status I/O Timing, TXFAULT, TXDISABLE, RSIN, RSOUT, and RXLOS
tOFF
TXDISABLE Assert Time
From input asserted to optical output
at 10% of nominal, CCOMP = 10nF.
10
µs
tON
TXDISABLE De-assert Time
From input de-asserted to optical
output at 90% of nominal, CCOMP =
10nF.
1
ms
tINIT
Initialization Time
From power on or transmitter enabled
to optical output at 90% of nominal
and TX_FAULT de-asserted.(4)
300
ms
tINIT2
Power-on Initialization Time
From power on to APC loop-enabled.
200
ms
tFAULT
TXFAULT Assert Time
From fault condition to TXFAULT
assertion.(4)
95
µs
tRESET
Fault Reset Time
Length of time TXDISABLE must be
asserted to reset fault condition.
tLOSS_ON
RXLOS Assert Time
From loss of signal to RXLOS
asserted.
95
µs
tLOSS_OFF
RXLOS De-assert Time
From signal acquisition to LOS deasserted.
100
µs
tDATA
Analog Parameter Data Ready
From power on to valid analog
parameter data available.(4)
400
ms
tPROP_IN
TXFAULT, TXDISABLE, RXLOS,
RSIN Input Propagation Time
Time from input change to
corresponding internal register bit set
or cleared.(4)
1
µs
tPROP_OUT
TXFAULT, RSOUT, /INT Output
Propagation Time
From an internal register bit set or
cleared to corresponding output
change.(4)
1
µs
0.525
ms
+3
%/F.S.
10
µs
Fault Comparators
φFLTTMR
Fault Suppression Timer Clock
Period
tREJECT
Glitch Rejection
VSAT
Saturation Detection Threshold
0.475
Note 4
Accuracy
0.5
-3
Maximum length pulse that will not
cause output to change state.(4)
4.5
µs
High level
95
%VDDA
Low level
5
%VDDA
Power-On Hour Meter
Timebase Accuracy
Resolution
0°C ≤ TA ≤ +70°C(4)
+5
-5
%
–40°C ≤ TA ≤ +105°C
+10
-10
%
Note 4
10
hours
Non-Volatile (FLASH) Memory
tWR
Write Cycle Time(7)
Data Retention
Endurance
July 2007
13
From STOP of a one to four-byte write
transaction.(4)
Minimum Permitted Number
Write Cycles
12
ms
100
years
10,000
cycles
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MIC3002
Serial Data I/O Pin, Data
Symbol
Parameter
Condition
VOL
Low Output Voltage
VIL
Low Input Voltage
VIH
High Input Voltage
ILEAK
Input Current
CIN
Input Capacitance
Min
Typ
Max
Units
IOL = 3mA
0.4
V
IOL = 6mA
0.6
V
0.8
V
2.1
V
±1
Note 4
10
µA
pF
Serial Clock Input, CLK
VIL
Low Input Voltage
2.7V ≤ VDD ≤ 3.6V
VIH
High Input Voltage
2.7V ≤ VDD ≤ 3.6V
ILEAK
Input Current
CIN
Input Capacitance
Serial Interface Timing
0.8
V
±1
µA
2.1
Note 4
V
10
pF
(4)
t1
CLK (clock) Period
2.5
µs
t2
Data In Setup Time to CLK High
100
ns
t3
Data Out Stable After CLK Low
300
ns
t4
Data Low Setup Time to CLK
Low
Start Condition
100
ns
t5
Data High Hold Time After CLK
High
Stop Condition
100
ns
tDATA
Data Ready Time
From power on to completion of one
set of ADC conversions; analog data
available via serial interface.
400
ms
Notes:
1.
Exceeding the absolute maximum rating may damage the device.
2.
The device is not guaranteed to function outside its operating rating.
3.
Devices are ESD sensitive. Handling precautions recommended.
4.
Guaranteed by designing and/or testing of related parameters. Not 100% tested in production.
5.
The MIC3000 will attempt to enter its shutdown state when VDD falls below VUVLO. This operation requires time to complete. If the supply voltage
falls too rapidly, the operation may not be completed.
6.
Does not include quantization error.
7.
The MIC3002 will not respond to serial bus transactions during an EEPROM write-cycle. The host will receive a NACK during tWR.
8.
Final test on outgoing product is performed at TA = +25°C.
July 2007
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MIC3002
Timing Diagram
Serial Interface Timing
July 2007
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MIC3002
Address Map
Address(s)
Field Size
(Bytes)
Name
Description
0 –95
96
Serial ID defined by SEP MSA
G-P NVRAM; R/W under valid OEM password.
96 – 127
32
Vendor Specific
Vendor specific EEPROM
128 – 255
128
Reserved
Reserved for future use. G-P NVRAM; R/W under valid OEM
password.
Table 1. MIC3002 Address Map, Serial Address = A0h
Address(s)
Field Size
(Bytes)
HEX
DEC
Name
Description
00-27
0-39
40
Alarm and Warning
Threshold
High/low limits for warning and alarms; writeable using OEM p/w; readonly otherwise.
28-37
40-55
16
Reserved
Reserved – do not write; reads undefined.
38-5B
56-91
36
Calibration Constants
Numerical constants for external calibration; writeable using OEM p/w;
read-only otherwise.
5C-5E
92-94
3
Reserved
Reserved – do not write; reads undefined.
5F
95
1
Checksum
G-P NVRAM; writeable using OEM p/w; ready only otherwise.
60-69
96-105
10
Analog Data
Real time analog parameter data.
6A-6D
106-109
4
Reserved
Reserved – do not write; reads undefined.
6E
110
1
Control/Status Bits
Control and status bits.
6F
111
1
Reserved
Reserved – do not write; reads undefined.
70-71
112-113
2
Alarm Flags
Alarm status bits; read only.
72-73
114-115
2
Reserved
Reserved – do not write; reads undefined.
74-75
116-117
2
Warning Flags
Warning status bits; read only.
76-77
118-119
2
Reserved
Reserved – do not write; reads undefined.
78-7E
120-126
7
OEMPW
OEM password entry field. The OEM password location can be selected
to be 78-7B (120-123) or 7B-7E (123-126) by setting the bit OEMCFG5
bit 2 to 0 (default) or 1.
7F
127
1
Vendor Specific
Vendor specific. Reserved – do not write; reads undefined.
80-DD
128-221
94
User Scratchpad
User writeable EEPROM. G-P NVRAM; R/W using any valid password.
DE
222
1
ALT_USRCTL
Alternate location for USRCTL register. Set bit OEMCFG6-2 to 1 to
select this location. Can be used as a scratch pad if not selected.
DF-F5
223-245
23
User Scratchpad
User writeable EEPROM. G-P NVRAM; R/W using any valid password.
F6
246
1
USRPWSET
User password setting; read/write using any p/w; returns zero otherwise.
F7
247
1
USRPW
User password register
F8-F9
248-249
2
Alarms Masks
Bit =1: corresponding alarm not masked
FA-FB
250-251
2
Warnings Masks
Bit =1: corresponding warning not masked
FC-FE
252-254
3
Reserved
Reserved – do not write; reads undefined.
FF
255
1
USRCTL
End-user control and status bits If ALT-USRCTL is not selected. Can be
used as a scratch pad if not selected.
Bit = 0: corresponding alarm masked
Bit = 0: corresponding warning masked
Table 2. MIC3002 Address Map, Serial Address = A2h
July 2007
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Address(s)
MIC3002
Field Size
(Bytes)
HEX
DEC
Name
Description
00-3F
0-63
64
BIASLUT1
Bias temperature compensation L.U.T. first 64 entries. Additional 12
entries are located in A6: 90-9B.
40-7F
64-127
64
MODLUT1
Modulation temperature compensation L.U.T. first 64 entries. Additional
12 entries are located in A6: A0-AB.
80-BF
128-191
64
IFTLUT1
Bias current fault threshold temperature compensation L.U.T. first 64
entries. Additional 12 entries are located in A6: B0-BB.
C0-FF
192-255
64
HATLUT1
Bias current high alarm threshold temperature compensation L.U.T. first
64 entries. Additional 12 entries are located in A6: C0-CB.
Table 3. Temperature Compensation Tables, Serial Address = A4h
Address(s)
HEX
DEC
00
0
01
1
02
Field Size
(Bytes)
Name
Description
1
OEMCFG0
OEM configuration register 0
1
OEMCFG1
OEM configuration register 1
2
1
OEMCFG2
OEM configuration register 2
03
3
1
APCSET0
APC setpoint register 0
04
4
1
APCSET1
APC setpoint register 1
05
5
1
APCSET2
APC setpoint register 2
06
6
1
MODSET0
Modulation setpoint register 0
07
7
1
IBFLT
Bias current fault-comparator threshold. This register is temperature
compensated
08
8
1
TXPFLT
TX power fault threshold
09
9
1
LOSFLT
RX LOS fault-comparator threshold
0A
10
1
FLTTMR
Fault comparator timer setting
0B
11
1
FLTMSK
Fault source mask bits
0C-0F
12-15
4
OEMPWSET
Password for access to OEM areas
10
16
1
OEMCAL0
OEM calibration register 0
11
17
1
OEMCAL1
OEM calibration register 1
12
18
1
LUTINDX
Look-up table index read-back
13
19
1
OEMCFG3
OEM configuration register 3
14
20
1
APCDAC
Reads back current APC DAC value (setpoint+offset)
15
21
1
MODDAC
Reads back current modulation DAC value (setpoint+offset)
16
22
1
OEMREAD
Reads back OEM calibration data
17
23
1
LOSFLTn
LOS De-assert threshold
18
24
1
RXPOT
RXPOT tap selection
19
25
1
OEMCFG4
OEM configuration register 4
1A
26
1
OEMCFG5
OEM configuration register 5
1B
27
1
OEMCFG6
OEM configuration register 6
1C-1D
28-29
2
SCRATCH
Reserved – do not write; reads undefined.
1E
30
1
MODSET 1
Modulation setpoint register 1
1F
31
1
MODSET 2
Modulation setpoint register 2
July 2007
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MIC3002
20-27
32-39
8
POHDATA
Power-on hour meter scratchpad
28-47
40-71
32
RXLUT
RX power calibration look-up table. Eight sets of slope and offset
48-57
72-87
16
CALCOEF
Slope and offset coefficients used for Temperature, Voltage, Bias, and
TXPOWER internal calibration
58-5F
88-95
8
SCRATCH
OEM scratchpad area
60-86
96-134
39
TCTRLUT
LUT to temperature-compensate temperature results and/or
temperature to be used by parameters compensation LUT.
87-8F
135-143
9
SCRATCH
OEM scratchpad area.
90-9B
144-155
12
BIASLUT2
Bias temperature compensation L.U.T. additional 12 entries.
9C-9F
156-159
4
SCRATCH
OEM scratchpad area
A0-AB
160-171
12
MODLUT2
Modulation temperature compensation L.U.T. additional 12 entries.
AC-AF
172-175
14
SCRATCH
OEM scratchpad area.
B0-BB
176-187
12
IFTLUT2
Bias current fault threshold temperature compensation L.U.T. additional
12 entries.
BC-BF
188-191
4
SCRATCH
OEM scratchpad area
C0-CB
192-203
12
HATLUT2
Bias current high alarm threshold temperature compensation L.U.T.
additional 12 entries.
CC-CF
204-207
4
SCRATCH
OEM scratchpad area
D0-DD
208-221
14
RXLUTSEG
RXPWR calibration segments delimiters. Each of the eight segments can
have its own slope and offset.
DE-FA
222-250
128
SCRATCH
OEM scratchpad area
FB-FC
251-252
2
POH
Power on hour meter result; read only
FD
253
1
Data Ready Flags
Data ready bits for each measured parameter; read only
FE
254
1
MFG_ID
Manufacturer identification (Micrel = 42 = 2Ah)
FF
255
1
DEV_ID
Device and die revision
Table 4. OEM Configuration Registers, Serial Address = A6h
July 2007
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MIC3002
Block Diagram
Figure 1. MIC3002 Block Diagram
Analog-to-Digital Converter/Signal Monitoring
A block diagram of the monitoring circuit is shown below.
Each of the five analog parameters monitored by the
MIC3002 are sampled in sequence. All five parameters
are sampled and the results updated within the tCONV
internal given in the “Electrical Characteristics” section. In
OEM, Mode, the channel that is normally used to
measure VIN may be assigned to measure the level of the
VDDA pin or one of five other nodes. This provides a kind
of analog loopback for debug and test purposes. The
VAUX bits in OEMCFG0 control which voltage source is
being sampled. The various VAUX channels are levelshifted differently depending on the signal source,
resulting in different LSB values and signal ranges. See
Table 5.
July 2007
Figure 2. Analog-to-Digital Converter Block Diagram
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MIC3002
Channel
ADC Resolution
(bits)
TEMP
8 or 9
VAUX
8
VMPD
8
VILD
(1)
Input Range (V)
LSB
N/A
1°C or 0.5°C
See Table 6
8
VRX
Conditions
GAIN = 0; BIASREF = 0
GNDA - VREF
GAIN = 0; BIASREF = 1
VDDA – (VDDA – VREF)
4.77mV
GAIN = 1; BIASREF = 0
GNDA - VREF/4
1.17mV
/4
GAIN = 1; BIASREF = 1
VDDA – (VDDA – VREF )
VILD- = VDDA
VDDA – (VDDA – VREF)
VILD- = GNDA
GNDA - VREF
RXPOT = 00
0 - VREF
12
4.77mV
0.298mV
Table 5. A/D Input Signal Ranges and Resolutions
Note:
1. Assumes typical VREF value of 1.22V.
(1)
Channel
VAUX [2:0]
Input Range (V)
LSB
(mV)
VIN
000 = 00h
0.5V to 5.5V
25.6mV
VDDA
0001 = 01h
0.5V to 5.5V
25.6mV
VBIAS
010 = 02h
0.5V to 5.5V
25.6mV
VMOD
011 = 03h
0.5V to 5.5V
25.6mV
APCDAC
100 = 04h
0V to VREF
4.77mV
MODDAC
101 = 05h
0V to VREF
4.77mV
FLTDAC
110 = 06h
0V to VREF
4.77mV
Table 6. VAUX Input Signal Ranges and Resolutions
Note:
1. Assumes typical VREF value of 1.22V.
Temperature Reading Compensation
The sensed temperature by the MIC3002 can be
temperature compensated and converted to the optical
module case temperature to be monitored or used for
modulation and other parameters (L.U.T.s). There are 39
entries (bytes) at address A6: 96-134 (60-86h) where the
OEM can enter the temperature difference between the
chip (sensed) temperature and the measured module
case temperature over the operating temperature range.
Table 7 shows the correspondence between the entries
and temperature intervals.
July 2007
The resolution of this table is 0.5ºC/bit. The number
entered should be twice the temperature difference. For
example if the chip-case temperature difference is 5ºC,
the value to be entered should be 2x5=10.
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MIC3002
Entry
Address
Temperature Range
0
A6: 96 (60h)
t ≤ -45 ºC
1
A6: 97 (61h)
-44 ºC ≤ t ≤ -41 ºC
2
A6: 98 (62h)
-40 ºC ≤ t ≤ -37 ºC
…………………………………………………………………………………
…………………………………………………………………………………
36
A6: 97 (61h)
96 ºC ≤ t ≤ 99 ºC
37
A6: 97 (61h)
100 ≤ t ≤ 103 ºC
38
A6: 134 (86h)
t ≥ 104 ºC
Table 7. L.U.T. for Temperature Reading Compensation
Alarms and Warnings Interrupt Source Masking
Alarms and warnings set the flags and Interrupt when
they are asserted if they are not masked (default). If an
alarm or warning is masked, it will not set the Interrupt.
Serial Address A2h
Byte
248
249
Default Value
Table 8 shows the locations of the masking bits. The
warning or alarm is masked if the corresponding bit is
set to 1.
Description
Bit
7
0
Masking bit for Temp High Alarm interrupt source
6
0
Masking bit for Temp Low Alarm interrupt source
5
0
Masking bit for Voltage High Alarm interrupt source
4
0
Masking bit for Voltage Low Alarm interrupt source
3
0
Masking bit for Bias High Alarm interrupt source
2
0
Masking bit for Bias Low Alarm interrupt source
1
0
Masking bit for TX Power High Alarm interrupt source
0
0
Masking bit for TX Power Low Alarm interrupt source
7
0
Masking bit for RX Power High Alarm interrupt source
6
1
Masking bit for RX Power Low Alarm interrupt source
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Table 8. Alarms Interrupt Sources Masking Bits
July 2007
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MIC3002
Serial Address A2h
Byte
250
251
Default Value
Description
7
0
Masking bit for Temp High Warning interrupt source
6
0
Masking bit for Temp Low Warning interrupt source
5
0
Masking bit for Voltage High Warning interrupt source
4
0
Masking bit for Voltage Low Warning interrupt source
3
0
Masking bit for Bias High Warning interrupt source
2
0
Masking bit for Bias Low Warning interrupt source
1
0
Masking bit for TX Power High Warning interrupt source
0
0
Masking bit for TX Power Low Warning interrupt source
7
0
Masking bit for RX Power High Warning interrupt source
6
1
Masking bit for RX Power Low Warning interrupt source
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Bit
Table 9. Warnings Interrupt Sources Masking Bits
Alarms and Warnings as TXFAULT Source
Alarms and warnings are not sources for TXFAULT with
the default setting. To set alarms as a TXFAULT source
set OEMCFG4 bit 6 to 1. To set warnings as a
TXFAULT, source set OEMCFG4 bit 7 to 1. The alarms
and warnings TXFAULT sources can be masked
individually in the same way shown in Tables 7 and 8.
Alarms and Warnings Latch
Alarms and warnings are latched with the default setting,
i.e., the flags once asserted remain ON until the register
is read or TXDSABLE is toggled. If OEMCFG4 bit 5 is
set to 1, the warnings are not latched and will be set and
reset with the warning condition. Reading the register or
toggling TXDISABLE will clear the flag. If OEMCFG4 bit
4 is set to 1, the alarms are not latched and will be set
and reset with the alarm condition. Reading the register
or toggling TXDISABLE will clear the flag.
July 2007
SMBus Multipart Support
If more than one MIC3002 device shares the same serial
interface and multipart mode is selected on them
(OEMCFG5 bit 3 = 1), then pin 7 and pin 20 become
SMBus address bits 3 and 4 respectively. Therefore, the
parts should have a different setting on those pins to
create four address combinations based upon pin 7 and
pin 20 state, (00, 01, 10, 11) where 0 is a pull down to
GND and 1 is a pull up to VCC. The parts come from the
factory with the same address (A0) and multipart mode
OFF (OEMCFG5 bit 3 = 0). After power up, write 1 to
OEMCFG5 bit 3 to turn ON multipart mode, which is
done to all parts at the same time since they all respond
to serial address A0 at this point. With multipart mode
ON, the parts have different addresses based on the
states of pins 7 and 20. Another option is to access each
part individually, set their single mode address in
OEMCFG2 bits [4-7] to different values and then turn
OFF multipart mode to return to normal mode where the
parts have new different address.
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MIC3002
Calibration Modes
The default mode of calibration in the MIC3002 is
external calibration, for which INTCAL bit (bit 0 in
OEMCF3 register) is set to 0. The internal calibration
mode is selected by setting INTCAL bit to 1.
The value of the least significant bit (LSB) of IBIASh is
given by:
(2)
A/ External Calibration
The voltage and temperature values returned by the
MIC3002’s A/D converter are internally calibrated. The
binary values of TEMPh:TEMPl and VOLTh:VOLTl are in
the format called for by SFF-8472 under Internal
Calibration.
SFF-8472 calls for a set of calibration constants to be
stored by the transceiver OEM at specific non-volatile
memory locations; refer to SFF-8472 specifications for
memory map of calibration coefficient. The MIC3002
provides the non-volatile memory required for the
storage of these constants. The Digital Diagnostic
Monitoring Interface specification should be consulted
for full details. Slopes and offsets are stored for use with
voltage, temperature, bias current, and transmitted
power measurements. Coefficients for a fourth-order
polynomial are provided for use with received power
measurements. The host system can retrieve these
constants and use them to process the measured data.
Per SFF-8472, the value of the bias current LSB is 2µA.
The conversion factor, “slope”, needed is therefore:
Voltage
The voltage values returned by the MIC3002’s A/D
converter are internally calibrated. The binary values of
VOLTh:VOLTl are in the format called for by SFF-8472
under Internal Calibration. Since VINh:VINl requires no
processing, the corresponding slope should be set to
one and the offset to zero.
The tolerance of the sense resistor directly impacts the
accuracy of the bias current measurement. It is
recommended that the sense resistor chosen be 1%
accurate or better. The offset correction, if needed, can
be determined by shutting down the laser, i.e., asserting
TXDISABLE, and measuring the bias current. Any nonzero result gives the offset required. The offset will be
equal and opposite to the result of the “zero current”
measurement.
TX Power
Transmit power is sensed via a resistor carrying the
monitor photodiode current. In most applications, the
signal at VMPD will be feedback voltage on FB. The
VMPD voltage may be measured relative to GND or
VDDA depending on the setting of the BIASREF bit in
OEMCFG1. The value returned by the A/D is therefore a
voltage analogous to transmit power. The binary value in
TXOPh (TXOPl is always zero) is related to transmit
power by:
Temperature
The temperature values returned by the MIC3002’s A/D
converter are internally calibrated. The binary values of
TEMPh:TEMPl are in the format called for by SFF-8472
under Internal Calibration.
Bias Current
Bias current is sensed via an external sense resistor as
a voltage appearing between VILD+ and VILD-. The
value returned by the A/D is therefore a voltage
analogous to bias current. Bias current, IBIAS, is simply
VVILD/RSENSE. The binary value in IBIASh (IBIASl is
always zero) is related to bias current by:
(3)
For a given implementation, the value of RSENSE is
known. It is either the value of the external resistor or the
chosen value of RFB used in the application. The
constant, K, will likely have to be determined through
experimentation or closed-loop calibration, as it depends
on the monitoring photodiode responsivity and coupling
efficiency.
It should be noted that the APC circuit acts to hold the
transmitted power constant. The value of transmit power
reported by the circuit should only vary by a small
amount as long as APC is functioning correctly.
(1)
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RX Power
Received power is sensed as a voltage appearing at
VRX. It is assumed that this voltage is generated by a
sense resistor carrying the receiver photodiode current
or by the RSSI circuit of the receiver. The value returned
by the A/D is therefore a voltage analogous to received
power. The binary values in RXOPh and RXOPl are
related to receive power by:
RX(mW) = K x VREF x (256 x RXOPh +RXOPl/16)/
65536
(4)
For a given implementation, the constant, K, will likely
have to be determined through experimentation or
closed-loop calibration, as it depends upon the gain and
efficiencies
of
the
receiver.
In
SFF-8472
implementations, the external calibration constants can
describe up to a fourth-order polynomial in case K is
nonlinear.
B/ Internal Calibration
If the INTCAL bit in OEMCFG3 is set to 1 (internal
calibration selected), the MIC3002 will process each
piece of data coming out of the A/D converter before
storing the result in memory. Linear slope/offset
correction will be applied on a per-channel basis to the
measured values for voltage, bias current, TX power,
and RX power. Only compensation is applied to
temperature.
The user must store the appropriate slope/offset
parameters in memory at the time of transceiver
calibration. In the case of RX power, a look-up table is
provided that implements eight-segment piecewiselinear correction. This correction may be performed as a
compensation of the receiver non-linearity over receive
power level. If static slope/offset correction for RX power
is desired, the eight coefficient sets can simply be made
the same. The memory maps for these coefficients are
shown in Tables 11 and 12. The user must enter the
seven delimiters of the intervals that fit better the
receiver response. The diagram in Figure 3 shows the
link between the delimiters and the sets of
slopes/offsets.
The slopes allow for the correction of gain errors. Each
slope coefficient is an unsigned, sixteen-bit, fixed-point
binary number in the format:
[mmmmmmmm.llllllll], where m is a data bit (5)
in the most-significant byte and l is a data
bit in the least significant byte
Slopes are always positive. The binary point is in between
the two bytes, i.e., between bits 7 and 8. This provides a
numerical range of 1/256 (0.00391) to 255.997 in steps of
1/256. The most significant byte is always stored in
memory at the lower numerical address.
July 2007
MIC3002
The offsets correct for constant errors in the measured
data. Each offset is a signed, sixteen-bit, fixed-point
binary number. The bit-weights of the offsets are the
same as that of the final results. The sixteen-bit offsets
provide a numerical range of –32768 to +32767 for
voltage, bias current, transmit power, and receive power.
The numerical range for the temperature offset is
–32513 (–128°) to +32512 (+127°) in increments of 256
(1°). The format for offsets is:
[Smmmmmmmllllllll], where S is the sign bit (6)
(0 = positive, 1 = negative), m is a data bit in
the most-significant byte and l is a data bit in
the least significant byte
The most significant byte is always stored in memory at
the lower numerical address.
Calibration of voltage, bias current, and TX power are
performed using the following calculation:
RESULTn = ADC_RESULTn x SLOPEn +
(7)
OFFSETn
Calibration of RX power is performed using the following
calculation:
RESULT = ADC_RESULT x SLOPE(m) + (9)
OFFSET(m)
where m represents one of the eight linearization
intervals corresponding to the RX power level.
The results of these calculations are rounded to sixteen
bits in length. If the seventeenth most significant bit is a
one, the result is rounded up to the next higher value. If
the seventeenth most significant bit is zero, the upper
sixteen bits remain unchanged. The bit-weights of the
offsets are the same as that of the final results. For SFF8472 compatible applications, these bit-weights are
given in Table 10.
Parameter
Magnitude of LSB
Voltage
100µV
Bias Current
2µA
TX Power
0.1µW
RX Power
0.1µW
Table 10. LSB Values of Offset Coefficients
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MIC3002
Address(s)
HEX
DEC
48-49
72-73
Field
Size
2
Name
RESERVED
Description
Reserved. (There is no slope for temperature.) Do not write; reads undefined.
4A-4B
74-75
2
RESERVED
4C-4D
76-77
2
VSLPh:VSLPl
Voltage slope; unsigned fixed-point; MSB is at lower physical address.
Reserved. (There is no offset for temperature.) Do not write; reads undefined.
4E-4F
78-79
2
VOFFh:VOFFl
Voltage offset; signed fixed point; MSB is at lower physical address.
50-51
80-81
2
ISLPh:ISLPl
Bias current slope; unsigned fixed-point; MSB is at lower physical address.
52-53
82-83
2
IOFFh:IOFFl
Bias current offset; signed fixed point; MSB is at lower physical address.
54-55
84-85
2
TXSLPh:
TXSLPl
TX power slope; unsigned fixed-point; MSB is at lower physical address.
56-57
86-87
2
TXOFFh:
TXOFFl
TX power offset; signed fixed point; MSB is at lower physical address.
Table 11. Internal Calibration Coefficient Memory Map – Part I
Address(s)
HEX
DEC
Field
Size
28-29
40-41
2
RXSLP0h:
RXSLP0l
RX power slope 0; unsigned fixed-point; MSB is at lower physical address.
2A-2B
42-43
2
RXOFF0h:
RXOFF0l
RX power offset 0; signed twos-complement; MSB is at lower physical address.
2C-2D
44-45
2
RXSLP1h:
RXSLP1l
RX power slope 1; unsigned fixed-point; MSB is at lower physical address.
2E-2F
46-47
2
RXOFF1h:
RXOFF1l
RX power offset 1; signed twos-complement; MSB is at lower physical address.
30-31
48-49
2
RXSLP2h:
RXSLP2l
RX power slope 2; unsigned fixed-point; MSB is at lower physical address.
32-33
50-51
2
RXOFF2h:
RXOFF2l
RX power offset 2; signed twos-complement; MSB is at lower physical address.
34-35
52-53
2
RXSLP3h:
RXSLP3l
RX power slope 3; unsigned fixed-point; MSB is at lower physical address.
36-37
54-55
2
RXOFF3h:
RXOFF3l
RX power offset 3; signed twos-complement; MSB is at lower physical address.
38-39
56-57
2
RXSLP4h:
RXSLP4l
RX power slope 4; unsigned fixed-point; MSB is at lower physical address.
3A-3B
58-59
2
RXOFF4h:
RXOFF4l
RX power offset 4; signed twos-complement; MSB is at lower physical address.
3C-3D
60-61
2
RXSLP5h:
RXSLP5l
RX power slope 5; unsigned fixed-point; MSB is at lower physical address.
3E-3F
62-63
2
RXOFF5h:
RXOFF5l
RX power offset 5; signed twos-complement; MSB is at lower physical address.
40-41
64-65
2
RXSLP6h:
RXSLP6l
RX power slope 6; unsigned fixed-point; MSB is at lower physical address.
42-43
66-67
2
RXOFF6h:
RXOFF6l
RX power offset 6; signed twos-complement; MSB is at lower physical address.
44-45
68-69
2
RXSLP7h:
RXSLP7l
RX power slope 7; signed twos-complement; MSB is at lower physical address.
46-47
70-71
2
RXOFF7h:
RXOFF7l
RX power offset 7; signed fixed-point; MSB is at lower physical address.
Name
Description
Table 12. Internal Calibration Coefficient Memory Map – Part II
July 2007
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MIC3002
Figure 3. Internal Calibration RX Power Linear Approximation
Temperature Offset
In both internal and external calibration, the temperature
offset is set in the temperature reading compensation LUT
(see subsection above). Bit 5 in OMCFG5 (A6:1Ah) must
be set to 1 in order to enable temperature reading
compensation. Since the resolution of that L.U.T. is 0.5ºC,
the entered value should be twice the real value. For
example, if the content of the L.U.T. is 0 for all the entries
and the offset is 5ºC, then the offset value to be added to
the entries content is 10. The new content of the L.U.T.
entries will be 0+10=10.
C/ ADC Result Registers Reading
The ADC result registers should be read as 16-bit registers
under internal calibration while under external calibration
they should be read as 8-bit or 16-bit registers at the MSB
address. For example, TX power should be read under
internal calibration as 16 bits at address A2h: 66–67 and
under external calibration as 8 bits at address A2h: 66h. 9bit temperature results and 12-bit receive power results
should always be read as 16-bit quantities.
RXPOT
A programmable, non-volatile digitally controlled
potentiometer is provided for adjusting the gain of the
receive power measurement signal chain in the analog
domain. Five bits in the RXPOT register are used to set
and adjust the position of potentiometer. RXPOT functions
as a programmable divider or attenuator. It is adjustable in
steps from 1:1 (no divider action) down to 1/32 in steps of
1/32. If RXPOT is set to zero, then the divider is bypassed
completely. There will be no scaling of the input signal, and
the resistor network will be disconnected from the VRX pin.
July 2007
At all other settings of RXPOT, there will be a 32kΩ (typical)
load seen on VRX.
Figure 4. RXPOT Block Diagram
Laser Diode Bias Control
The MIC3002 can be configured to generate a constant bias
current using electrical feedback, or regulate average
transmitted optical power using a feedback signal from a
monitor photodiode, refer to Figure 5. An operational
amplifier is used to control laser bias current via the VBIAS
output. The VBIAS pin can drive a maximum of ±10mA. An
external bipolar transistor provides current gain. The polarity
of the op amp’s output is programmable BIASREF in
OEMCFG1 in order to accommodate either NPN or PNP
transistors that drive common anode and common cathode
laser, respectively. Additionally, the polarity of the feedback
signal is programmable for use with either common-emitter
or emitter-follower transistor circuits.
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Furthermore, the reference level for the APC circuit is
selectable to accommodate electrical, i.e., current
feedback, or optical feedback via a monitor photodiode.
Finally, any one of seven different internal feedback
resistors can be selected. This internal resistor can be
used alone or in parallel with an external resistor. This wide
range of adjustability (50:1) accommodates a wide range
of photodiode current, i.e., wide range of transmitter output
power. The APC operating point can be kept near the midscale value of the APC DAC, insuring maximum SNR,
maximum effective resolution for digital diagnostics, and
the widest possible DAC adjustment range for temperature
compensation, etc. See Figure 6.
The APCCAL bit in OEMCAL0 is used to turn the APC
function on and off. It will be turned off in the MIC3002’s
default state as shipped from the factory. When APC is on,
the value in the selected APCSETx register is added to the
signed value taken from the APC look-up table and loaded
into the VBIAS DAC. When APC is off, the VBIAS DAC may
be written directly via the VBIAS register, bypassing the
look-up table entirely. This provides direct control of the
laser diode bias during setup and calibration. In either
case, the VBIAS DAC setting is reported in the APCDAC
register. The APCCFG bits determine the DACs response
to higher or lower numeric values.
MIC3002
Laser Modulation Control
As shown in Figure 5, a temperature-compensated DAC is
provided to set and control the laser modulation current via
an external laser driver circuit. MODREF in OEMCFG0
selects whether the VMOD DAC output swings up from
ground or down from VDD. If the laser driver requires a
voltage input to set the modulation current, the MIC3002’s
VMOD output can drive it directly. If a current input is required,
a fixed resistor can be used between the driver and the
VMOD output. Several different configurations are possible as
shown in Figure 8.
When APC is on, i.e., the APCCAL bit in OEMCAL0 is set to
0, the value corresponding to the current temperature is
taken from the MODLUT look-up table, added to MODSET,
and loaded into the VMOD DAC. When APC is off, the value
in VMOD is loaded directly into the VMOD DAC, bypassing the
look-up table entirely. This provides for direct modulation
control for setup and calibration. The MODREF bit
determines the DACs response to higher or lower numeric
values.
Figure 5. MIC3002 APC and Modulation Control
Block Diagram
Figure 7. Transmitter Configurations
Supported by MIC3002
Figure 6. Programmable Feedback Resistor
July 2007
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Configuration Bits
Shutdown State
OE
SPOL
SHDN
0
Don’t Care
Hi-Z
1
0
≈GND
1
1
≈VDD
Table 13. Shutdown State of SHDN vs.
Configuration Bits
VBIAS Shutdown State
Configuration Bits
OE
INV
BIASREF
VBIAS
0
Don’t Care
Don’t Care
Hi-Z
1
Don’t Care
0
≈GND
1
Don’t Care
1
≈VDD
Table 14. Shutdown State of VBIAS vs.
Configuration Bits
Configuration Bits
VMOD Shutdown State
OE
MODREF
Figure 8. VMOD Configured as Voltage Output
with Gain
0
Don’t Care
Hi-Z
1
0
≈GND
Power ON and Laser Start-Up
When power is applied, then the MIC3002 initializes its
internal registers and state machine. This process takes
tPOR, about 50ms. Following tPOR, analog-to-digital
conversions begin, serial communication is possible, and
the POR bit and data ready bits may be polled. The first
set of analog data will be available tCONV after tPOR.
MIC3002s are shipped from the factory with the output
enable bit, OE, set to zero, off. The MIC3002’s power-up
default state, therefore, is APC off, VBIAS, VMOD, and
SHDN outputs disabled. VBIAS, VMOD, and SHDN will
be floating (high impedance) and the laser diode, if
connected, will be off. Once the device is incorporated
into a transceiver and properly configured, then the
shutdown states of SHDN, VBIAS and VMOD will be
determined by the state of the APC configuration and
OE bits. Tables 13, 14, and 15 illustrate the shutdown
states of the various laser control outputs versus the
control bits.
1
1
≈VDD
July 2007
VMOD
Table 15. Shutdown State of VMOD vs.
Configuration Bits
In order to facilitate hot-plugging, the laser diode is not
turned on until tINIT2 after Power-On. Following tINIT2,
and assuming TXDISABLE is not asserted, the DACs
will be loaded with their initial values. Since tCONV is
much less than tINIT2, the first set of analog data,
including temperature, is available at tINIT2. Temperature
compensation will be applied to the DAC values if
enabled. APC will begin if OE is asserted. (If the output
enable bit, OE, is not set, the VMOD, VBIAS, and SHDN
outputs will float indefinitely.) Figure 9 shows the powerup timing of the MIC3002. If TXDISABLE is asserted at
power-up, the VMOD and VBIAS outputs will stay in their
shutdown states following MIC3002 initialization. A/D
conversions will begin, but the laser will remain off.
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MIC3002
Figure 9. MIC3002 Power-On Timing (OE = 1)
Fault Comparators
In addition to detecting and reporting the events specified
in SFF-8472, the MIC3002 also monitors five fault
conditions: inadequate supply voltage, thermal diode
faults, excessive bias current, excessive transmit power,
and APC op-amp saturation. Comparators monitor these
parameters in order to respond quickly to fault conditions
that could indicate link failure or safety issues, see Figure
10. When a fault is detected, the laser is shut down and
TXFAULT is asserted. Each fault source may be
independently disabled using the FLTMSK register.
FLTMSK is non-volatile, allowing faults to be masked only
during calibration and testing or permanently.
Figure 10. Fault Comparator Logic
July 2007
Thermal diode faults are detected within the temperature
measurement subsystem when an out-of-range signal is
detected. A window comparator circuit monitors the voltage
on the compensation capacitor to detect APC op-amp
saturation (Figure 11). Op-amp saturation indicates that
some fault has occurred in the control loop such as loss of
feedback. The saturation detector is blanked for a time,
tFLTTMR, following laser turn-on since the compensation
voltage will essentially be zero at turn-on. The FLTTMR
interval is programmable from 0.5ms to 127ms (typical) in
increments of 0.5ms (tFLTTMR). Note that a saturation
comparator cannot be relied upon to meet certain eyesafety standards that require 100ms response times. This is
because the operation of a saturation detector is limited by
the loop bandwidth, i.e., the choice of CCOMP. Even if the
comparator itself was very fast, it would be subject to the
limited slew-rate of the APC op-amp. Only the other fault
comparator
channels
will
meet
<100ms
timing
requirements.
The MIC3002 can also except and respond to fault inputs
from external devices. See “SHDN and TXFIN” section.
A similar comparator circuit monitors received signal
strength and asserts RXLOS when loss-of-signal is
detected (Figure 12). RXLOS will be asserted when and if
VRX drops below the level programmed in LOSFLT.
Hysteresis is implemented such that RXLOS will be deasserted when VRX subsequently rises above the level
programmed in LOSFLTn. The loss-of-signal comparator
may be disabled completely by setting the LOSDIS bit in
OEMCFG3. Once the LOS comparator is disabled, an
external device may drive RXLOS. The state of the RXLOS
pin is reported in the CNTRL register regardless of whether
it is driven by the internal comparator or by an external
device. A programmable digital-to-analog converter
provides the comparator reference voltages for monitoring
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received signal strength, transmit power, and bias
current. Glitches less than 10ms (typical) in length are
rejected by the fault comparators. Since laser bias current
varies greatly with temperature, there is a temperature
compensation look-up table for the bias current fault DAC
value.
When a fault condition is detected, the laser will be
shutdown immediately and TXFAULT will be asserted.
The VMOD, VBIAS, and SHDN if enabled, OEMCFG5-7 is
set to 1, outputs will be driven to their shutdown state
according to the state of the configuration bits. The
shutdown states of VMOD, VBIAS, and SHDN versus the
configuration bit settings are shown in Table 13, Table 14,
and Table 15.
SHDN and TXFIN
SHDN and TXFIN are optional functions of pin 7. SHDN
is an output function and is designed to drive a redundant
safety switch in the laser current path. TXFIN is an input
function and serves as an input for fault signals from
external devices that must be reported to the host via
TXFAULT. The SHDN function is designed for
applications in which the MIC3002 is performing all APC
and laser management tasks. The TXFIN function is for
situations in which an external device such as a laser
diode driver IC is performing laser management tasks,
including fault detection.
If the TXFIN bit in OEMCFG3 is zero (the default mode),
SHDN will be activated anytime the laser is off. Thus, it
will be active if 1) TXDISABLE is asserted, 2) STXDIS in
CNTRL, is set, or 3) a fault is detected. SHDN is a pushpull logic output. Its polarity is programmable via the
SPOL bit in OEMCFG1.
If TXFIN is set to one, pin 7 serves as an input that
accepts fault signals from external devices such as laser
diode driver ICs. Multiple TXFAULT signals cannot simply
be wire-ORed together as they are open-drain and active
high. The input polarity is programmable via the TXFPOL
bit in OEMCFG3. TXFIN is logically ORed with the
MIC3002’s internal fault sources to produce TXFAULT
and determine the value of the transmit fault bit in
CNTRL. See Figure 10.
Figure 11. Saturation Detector
July 2007
Figure 12. RXLOS Comparator Logic
Temperature Measurement
The temperature-to-digital converter for both internal and
external temperature data is built around a switched current
source and an eight-bit/nine-bit analog-to-digital converter.
The temperature is calculated by measuring the forward
voltage of a diode junction at two different bias current
levels. An internal multiplexer directs the current source’s
output to either an internal or external diode junction. The
value of the ZONE bit in OEMCFG1 determines whether
readings are taken from the on-chip sensor or from the XPN
input. The external PN junction may be embedded in an
integrated circuit, or it may be a diode-connected discrete
transistor. This data is also used as the input to the
temperature compensation look-up tables. Each time
temperature is sampled and an updated value acquired,
new corrective values for IMOD and the APC setpoint are
read from the corresponding tables, added to the set
values, and transferred to the DACs.
Diode Faults
The MIC3002 is designed to respond in a failsafe manner to
hardware faults in the temperature sensing circuitry. If the
connection to the sensing diode is lost or the sense line is
shorted to VDD or ground, the temperature data reported by
the A/D converter will be forced to its full-scale value
(+127°C). The diode fault flag, DFLT, will be set in
OEMCFG1, TXFAULT will be asserted, and the high
temperature alarm and warning flags will be set. The
reported temperature will remain +127°C until the fault
condition is cleared. Diode faults may be reset by toggling
TXDISABLE, as with any other fault. Diode faults will not be
detected at power up until the first A/D conversion cycle is
completed. Diode faults are not reported while TXDISABLE
is asserted.
Temperature Compensation
Since the performance characteristics of laser diodes and
photodiodes change with operating temperature, the
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MIC3002 provides a facility for temperature compensation
of the A.P.C. loop set-point, laser modulation current, bias
current fault comparator threshold, and bias current high
alarm flag threshold. Temperature compensation is
performed using a look-up table (LUT) that stores values
corresponding to each measured temperature over a
150°C span. Four identical tables reside at serial address
A4h and A6h as summarized in Table 16. Each table
entry is a signed twos complement number that is used
as an offset to the parameter being compensated. The
default value of all table entries is zero, giving a flat
response.
The A/D converter reports a new temperature sample
each tCONV. This occurs at roughly 10Hz. To prevent
temperature oscillation due to thermal or electrical noise,
sixteen successive temperature samples are averaged
together and used to index the L.U.T.s. Temperature
compensation results are therefore. updated at 16xtCONV
intervals, or about 1.6 seconds. This can be expressed as
shown in Equation 10:
(10)
Each time an updated average value is acquired, a new
offset value for the APC setpoint is read from the
corresponding look-up table (see Table 17) and
transferred to the APC circuitry. This is illustrated in
Equation 11. In a same way, new offset values are taken
from similar look-up tables (see Table 18 and Table 19),
added to the nominal values and transferred into the
modulation and fault comparator DACs. The bias current
high alarm threshold is compensated using a fourth lookup table (see Table 20). This compensation happens
internally and does not affect any host-accessible
registers.
MIC3002
(11)
If the measured temperature is greater than the maximum
table value, the highest value in each table is used. If the
measured temperature is less than the minimum, the
minimum value is used. Hysteresis is employed to further
enhance noise immunity and prevent oscillation about a
table threshold. Each table entry spans two degrees C. The
table index will not change unless the new temperature
average results in a table index beyond the midpoint of the
next entry in either direction. There is therefore 2 to 3°C of
hysteresis on temperature compensation changes. The
table index will never oscillate due to quantization noise as
the hysteresis is much larger than ±1⁄2 LSB.
Serial
Address
I2CADR+4h
I2CADR+6h
Byte
Addresses
Function
00h–3Fh
APC Look-up Table
40h–7Fh
IMOD Look-up Table
80h–BFh
IFLT Look-up Table
C0h–FFh
Bias High Alarm Look-up
Table
90h–9Bh
APC Look-up Table (cont.)
A0h–ABh
IMOD Look-up Table
(cont.)
B0h–BBh
IFLT Look-up Table (cont.)
C0h–CBh
Bias High Alarm Look-up
Table (cont.)
Table 16. Temperature Compensation Look-up Tables
July 2007
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MIC3002
Serial Address
Register
Address
Table
Offset
Temperature
Offset (°C)
I2CADR+4h
00h
0
≤ -45
01h
1
-44
-43
Serial Address
Register
Address
Table
Offset
Temperature
Offset (°C)
I2CADR+4h
80h
≤ -45
81h
-44
-43
82h
I2CADR+6h
•
•
•
•
•
•
•
•
•
•
•
•
8Eh
3Fh
63
8Fh
63
90h
64
B0
64
•
•
•
•
80
81
82
83
•
•
•
•
•
•
9A
74
BA
74
9B
75
BB
75
I2CADR+6h
102
103
≥ 104
Table 17. APC Temperature Compensation
Look-Up Table
Serial Address
Register
Address
Table
Offset
Temperature
Offset (°C)
I2CADR+4h
40h
0
≤ -45
41h
1
-44
-43
80
81
82
83
•
•
102
103
≥ 104
Table 19. IBIAS Comparator Temperature Compensation
Look-Up Table
Serial Address
Register
Address
Table
Offset
Temperature
Offset (°C)
I2CADR+4h
C0h
≤ -45
C1h
-44
-43
C2h
I2CADR+6h
•
•
•
•
•
•
•
•
•
7Fh
63
A0
64
•
•
•
•
80
81
82
83
•
•
AA
74
AB
75
•
•
•
FEh
I2CADR+6h
102
103
≥ 104
63
C0
64
•
•
•
•
CA
74
80
81
82
83
•
•
102
103
Table 20. BIAS Current High Alarm Temperature
Compensation Table
Table 18. VMOD Temperature Compensation
Look-Up Table
July 2007
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The internal state machine calculates a new table index
each time a new average temperature value becomes
available. This table index is derived from the average
temperature value. The table index is then converted into
a table address for each of the four look-up tables. These
operations can be expressed as:
(12)
where TAVG(n) is the current average temperature; and
TABLE_ADDRESS=INDEX+BASE_ADDRES
where BASE_ADDRESS is the physical base address of
each table, i.e., 00h, 40h, 80h, or C0h (tables reside in the
I2CADR+4h and I2CADR+6h pages of memory).
At any given time, the current table index can be read in
the LUTINDX register.
Alarms and Warning Flags
There are 20 different conditions that will cause the
MIC3002 to set one of the bits in the WARNx or ALARMx
registers. These conditions are listed in Table 22. The
less critical of these events generate warning flags by
setting a bit in WARN0 or WARN1. The more critical
events cause bits to be set in ALARM0 or ALARM1.
An event occurs when any alarm or warning condition
becomes true. Each event causes its corresponding
status bit in ALARM0, ALARM1, WARN0, or WARN1 to
be set. This action cannot be masked by the host. The
status bit will remain set until the host reads that
particular status register, a power on-off cycle occurs, or
the host toggles TXDISABLE.
If TXDISABLE is asserted at any time during normal
operation, A/D conversions continue. The A/D results for
all parameters will continue to be reported. All events will
be reported in the normal way. If they have not already
been individually cleared by read operations, when
TXDISABLE is de-asserted, all status registers will be
cleared.
July 2007
Control and Status I/O
The logic for the transceiver control and status I/O is shown
schematically in Figure 13. Note that the internal drivers on
RXLOS, RATE_SELECT, and TXFAULT are all open-drain.
These signals may be driven either by the internal logic or
external drivers connected to the corresponding MIC3002
pins. In any case, the signal level appearing at the pins of
the MIC3002 will be reported in the control register status
bits.
Note that the control bits for TX_DISABLE and
RATE_SELECT and the status bits for TXFAULT and
RXLOS do not meet the timing requirements as specified in
the SFP MSA or the GBIC Specification, revision 5.5 (SFF8053) for the hardware signals. The speed of the serial
interface limits the rate at which these functions can be
manipulated and/or reported. The response time for the
control and status bits is given in the “Electrical
Characteristics” subsection.
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MIC3002
Event
Condition
MIC3002 Response
Temperature high alarm
TEMP > TMAX
Set ALARM0[7]
Temperature low alarm
TEMP < TMIN
Set ALARM0[6]
Voltage high alarm
VIN > VMAX
Set ALARM0[5]
Voltage low alarm
VIN < VMIN
Set ALARM0[4]
TX bias high alarm
IBIAS > IBMAX
Set ALARM0[3]
TX bias low alarm
IBIAS < IBMIN
Set ALARM0[2]
TX power high alarm
TXOP > TXMAX
Set ALARM0[1]
TX power low alarm
TXOP < TXMIN
Set ALARM0[0]
RX power high alarm
RXOP > RXMAX
Set ALARM1[7]
RX power low alarm
RXOP < RXMIN
Set ALARM1[6]
Temperature high warning
TEMP > THIGH
Set WARN0[7]
Temperature low warning
TEMP < TLOW
Set WARN0[6]
Voltage high warning
VIN > VHIGH
Set WARN0[5]
Voltage low warning
VIN < VLOW
Set WARN0[4]
TX bias high warning
IBIAS > IBHIGH
Set WARN0[3]
TX bias low warning
IBIAS < IBLOW
Set WARN0[2]
TX power high warning
TXOP > TXHIGH
Set WARN0[1]
TX power low warning
TXOP < TXLOW
Set WARN0[0]
RX power high warning
RXOP > RXHIGH
Set WARN1[7]
RX power low warning
RXOP < RXLOW
Set WARN1[6]
Table 22. MIC3002 Events
Figure 13. Control and Status I/O Logic
July 2007
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MIC3002
System Timing
The timing specifications for MIC3002 control and status
I/O are given in the “Electrical Characteristics” subsection.
Figure 14. Transmitter ON-OFF Timing
Figure 15. Initialization Timing with TXDISABLE Asserted
Figure 16. Initialization Timing with TXDISABLE Not Asserted
July 2007
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Figure 17. Loss-of-Signal (LOS) Timing
Figure 18. Transmit Fault Timing
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Figure 19. Successfully Clearing a Fault Condition
Figure 20. Unsuccessful Attempt to Clear a Fault
Warm Resets
The MIC3002 can be reset to its power-on default state
during operation by setting the reset bit in OEMCFG0.
When this bit is set, TXFAULT and RXLOS will be deasserted, all registers will be restored to their normal
power-on default values, and any A/D conversion in
progress will be halted and the results discarded. The
state of the MIC3002 following this operation is
indistinguishable from a power-on reset.
Power-On Hour Meter
The Power-On Hour meter logs operating hours using an
internal real-time clock and stores the result in NVRAM.
The hour count is incremented at ten-hour intervals in the
middle of each interval. The first increment therefore
takes place five hours after power-on. Time is
accumulated whenever the MIC3002 is powered. The
hour meter’s time base is accurate to 5% over all
MIC3002 operating conditions. The counter is capable of
storing counts of more than thirty years, but is ultimately
limited by the write-cycle endurance of the non-volatile
memory. This implies a range of at least twenty years.
Actual results will depend upon the operating conditions
and write-cycle endurance of the part in question.
Two registers, POHH and POHl, contain a 15-bit power-on
hour measurement and an error flag, POHFLT. Great care
has been taken to make the MIC3002’s hour meter immune
to data corruption and to insure that valid data is maintained
across power cycles. The hour meter employs multiple data
copies and error correction codes to maintain data validity.
This data is stored in the POHDATA registers. If POHFLT is
set, however, the power-on hour meter data has been
corrupted and should be ignored.
It is recommended that a two-byte (or more) sequential
read operation be performed on POHh and POHl to insure
coherency between the two registers. These registers are
accessible by the OEM using a valid OEM password. The
only operation that should be performed on these registers
is to clear the hour meters initial value, if necessary, at the
time of product shipment. The hour meter result may be
cleared by setting all eight POHDATA bytes to 00h.
Power-On Hour Result Format
High Byte, POHH
Error Flag
Low Byte, POHI
Elapsed Time / 10 Hours, MSBs
Elapsed Time / 10 Hours, LSBs
MSB
LSB
Table 23. Power-On Hour Meter Result Format
July 2007
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MIC3002
Test and Calibration Features
Numerous features are included in the MIC3002 to
facilitate development, testing, and diagnostics. These
features are available via registers in the OEM area. As
shown in Table 24, these features include:
Function
Description
Control
Register(s)
Analog loop-back
Provides analog visibility of op-amp and DAC outputs via the ADC
OEMCFG0
Fault comparator disable control
Disables the fault comparator
OEMCAL0
Fault comparator spin-on-channel
mode
Selects a single fault comparator channel
OEMCAL0
Fault comparator output read-back
Allows host to read individual fault comparator outputs
OEMRD
RSOUT, /INT read-back
Allows host to read the state of these pins
OEMRD
Inhibit EEPROM write cycles
Speeds repetitive writes to registers backed up by NVRAM
OEMCAL0
APC calibration mode
Allows direct writes to MODDAC and APCDAC (temperature
compensation not used)
OEMCAL0
Continuity checking
Forcing of RXLOS, TXFAULT, /INT
OEMCAL0
Halt A/D
Stops A/D conversions; ADC in one-shot mode
OEMCAL1
ADC idle flag
Indicates ADC status
OEMCAL1
A/D one-shot mode
Performs a single A/D conversion on the selected input channel
OEMCAL1
A/D spin-on-channel mode
Selects a single input channel
OEMCAL1
Channel selection
Selects ADC or fault comparator channel for spin-on-channel
modes
OEMCAL1
LUT index read-back
Permits visibility of the LUT index calculated by the state-machine
LUTINDX
Manufacturer and device ID registers
Facilitates presence detection and version control
MFG_ID,
DEV_ID
Table 24. Test and Diagnostic Features
July 2007
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MIC3002
Serial Port Operation
The MIC3002 uses standard Write_Byte, Read_Byte, and
Read_Word operations for communication with its host. It
also supports Page_Write and Sequential_Read
transactions. The Write_Byte operation involves sending
the device’s slave address (with the R/W bit low to signal a
write operation), followed by the address of the register to
be operated upon and the data byte. The Read_Byte
operation is a composite write and read operation: the host
first sends the device’s slave address followed by the
register address, as in a write operation. A new start bit
must then be sent to the MIC3002, followed by a repeat of
the slave address with the R/W bit (LSB) set to the high
(read) state. The data to be read from the part may then be
clocked out. A Read_Word is similar, but two successive
data bytes are clocked out rather than one. These
protocols are shown in Figures 21 to 24.
The MIC3002 will respond to up to four sequential slave
addresses depending upon whether it is in OEM or User
mode. A match between one of the MIC3002’s addresses
and the address specified in the serial bit stream must be
made to initiate communication. The MIC3002 responds to
slave addresses A0h and A2h in User Mode; it also
responds to A4h and A6h in OEM Mode (assuming
I2CADR = Axh).
Page Writes
To increase the speed of multi-byte writes, the MIC3002
allows up to four consecutive bytes (one page) to be written
before the internal write cycle begins. The entire non-volatile
memory array is organized into four-byte pages. Each page
begins on a register address boundary where the last two
bits of the address are 00b. Thus, the page is composed of
any four consecutive bytes having the addresses xxxxxx00b,
xxxxxx01b, xxxxxx10b, and xxxxxx11b.
The page write sequence begins just like a Write_Byte
operation with the host sending the slave address, R/W bit
low, register address, etc. After the first byte is sent the host
should receive an acknowledge. Up to three more bytes can
be sent in sequence. The MIC3002 will acknowledge each
one and increment its internal address register in anticipation
of the next byte. After the last byte is sent, the host issues a
STOP. The MIC3002’s internal write process then begins. If
more than four bytes are sent, the MIC3002’s internal
address counter wraps around to the beginning of the fourbyte page.
To accelerate calibration and testing, NVRAM write cycles
can be disabled completely by setting the WRINH bit in
OEMCAL0. Writes to registers that do not have NVRAM
backup, will not incur write-cycle delays when writes are
inhibited. Write operations on registers that exist only in
NVRAM will still incur write cycle delays.
Figure 21. Write Byte Protocol
Figure 22. Read Byte Protocol
Figure 23. Read_Word Protocol
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Figure 24. Four-Byte Page White Protocol
Acknowledge Polling
The MIC3002’s non-volatile memory cannot be accessed
during the internal write process. To allow for maximum
speed bulk writes, the MIC3002 supports acknowledge
polling. The MIC3002 will not acknowledge serial bus
transactions while internal writes are in progress. The host
may therefore monitor for the end of the write process by
periodically checking for an acknowledgement.
Write Protection and Data Security
OEM Password
A password is required to access the OEM areas of the
MIC3002, specifically the non-volatile memory, look-up
tables, and registers at serial addresses A4h and A6h. A fourbyte field, OEMPWSET, at serial address A6h is used for
setting the OEM password. The OEM password is set by
writing OEMPWSET with the new value. The password
comparison is performed following the write to the MSB of
the OEMPW, address 7Bh (or 7Eh) at serial address A2h.
Therefore, this byte must be written last. A four-byte burstwrite sequence to address 78h (or 7Bh) may be used as this
will result in the MSB being written last. The new password
will not take effect until after a power-on reset occurs or a
warm reset is performed using the RST bit in OEMCFG0.
This allows the new password to be verified before it takes
effect.
The corresponding four-byte field for password entry,
OEMPW, is located at serial address A2h. This field is
therefore always visible to the host system. OEMPW is
compared to the four-byte OEMPWSET field at serial
address A6h. If the two fields match, access is allowed to the
OEM areas of the MIC3002 non-volatile memory at serial
addresses A4h and A6h. If OEMPWSET is all zeroes, no
password security will exist. The value in OEMPW will be
ignored. This helps prevent a deliberately unsecured
MIC3002 from being inadvertently locked. Once a valid
July 2007
password is entered, the MIC3002 OEM areas will be
accessible. The OEM areas may be re-secured by writing an
incorrect password value at OEMPW, e.g., all zeroes. In all
cases, OEMPW must be written LSB first through MSB last.
The OEM areas will be inaccessible following the final write
operation to OEMPW’s LSB. The OEMPW field is reset to all
zeros at power on. Any values written to these locations will be
readable by the host regardless of the locked/unlocked status
of the device. If OEMPWSET is set to zero (00000000h), the
MIC3002 will remain unlocked regardless of the contents of the
OEMPW field. This is the factory default security setting.
Note that a valid OEM password allows access to the OEM
and user areas of the chip, i.e., the entire memory map,
regardless of any user password that may be in place. Once
the OEM areas are locked, the user password can provide
access and write protection for the user areas.
User Password
A password is required to access the USER areas of the
MIC3002, specifically, the non-volatile memory at serial
addresses A0h and A2h. A one-byte field, USRPWSET at serial
address A2h is used for setting the USER password.
USRPWSET is compared to the USRPW field at serial address
A2h. If the two fields match, access is allowed to the USER
areas of the MIC3002 non-volatile memory at serial addresses
A0h and A2h. The USER password is set by writing
USRPWSET with the new value. The new password will not
take effect until after a power-on reset occurs or a warm reset
is performed using the RST bit in OEMCFG0. This allows the
new password to be verified before it takes effect.
Note also that a valid OEM password allows access to the
OEM and user areas of the chip, i.e., the entire memory map,
regardless of any user password that may be in place. Once
the OEM areas are locked, the user password can then provide
access and write protection for the user areas. If a valid OEM
password is in place, the user password will have no effect.
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MIC3002
Detailed Register Descriptions
Note: Serial bus addresses shown assume that I2CADR = Axh.
Alarm Threshold Registers
Temperature High Alarm Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0°C)
Serial Address
A2h
Byte Address
MSB (TXMAHh): 00 = 00h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TXMAHl): 00 = 01h
Each LSB of TMAXh represents one degree centigrade. This register is to be used in conjunction with TMAXl to yield a sixteenbit temperature value.
The value in this register is uncalibrated. The nine MSbits of threshold value (TMAXh;TMAXl) are compared bit to bit to the
nine MSbits value of the temperature reading (TEMPh;TEMPl).. Alarm bit Ax is set if Reading > Threshold.
Temperature Low Alarm Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5] read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0°C)
Serial Address
A2h
Byte Address
MSB (TMINh): 02 = 02h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TMINl): 02 = 02h
Each LSB of TMINh represents one degree centigrade. TMINh is to be used in conjunction with TMINl to yield a sixteen-bit
temperature value. The value in this register is uncalibrated. The nine MSbits of threshold value (TMINh;TMINl) are compared,
bit to bit, to The nine MSbits value of the temperature reading (TEMPh;TEMPl). Alarm bit Ax is set if Reading < Threshold.
Voltage High Alarm Threshold
D[7]
read/write
D[6]
read/write
D[5] read/write
D[4]
read/write
D[3]
read/write
Default Value
0000 0000b = 00h (0V)
Serial Address
A2h
Bytes Address
MSB (VMAXh): 08 = 08h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (VMAXl): 09 = 09h
Each LSB of VMAXh represents 25.6mV and each LSB of VMAXl represents 0.1mV. The sixteen bits threshold value
(VMAXh;VMAXl) is compared bit to bit to the sixteen bits value of the voltage reading (VINh;VINl). Alarm bit Ax is set if Reading
> Threshold.
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Voltage Low Alarm Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0V)
Serial Address
A2h
Bytes Address
MSB (VMINh): 10 = 0Ah
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (VMINl): 11 = 0Bh
Each LSB of VMINh represents 25.6mV and each LSB of VMINl represents 0.1mV. The sixteen bits threshold value
(VMINh;VMINl) is compared bit to bit to the sixteen bits value of the voltage reading (VINh;VINl). Alarm bit Ax is set if Reading
< Threshold.
Bias Current High Alarm Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mA)
Serial Address
A2h
Bytes Address
MSB (IMAXh): 16 = 10h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (IMAXl): 17 = 11h
Each LSB of IMAXh represents 512µA and each LSB of IMAXl represents 2µA. The sixteen bits threshold value (IMAXh;IMAXl)
is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Alarm bit Ax is set if Reading >
Threshold.
Bias Current Low Alarm Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mA)
Serial Address
A2h
Byte Address
MSB (IMINh): 18 = 12h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (IMINl): 19 = 13h
Each LSB of IMINh represents 512µA and each LSB of IMINl represents 2µA. The sixteen bits threshold value (IMINh;IMINl) is
compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Alarm bit Ax is set if Reading < Threshold.
TX Optical Power High Alarm
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Byte Address
MSB (TXMAXh): 24 = 18h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TXMAXl): 25 = 19h 24 = 18h
Each LSB of TXMAXh represents 25.6µW. This register is to be used in conjunction with TXMAXl to yield a sixteen-bit value.
The values in TXMAXh:TXMAXl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits
threshold value (TXMAXh;TXMAXl) is compared, bit to bit, to the sixteen bits value of the TX power reading (TXOPh:TXOPl).
Alarm bit Ax is set if Reading > Threshold.
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MIC3002
TX Optical Power Low Alarm
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Byte Address
MSB (TXMAXh): 24 = 18h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TXMAXl): 25 = 19h
Each LSB of TXMINh represents 25.6µW. This register is to be used in conjunction with TXMINl to yield a sixteen-bit value.
The values in TXMINh:TMINl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits
threshold value (TXMINh;TXMINl) is compared, bit to bit, to the sixteen bits value of the RTX power reading (TXOPh:TXOPl).
Alarm bit Ax is set if Reading < Threshold.
RX Optical Power High Alarm Threshold MSB (RXMAXh)
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Bytes Address
MSB (RXMAXh): 32 = 20h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (RXMAXl): 33 = 21h
Each LSB of RXMAXh represents 25.6µW. This register is to be used in conjunction with RXMAXl to yield a sixteen-bit value.
The value in this register is uncalibrated. The sixteen bits threshold value (RXMAXh;RXMAXl) is compared, bit to bit, to the
sixteen bits value of the RX power reading (RXOPh:RXOPl). Alarm bit Ax is set if Reading > Threshold.
RX Optical Power Low Alarm Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Byte Address
MSB (RXMINh): 34 = 22h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (RXMINl): 35 = 23h
Each LSB of RXMINh represents 25.6µW. This register is to be used in conjunction with RXMINl to yield a sixteen-bit value.
The value in this register is uncalibrated. The sixteen bits threshold value (RXMINh;RXMINl) is compared, bit to bit, to the
sixteen bits value of the RX power reading (RXOPh:RXOPl). Alarm bit Ax is set if Reading < Threshold.
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MIC3002
Warning Threshold Registers
Temperature High Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0°C)
Serial Address
A2h
Bytes Address
MSB (THIGHh): 04 = 04h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (THIGHl): 05 = 05h
Each LSB of THIGHh represents one degree centigrade. This register is to be used in conjunction with THIGHl to yield a
sixteen-bit temperature value. The value in this register is uncalibrated. The nine MSbits of threshold value (THIGHh;THIGHl)
are compared, bit to bit, to the nine MSbits value of the temperature reading (TEMPh;TEMPl).. Warning bit Wx is set if Reading
> Threshold.
Temperature Low Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0°C)
Serial Address
A2h
Bytes Address
MSB (TLOWh): 06 = 06h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TLOWl): 06 = 06h
Each LSB of TLOWh represents one degree centigrade. This register is to be used in conjunction with TLOWl to yield a
sixteen-bit temperature value. The value in this register is uncalibrated. The threshold value (THIGHh;THIGHl) is compared, bit
to bit, to the value of the temperature reading (TEMPh;TEMPl). Warning bit Wx is set if Reading < Threshold,
Voltage High Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0V)
Serial Address
A2h
Bytes Address
MSB (VHIGHh): 12 = 0Ch
LSB (VHIGHl): 13 = 0Dh 12 = 0Ch
D[2]
read/write
D[1]
read/write
D[0]
read/write
Each LSB of VHIGHh represents 25.6mV. This register is to be used in conjunction with VHIGHl to yield a sixteen-bit value.
The value in this register is uncalibrated. The threshold value (VHIGHh;VHIGHl) is compared. bit to bit. to the value of the
voltage reading (VINh;VINl). Warning bit Wx is set if Reading > Threshold.
Voltage Low Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0V)
Serial Address
A2h
Byte Address
MSB (VLOWh): 14 = 0Eh
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (VLOWl): 15 = 0Fh
Each LSB of VLOWh represents 25.6mV. This register is to be used in conjunction with VLOWl to yield a sixteen-bit value. The
value in this register is uncalibrated. The threshold value (VLOWh;VLOWl) is compared. bit to bit, to the value of the voltage
reading (VINh;VINl). Warning bit Wx is set if Reading < Threshold.
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MIC3002
Bias Current High Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mA)
Serial Address
A2h
Bytes Address
MSB (IHIGHh): 20 = 14h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (IHIGHl): 21 = 15h
Each LSB of IHIGHh represents 512µA and each LSB of IHIGHl represents 2µA. The sixteen bits threshold value
(IHIGHh;IHIGHl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Warning bit Wx is set if
Reading > Threshold.
Bias Current Low Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mA)
Serial Address
A2h
Bytes Address
MSB (ILOWh): 22 = 16h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (ILOWl): 23 = 17h
Each LSB of ILOWh represents 512µA and each LSB of ILOWl represents 2µA. The sixteen bits threshold value
(ILOWh;ILOWl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ILDh:ILDl). Warning bit Wx is set if
Reading < Threshold.
TX Optical Power High Warning MSB (TXHIGHh)
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Bytes Address
MSB (TXHIGHh): 28 = 1Ch
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TXHIGHl): 29 = 1Dh
Each LSB of TXHIGHh represents 25.6µW. This register is to be used in conjunction with TXHIGHl to yield a sixteen-bit value.
The values in TXHIGHh:TXHIGHl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits
threshold value (TXHIGHh;TXHIGHl) is compared, bit to bit, to the sixteen bits value of the TX power reading (TXOPh:TXOPl).
Warning bit Wx is set if Reading > Threshold.
TX Optical Power Low Warning
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Byte Address
MSB (TXLOWh): 30 = 1Eh
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (TXLOWl): 31 = 1Fh
Each LSB of TXLOWh represents 25.6µW. This register is to be used in conjunction with TXLOWl to yield a sixteen-bit value.
The values in TXLOWh:TLOWl are in an unsigned binary format. The value in this register is uncalibrated. The sixteen bits
threshold value (TXLOWh;TXLOWl) is compared, bit to bit, to the sixteen bits value of the TX power reading (TXOPh:TXOPl).
Warning bit Wx is set if Reading < Threshold.
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MIC3002
RX Optical Power High Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Byte Address
MSB (RXHIGHh): 36 = 24h
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (RXHIGHl): 37 = 25h
Each LSB of RXHIGHh represents 25.6µW and each ach LSB of RXHIGHl represents 0.1µW.. The value in this register is
uncalibrated. The sixteen bits threshold value (RXHIGHh;RXHIGHl) is compared, bit to bit, to the sixteen bits value of the RX
power reading (RXOPh:RXOPl). Warning bit Wx is set if Reading > Threshold.
RX Optical Power Low Warning Threshold
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0mW)
Serial Address
A2h
Byte Address
38 = 26h
D[2]
read/write
D[1]
read/write
D[0]
read/write
Each LSB of RXLOWh represents 25.6µW and each eah LSB of RXLOWl represents 0.1µW. The value in this register is
uncalibrated. The sixteen bits threshold value (RXlOWh;RXLOWl) is compared, bit to bit, to the sixteen bits value of the RX
power reading (RXOPh:RXOPl). Warning bit Wx is set if Reading > Threshold.
Checksum (CHKSUM)
Checksum of bytes 0 - 94 at serial address A2h
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h (0°C)
Serial Address
A2h
Byte Address
95 = 5Fh
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register is provided for compliance with SFF-8472. It is implemented as general-purpose non-volatile memory. Read/write
access is possible whenever a valid OEM password has been entered. CHKSUM is read-only in USER mode.
ADC Result Registers
Temperature Result
D[7]
read-only
Default Value
D[6]
read-only
D[5]
read-only
D[4]
read-only
Serial Address
D[3]
read-only
0000 0000b = 00h (0°C)(1)
A2h
Byte Address
MSB (TEMPh): 96 = 60h
D[2]
read-only
D[1]
read-only
D[0]
read-only
LSB (TEMPl): 97 = 61h
Each LSB of TEMPh represents one degree centigrade. The TEMPh register is to be used in conjunction with TEMPl to yield a
sixteen-bit temperature value. If OEMCFG6 bit 1 is a zero, temperature is read to 1°C resolution in TEMPh only, and TEMPl is
zero. If OEMCFG6 bit 1 is a one, then temperature is read to 0.5°C resolution as a nine-bit value consisting of TEMPh and the
MS bit of TEMPl. The lower seven bits of TEMPl are zero.
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MIC3002
Voltage
D[7]
read-only
Default Value
D[6]
read-only
D[5]
read-only
D[4]
read-only
Serial Address
D[3]
read-only
0000 0000b = 00h (0V)(2)
A2h
Byte Address
MSB (VINh): 98 = 62h
D[2]
read-only
D[1]
read-only
D[0]
read-only
LSB (VINl): 99 = 63h
Each LSB of VINh represents 25.6mV. VINh register is to be used in conjunction with VINl to yield a sixteen-bit value. The
values in VINh:VlNl are in an unsigned binary format. The value in this register is uncalibrated. The host should process the
results using the scale factor and offset provided. See the External Calibration section. In the MIC3002, VINl will always return
zero. It is provided for compliance with SFF-8472.
Notes:
1. TEMPh will contain measured temperature data after the completion of one conversion.
2. VINh will contain measured data after one A/D conversion cycle.
Laser Diode Bias Current
D[7]
read-only
Default Value
D[6]
read-only
D[5]
read-only
D[4]
read-only
Serial Address
D[3]
read-only
0000 0000b = 00h (0mA)(3)
A2h
Byte Address
MSB (ILDh):100 = 64h
D[2]
read-only
D[1]
read-only
D[0]
read-only
LSB (ILDl):100 = 65h
ILDh is to be used in conjunction with ILDl to yield a sixteen-bit value. The values in ILDh:ILDl are in an unsigned binary format.
The value in this register is uncalibrated. The host should process the results using the scale factor and offset provided. See
the External Calibration sections. In the MIC3002, ILDl will always return zero. It is provided for compliance with SFF-8472.
Transmitted Optical Power
D[7]
read-only
Default Value
Serial Address
Byte Address
D[6]
read-only
D[5]
read-only
D[4]
read-only
D[3]
read-only
0000 0000b = 00h (0mW)(5)
A2h
D[2]
read-only
D[1]
read-only
D[0]
read-only
MSB (TXOPh): 102 = 66h
LSB (TXOPl): 103 = 67h
Each LSB of TXOPh represents 25.6µW. THOPh is to be used in conjunction with TXOPl to yield a sixteen-bit value. The
values in TXOPh:TXOPl are in an unsigned binary format. The value in this register is uncalibrated. The host should process
the results using the scale factor and offset provided. See the External Calibration section. In the MIC3002, this TXOPl will
always return zero. It is provided for compliance with SFF-8472.
Notes:
3. ILDh will contain measured data after one A/D conversion cycle.
4. The scale factor corresponding to the sense resistor used must be set in the configuration register.
5. TXOPh will contain measured data after one A/D conversion cycle.
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MIC3002
Received Optical Power
D[7]
read-only
Default Value
D[6]
read-only
D[5]
read-only
D[4]
read-only
Serial Address
D[3]
read-only
0000 0000b = 00h (0mW)(6)
A2h
Byte Address
MSB (RXOPh): 104 = 68h
D[2]
read-only
D[1]
read-only
D[0]
read-only
LSB (RXOPl): 105 = 69h
Each LSB of RXOPl represents 25.6µW and each LSB of RXOPl represents 0.1µW. RXOPh is to be used in conjunction with
RXOPl to yield a sixteen-bit value. The values in RXOPh:RXOPl are in an unsigned binary format. The value in this register is
uncalibrated. The host should process the results using the scale factor and offset provided. See the External Calibration
section.
Control and Status (CNTRL)
D[7]
TXDIS
read-only
Default Value
D[6]
STXDIS
read/write
D[5]
reserved
D[4]
RSEL
read/write
D[3]
SRSEL
read/write
D[2]
XFLT
read-only
0000 0000b = 00h
Serial Address
A2h
Byte Address
110 = 6Eh
Bit(s)
D[7]
TXDIS
D[6]
STXDIS
D[1]
LOS
read-only
D[0]
POR
read-only
Function
Operation
Reflects the state of the TXDISABLE pin
1 = disabled, 0 = enabled, read only.
Soft transmit disable
1 = disabled; 0 = enabled.
D[5]
D[5]
Reserved
Reserved - always write as zero.
D[4]
RSEL
Reflects the state of the RSEL pin
1 = high; 0 = low.
D[3]
SREL
Soft rate select
1 = high (2Gbps); 0 = low (1Gbps).
D[2]
TXFLT
Reflects the state of the TXFAULT pin
1 = high (fault); 0 = low (no fault).
D[1]
LOS
Loss of signal. Reflects the state of the LOS pin
1 = high (loss of signal); 0 = low (no loss
of signal).
D[0]
POR
MIC3002 power-on status
0 = POR complete, analog data ready;
1 = POR in progress.
Notes:
6.
RXOPh will contain measured data after one A/D conversion cycle.
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MIC3002
Alarm Flags
Alarm Status Register 0 (ALARM0)
D[7]
A7
read-only
Default Value
D[6]
A6
read-only
D[5]
A5
read-only
D[4]
D[3]
D[2]
A4
A3
A2
read-only
read-only
read-only
0000 0000b = 00h (no events pending)
Serial Address
A2h
Byte Address
112 = 70h
D[1]
A1
read-only
D[0]
A1
read-only
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the
results.
Bit(s)
Function
Operation
D[7]
A7
High temperature alarm, TEMP > TMAXh
1 = condition exists, 0 = normal/OK.
D[6]
A6
Low temperature alarm, TEMPh< TMIN
1 = condition exists, 0 = normal/OK.
D[5]
A5
High voltage alarm, VIN > VMAX
1 = condition exists, 0 = normal/OK.
D[4]
A4
Low voltage alarm, VIN < VMIN
1 = condition exists, 0 = normal/OK.
D[3]
A3
High laser diode bias alarm, IBIAS > IMAX
1 = condition exists, 0 = normal/OK.
D[2]
A2
Low laser diode bias alarm, IBIAS < IMIN
1 = condition exists, 0 = normal/OK.
D[1]
A1
High transmit optical power alarm,
TXOP > TXMAX
1 = condition exists, 0 = normal/OK.
D[0]
A0
Low transmit optical power alarm,
TXOP < TXMIN
1 = condition exists, 0 = normal/OK.
Alarm Status Register 1 (ALARM1)
D[7]
A15
read-only
Default Value
D[6]
A14
read-only
D[5]
reserved
D[4]
reserved
D[3]
reserved
D[2]
reserved
D[1]
reserved
D[0]
reserved
0000 0000b = 00h (no events pending)
Serial Address
A2h
Byte Address
113 = 71h
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the
results.
Function
Operation
D[7]
Bit(s)
A15
High received power (overload) alarm, RXOP
> RXMAX
1 = condition exists, 0 = normal/OK.
D[6]
A14
Low received power (LOS) alarm, RXOP <
RXMIN
1 = condition exists, 0 = normal/OK.
Reserved
Reserved - always write as zero.
D[5:0]
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MIC3002
Warning Flags
Warning Status Register 0 (WARN0)
D[7]
W7
read-only
D[6]
W6
read-only
D[5]
W5
read-only
Default Value
D[4]
D[3]
D[2]
W4
W3
W2
read-only
read-only
read-only
0000 0000b = 00h (no events pending)
Serial Address
A2h
Byte Address
116 = 74h
D[1]
W1
read-only
D[0]
W1
read-only
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the
results.
Bit(s)
Function
Operation
D[7]
W7
High temperature warning, TEMP > THIGH
1 = condition exists, 0 = normal/OK.
D[6]
W6
Low temperature warning, TEMP < TLOW
1 = condition exists, 0 = normal/OK.
D[5]
W5
High voltage warning, VIN > VHIGH
1 = condition exists, 0 = normal/OK.
D[4]
W4
Low voltage warning, VIN < VLOW
1 = condition exists, 0 = normal/OK.
D[3]
W3
High laser diode bias warning, IBIAS > IHIGH
1 = condition exists, 0 = normal/OK.
D[2]
W2
Low laser diode bias warning, IBIAS < ILOW
1 = condition exists, 0 = normal/OK.
D[1]
W1
High transmit optical power warning,
TXOP > TXHIGH
1 = condition exists, 0 = normal/OK.
D[0]
W0
Low transmit optical power warning,
TXOP < TXLOW
1 = condition exists, 0 = normal/OK.
Warning Status Register 1 (WARN1)
D[7]
W15
read-only
D[6]
W14
read-only
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read-only
read-only
read-only
Default Value
0000 0000b = 00h (no events pending)
Serial Address
A2h
Byte Address
117 = 75h
The power-up default value is 00h. Following the first A/D conversion, however, any of the bits may be set depending upon the
results.
Bit(s)
Function
Operation
D[7]
W15
Received power high warning, RXOP >
RXHIGH
1 = condition exists, 0 = normal/OK.
D[6]
W14
Received power low warning, RXOP < RXMIN
1 = condition exists, 0 = normal/OK.
Reserved
Reserved - always write as zero.
D[5:0]
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MIC3002
OEM Password Entry (OEMPW)
D[7]
read/write
D[6]
read/write
D[5]
read/write
D[4]
read/write
D[3]
read/write
D[2]
read/write
Default Value
0000 0000b = 00h (reset to zero at power-on)
Serial Address
A2h
Byte Address
If OEMCFG5-2 = 0: 120 – 123 = 78h - 7Bh
If OEMCFG5-2 = 1: 123– 126 = 7Bh – 7Eh
D[1]
read/write
D[0]
read/write
(MSB is 7Bh
(MSB is 7Eh)
This four-byte field is for entry of the password required to access the OEM area of the MIC3002’s memory and registers. A
valid OEM password will also permit access to the user areas of memory. The byte at address 123 (7Bh), 126 (7Eh) if
OMGFG5 bit2 =1, is the most significant byte. This field is compared to the four-byte OEMPWSET field at serial address A6h,
bytes 12 to 15. If the two fields match, access is allowed to the OEM areas of the MIC3002 non-volatile memory at serial
addresses A4h and A6h. The OEM password is set by writing the new value into OEMPWSET. The password comparison is
performed following the write to the MSB, address 7Bh (7Eh if OEMCFG5-2 = 1). This byte must be written last!
A four-byte burst-write sequence to address 78h(7Bh if OEMCFG5-2 = 1) may be used as this will result in the MSB being
written last. The new password will not take effect until after a power-on reset occurs or a warm reset is performed using the
RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. This field is reset to all zeros at power
on. Any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device. If
OEMPWSET is set to zero (00000000h), the MIC3002 will remain unlocked regardless of the contents of the OEMPW field.
This is the factory default security setting.
Byte
Weight
3
OEM Password Entry, Most Significant Byte (Address = 7Bh resp. 7Eh)
2
OEM Password Entry, 2nd Most Significant Byte (Address = 7Ah resp. 7Dh)
1
OEM Password Entry, 2nd Least Significant Byte (Address = 79h resp. 7Ch)
0
OEM Password Entry, Least Significant Byte (Address = 78h resp. 7Bh)
USER Password Setting (USRPWSET)
D[7]
read/write
D[6]
read/write
D[5]
read/write
D[4]
read/write
Default Value
0000 0000b = 00h
Serial Address
A2h
Byte Address
246 = F6h
D[3]
read/write
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register is for setting the password required to access the USER area of the MIC3002’s memory and registers. This field is
compared to the USRPW field at serial address A2h, byte 247(F7h). If the two fields match, access is allowed to the USER
areas of the MIC3002 non-volatile memory at serial addresses A0h and A2h. If a valid USER password has not been entered,
writes to the serial ID fields, USRCTRL, and the user scratchpad areas of A0h and A2h will not be allowed, and USRPWSET
will be unreadable (returns all zeroes).
A USER password is set by writing the new value into USRPWSET. The new password will not take effect until after a poweron reset occurs or a warm reset is performed using the RST bit in OEMCFG0. This allows the new password to be verified
before it takes effect. This register is non-volatile and will be maintained through power and reset cycles. A valid USER or OEM
password is required for access to this register. Otherwise, this register will read as 00h. Note: a valid OEM password overrides
the USER password setting. If a valid OEM password is currently in place, the user password will have no effect.
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MIC3002
USER Password (USRPW)
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A2h
Byte Address
247 = F7h
D[2]
read/write
D[1]
read/write
D[0]
read/write
USER passwords are entered in this field. This field is compared to the USRPWSET field at serial address A2h, byte 246
(F6h). If the two fields match, access is allowed to the USER areas of the MIC3002 non-volatile memory at serial addresses
A0h and A2h. If a valid USER password has not been entered, writes to the serial ID fields and user scratchpad areas of A0h
and A2h will not be allowed and USRPWSET will be unreadable (returns all zeroes).
Power-On Hours
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Bytes Address
MSB (POHh): 251 = FBh
D[2]
read/write
D[1]
read/write
D[0]
read/write
LSB (POHl): 252 = FCh
The lower seven bits of POHh register contain the most-significant bits of the 15-bit power-on hours measurement. POHFLT is
an error flag. The value in POHh should be combined with the Power-on Hours, Low Byte, POHl, to yield the complete result.
If POHFLT is set, the power-on hour meter data has been corrupted and should be ignored. It is recommended that a two-byte
(or more) sequential read operation be performed on POHh and POHl to insure coherency between the two registers. This
register is non-volatile and will be maintained through power and reset cycle.
POHh Bit(s)
Function
Operation
D[7]
Power-on hours fault flag
1 = fault; 0 = no fault.
D[6:0]
Power-on hours, high byte
Non-volatile.
Data Ready Flags (DATARDY)
D[7]
TRDY
read/write
Default Value
D[6]
VRDY
read/write
D[5]
IRDY
read/write
D[4]
D[3]
TXRDY
RXDY
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
253 = FDh
D[2]
reserved
D[1]
reserved
D[0]
reserved
When the A/D conversion for a given parameter is completed and the results available to the host, the corresponding data
ready flag will be set. The flag will be cleared when the host reads the corresponding result register.
Bit(s)
Function
Operation
D[7]
TRDY
Temperature data ready flag
0 = old data; 1 = new data ready
D[6]
VRDY
Voltage data ready flag
0 = old data; 1 = new data ready
D[5]
IRDY
D[4]
TXRDY
D[3]
RXRDY
D[2:0]
July 2007
Bias current data ready flag
0 = old data; 1 = new data ready
Transmit power data ready flag
0 = old data; 1 = new data ready
Receive power data ready flag
0 = old data; 1 = new data ready
Reserved
Reserved
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MIC3002
USER Control Register (USRCTL)
D[7]
D[6]
PORM
read/write
read/write
D[5]
PORS
read/write
D[4]
IE
read/write
D[3]
APCSEL[1]
read/write
Default Value
0010 0000b = 20h
Serial Address
A2h
Byte Address
255 = FFh if OMCFG6 bit 2 = 0
D[2]
APCSEL[0]
read/write
D[1]
MODSEL[1]
read/write
D[0]
MODSEL[0]
read/write
222 = DEh if OMCFG6 bit 2 = 1
This register provides for control of the nominal APC setpoint and management of interrupts by the end-user. APCSEL[1:0]
select which of the APC setpoint registers, APCSET0, APCSET1, or APCSET2 are used as the nominal automatic power
control setpoint.
IE must be set for any interrupts to occur. If PORM is set, the power-on event will generate an interrupt and warm resets using
RST will not generate a POR interrupt. When a power-on interrupt occurs, assuming PORM=1, PORS will be set. PORS will be
cleared and the interrupt output de-asserted when USRCTL is read by the host. If IE is set while /INT is asserted, /INT will be
de-asserted. The host must still clear the various status flags by reading them. If PORM is set following the setting of PORS,
PORS will remain set, and /INT will not be de-asserted, until USRCTL is read by the host.
PORM, IE, and APCSEL are non-volatile and will be maintained through power and reset cycles. A valid USER password is
required for access to this register.
Bit
D[7]
Function
Operation
Reserved
Always write as zero; reads undefined.
D[6]
PORM
Power-on interrupt mask
1 = POR interrupts enabled; 0 = disabled; read/write;
non-volatile.
D[5]
PORS
Power-on interrupt flag
1 = POR interrupt occurred; 0 = no POR interrupt;
read-only.
D[4]
IE
Global interrupt enable
1 = enabled; 0 = disabled; read/write; non-volatile.
D[3:2]
APCSEL
Selects APC setpoint register
00 = APCSET0, 01 = APCSET1, 10 = APCSET2;
11 = reserved; read/write; non-volatile.
D[1:0]
MODSEL
Selects Modulation setpoint register
00 = MODSET0, 01 = MODSET1, 10 = MODSET2, 11 =
reserved; read/write; non volatile.
OEM Configuration Register 0 (OEMCFG0)
D[7]
RST
write only
Default Value
D[6]
ZONE
read/write
D[5]
DFLT
read only
D[4]
D[3]
OE
MODREF
reserved
reserved
0000 0000b = 00h
Serial Address
A6h
Byte Address
00 = 00h
D[2]
VAUX[2]
read/write
D[1]
VAUX[1]
read/write
D[0]
VAUX[0]
read/write
A write to OEMCFG0 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a
new conversion sequence once the write operation is complete. All bits in OEMCFG0 are non-volatile except DFLT and RST. A
valid OEM password is required for access to this register.
Bit(s)
Function
Operation
D[7]
RST
D[6]
ZONE
Selects temperature zone.
D[5]
DFLT
Diode fault flag.
1 = diode fault; 0 = OK.
D[4]
OE
Output enable for SHDN, VMOD,
1 = enabled; 0 = hi-Z; non-volatile.
July 2007
0 = no action; 1 = reset; write-only.
0 = internal; 1 = external; non-volatile.
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and VBIAS.
D[3]
MODREF
Selects whether VMOD is
referenced to ground or VDD.
1 = VDD; 0 = GND; non-volatile.
D[2:0]
VAUX[2:0]
Selects the voltage reported in
VINh:VINl.
000 = VIN; 001 = VDDA; 010 = VBIAS; 011 = VMOD;
100 = APCDAC; 101 = MODDAC; 110 = FLTDAC; nonvolatile
OEM Configuration Register 1 (OEMCFG1)
D[7]
INV
read/write
Default Value
D[6]
GAIN
read/write
D[5]
BIASREF
read/write
D[4]
D[3]
RFB[2]
RFB[1]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
1 = 01h
D[2]
RFB[0]
read/write
D[1]
SRCE
read/write
D[0]
SPOL
read/write
A write to OEMCFG1 will result in any A/D conversion in progress being aborted and the result discarded. The A/D will begin a
new conversion sequence once the write operation is complete. All bits in OEMCFG1 are non-volatile and will be maintained
through power and reset cycles. A valid OEM password is required for access to this register.
Bit(s)
D[7]
D[6]
INV
GAIN
Function
Operation
Inverts the APC op-amp inputs.
When set to “0” the BIAS DAC
output is connected to the “+”input
and FB is connected to the “–” input
of the op amp. Set to “0” to use the
ADC feedback loop.
0 = emitter follower (no inversion);
Sets the feedback voltage range by
changing the APCDAC output
swing; 0-VREF for optical feedback,
0-VREF/4 for electrical feedback.
1 = VREF/4 full scale;
1 = common emitter (inverted); read/write; non-volatile.
0 = VREF full scale; read/write; non-volatile.
D[5]
BIASREF
Selects whether FB and VMPD are
referenced to ground or VDD and
selects feedback resistor termination
voltage (VDDA or GNDA).
1 = VDD; 0 = GND; read/write; non-volatile.
D[4:2]
RFB[2:0]
Selects internal feedback resistance.
(Resistors will be terminated to VDDA
or GNDA according to BIASREF.)
000 = ∞;
001 = 800Ω,
010 = 1.6kΩ,
011 = 3.2kΩ,
100 = 6.4kΩ,
101 = 12.8kΩ,
110 = 25.6kΩ,
111 = 51.2kΩ;
read/write; non-volatile.
D[1]
SRCE
VBIAS source vs. sink drive.
1 = source (NPN),
0 = sink (PNP); read/write; non-volatile.
D[0]
SPOL
Polarity of shutdown output, SHDN,
when active.
1 = high;
0 = low; read/write; non-volatile.
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MIC3002
OEM Configuration Register 2 (OEMCFG2)
D[7]
I2CADR[3]
read/write
D[6]
I2CADR[2]
read/write
D[5]
I2CADR[1]
read/write
Default Value
D[4]
D[3]
D[2]
I2CADR[0]
read/write
read/write
read/write
1010 xxxxb = xxh (slave address = 1010xxxb)
Serial Address
A6h
Byte Address
2 = 02h
D[1]
D[0]
read/write
read/write
CAUTION: Changes to I2CADR take effect immediately! Any accesses following a write to I2CADR must be to the newly
programmed serial bus address. A valid OEM password is required for access to this register. This register is non-volatile and
will be maintained through power and reset cycles.
Bit(s)
D[7:4]
I2CADR[3:0]
D[3:0]
Reserved
Function
Operation
Upper four MSBs of the serial bus
slave address; writes take effect
immediately.
Read/write; non-volatile.
Read/write; non-volatile.
APC Setpoint x (APCSETx)
Automatic power control setpoint (unsigned binary) used when APCSEL[1:0] = 00
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Bytes Address
APCSET0: 3 = 03h
D[2]
read/write
D[1]
read/write
D[0]
read/write
APCSET1: 4 = 04h
APCSET2: 5 = 05h
When A.P.C. is on, i.e., the APCCAL bit in OEMCAL0 is set, the value in APCSETx is added to the signed value taken from the
A.P.C. look-up table and loaded into the VBIAS DAC. When A.P.C. is off, the value in APCSET is loaded directly into the
VBIAS DAC, bypassing the look-up table entirely. In either case, the VBIAS DAC setting is reported in the VBIAS register. The
APCCFG bits determine the DAC’s response to higher or lower numeric values. A valid OEM password is required for access
to this register. This register is non-volatile and will be maintained through power and reset cycles.
Modulation Setpoint x (MODSETx)
Nominal VMOD setpoint
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
MODSET0: 6 = 06h
D[2]
read/write
D[1]
read/write
D[0]
read/write
MODSET1: 30 = 1Eh
MODSET2: 31 = 1Fh
When A.P.C. is on, the value corresponding to the current temperature is taken from the MODLUT look-up table, added to
MODSET and loaded into the VMOD DAC. This register is non-volatile and will be maintained through power and reset cycles. A
valid OEM password is required for access to this register.
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MIC3002
IBIAS Fault Threshold (IBFLT)
Bias current fault threshold
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
7 = 07h
D[2]
read/write
D[1]
read/write
D[0]
read/write
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power
and reset cycles. A fault is generated if the bias current is higher than IBFLT value set in this register.
Transmit Power Fault Threshold (TXFLT)
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
8 = 08h
D[2]
read/write
D[1]
read/write
D[0]
read/write
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power
and reset cycles. A fault is generated if the Transmit power is higher than TXFLT value set in this register.
Loss-Of-Signal Threshold (LOSFLT)
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
9 = 09h
D[2]
read/write
D[1]
read/write
D[0]
read/write
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power
and reset cycles. A fault is generated if the received power is lower than LOSFLT value set in this register.
Byte
Function
Operation
D[7:4]
Receive loss-of-signal threshold
Read/write; non-volatile.
Fault Suppression Timer (FLTTMR)
Fault suppression interval in increments of 0.5ms
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
10 = 0Ah
D[2]
read/write
D[1]
read/write
D[0]
read/write
Saturation faults are suppressed for a time, tFLTTMR, following laser turn-on. This avoids nuisance tripping while the APC loop
starts up. The length of this interval is (FLTTMRx 0.5ms), typical. A value of zero will result in no fault suppression. A valid
OEM password is required for access to this register. This register is non-volatile and will be maintained through power and
reset cycles.
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MIC3002
Fault Mask (FLTMSK)
D[7]
OEMIM
read/write
Default Value
D[6]
POHE
read/write
D[5]
reserved
D[4]
reserved
D[3]
SATMSK
read/write
D[2]
TXMSK
read/write
D[1]
IAMSK
read/write
D[0]
DFMSK
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
11 = 0Bh
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power
and reset cycles.
Bit
Function
Operation
D[7]
OEMIM
OEM interrupt mask bit
1 = masked; 0 = enabled; Read/write; non-volatile.
D[6]
POHE
OEM Power-on Hour Meter enable bit
1 = enabled; 0 = disabled; Read/write; non-volatile.
D[5:4]
D[5:4]
Reserved
Always write as zero; reads undefined.
D[3]
SATMSK
APC saturation fault mask bit
1 = masked; 0 = enabled; Read/write; non-volatile.
D[2]
TXMSK
High TX optical power fault mask bit
1 = masked; 0 = enabled; Read/write; non-volatile.
D[1]
IAMSK
Bias current high alarm mask bit
1 = masked; 0 = enabled; Read/write; non-volatile.
D[0]
DFMSK
Diode fault mask bit
1 = masked; 0 = enabled; Read/write; non-volatile.
OEM Password Setting (OEMPWSET)
D[7]
read/write
D[6]
read/write
D[5]
read/write
Default Value
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
12 - 15 = 0Ch - 0Fh; 0Ch = MSB
D[2]
read/write
D[1]
read/write
D[0]
read/write
This four-byte field is the password required for access to the OEM area of the MIC3002’s memory and registers. The byte at
address 12 (0Ch) is the most significant byte. This field is compared to the four-byte OEMPW field at serial address A2h, byte
120 to 123 if OMCFG6-2 = 0, or byte 123 to 126 if OEMCFG6-2 = 1. If the two fields match, access is allowed to the OEM
areas of the MIC3002 non-volatile memory at serial addresses A4h and A6h. The OEM password may be set by writing the
new value into OEMPWSET. The new password will not take effect until after a power-on reset occurs or a warm reset is
performed using the RST bit in OEMCFG0. This allows the new password to be verified before it takes effect. These registers
are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for access to this
register.
Byte
Weight
3
OEM Password, Most Significant Byte
2
OEM Password, 2nd Most Significant Byte
1
OEM Password, 2nd Least Significant Byte
0
OEM Password, Least Significant Byte
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MIC3002
OEM Calibration 0 (OEMCAL0)
D[7]
D[6]
FLTDIS
read/write
reserved
Default Value
D[5]
FSPIN
read/write
D[4]
D[3]
WRINH
APCCAL
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
16 = 10h
D[2]
FRCINT
read/write
D[1]
FRCTXF
read/write
D[0]
FRCLOS
read/write
A valid OEM password is required for access to this register.
Bit
D[7]
Function
Operation
Reserved
Always write as zero; reads undefined.
D[6]
FLTDIS
Fault comparator disable; inhibits output
of fault comparators when set.
0 = faults enabled; 1 = disabled; Read/write.
D[5]
FSPIN
Fault comparator “spin-on-channel” mode
select; do not enable ADC and FC spinon-channel modes simultaneously.
0 = normal operation; 1 = spin on channel; Read/write.
D[4]
WRINH
Inhibit NVRAM write cycles.
0 = normal operation; 1 = inhibit writes; Read/write.
D[3]
APCCAL
Selects APC calibration mode - DACs
may be controlled directly.
0 = normal mode; 1 = calibration mode; Read/write.
D[2]
FRCINT
Forces the assertion of /INT
0 = normal operation; 1 = asserted; Read/write.
D[1]
FRCTXF
Forces the assertion of TXFAULT
0 = normal operation; 1 = asserted; Read/write.
D[0]
FDCLOS
Forces the assertion of RXLOS
0 = normal operation; 1 = asserted; Read/write.
OEM Calibration 1 (OEMCAL1)
D[7]
D[6]
ADSTP
read/write
reserved
Default Value
D[5]
ADIDL
read/write
D[4]
D[3]
1SHOT
ADSPIN
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
17 = 11h
D[2]
SPIN[2]
read/write
D[1]
SPIN[1]
read/write
D[0]
SPIN[0]
read/write
A valid OEM password is required for access to this register.
Bit
D[7]
Function
Operation
Reserved
Always write as zero; reads undefined.
D[6]
ADSTP
Stop ADC Halts the analog to digital
converter
0 = normal operation; 1 = stopped; Read/write.
D[5]
ADIDL
ADC idle flag
0 = busy; 1 = idle; Read/write.
D[4]
1SHOT
Triggers one-shot A/D conversion cycle
0 = normal operation; 1 = one-shot; Read/write.
D[3]
ADSPIN
Selects ADC spin-on-channel mode; do
not enable ADC and FC spin-on-channel
modes simultaneously
0 = normal operation; 1 = spin-on-channel; Read/write.
D[2],
D[1], D[0]
SPIN[2:0]
ADC and fault comparator (FC) channel
select for spin-on-channel mode; do not
enable ADC and FC spin-on-channel
modes simultaneously
ADC: 000 = temperature; 001 = voltage; 010 = VILD;
011 = VMPD; 100 = VRX; FC: 001 = VILD;
001 = VMPD; 010 = VRX; Read/write.
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MIC3002
OEM Calibration 1 (LUT Index)
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
read/write
D[3]
read/write
D[2]
read/write
D[1]
read/write
D[0]
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
18 = 12h
The look-up table index is derived from the current temperature measurement as follows:
INDEX = TAVG / 2
where TAVG(n) is the current average temperature. This register allows the current table index to be read by the host. The table
base address must be added to LUTINDX to form a complete table index in physical memory. A valid OEM password is
required for access to this register. Otherwise, reads are undefined.
OEM Configuration 3 (OEMCFG3)
D[7]
LUTSEL
read/write
Default Value
D[6]
TXFPOL
read/write
D[5]
GPOD
read/write
D[4]
GPOM
read/write
D[3]
GPOC
read/write
D[2]
TXFIN
read/write
D[1]
LOSDIS
read/write
D[0]
INTCAL
read/write
0000 1000b = 08h
Serial Address
A6h
Byte Address
19 = 13h
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to this register. GPOD and GPOC are ignored when GPOM = 0. TXFPOL is ignored if TXFIN = 0.
Bit
Function
Operation
D[7]
LUTSEL
RX power look-up table input
selection bit
1 = RX power;
0 = temperature; read/write; ignored if INTCAL = 0.
D[6]
TXFPOL
TXFIN active polarity select; a fault
is indicated when TXFIN = TXFPOL
0 = active-low;
1 = active-high; read/write; ignored if TXFIN = 0.
D[5]
GPOD
GPO output drive
0 = open drain;
1 = push-pull; read/write; ignored if GPOM = 0.
D[4]
GPOM
GPO/RSOUT mode select
0 = RSOUT; 1 = GPO; read/write.
D[3]
GPOC
GPO output control
0 = low; 1 = high; read/write; ignored if GPOM = 0.
D[2]
TXFIN
TXFIN mode select
0 = SHDN; 1 = TXFIN; read/write.
D[1]
LOSDIS
RXLOS comparator disable
0 = enabled; 1 = disabled; read/write.
D[0]
INTCAL
Calibration mode select
0 = external calibration;
1 = internal calibration; read/write.
BIAS DAC Setting (APCDAC)
Current VBIAS Setting
D[7]
read only
Default Value
D[6]
read only
D[5]
read only
D[4]
read only
D[3]
read only
D[2]
read only
D[1]
read only
D[0]
read only
0000 0000b = 00h
Serial Address
A6h
Byte Address
20 = 14h
This register reflects (reads back) the value set in the APC register (APCSET0, APCSET1, or APCSET2 whichever is
selected). A valid OEM password is required for access to this register.
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MIC3002
Modulation DAC Setting (MODDAC)
Current VMOD Setting
D[7]
read only
Default Value
D[6]
read only
D[5]
read only
D[4]
read only
D[3]
read only
D[2]
read only
D[1]
read only
D[0]
read only
0000 0000b = 00h
Serial Address
A6h
Byte Address
21 = 15h
This register reflects (reads back) the value set in the MODSET register. A valid OEM password is required for access to this
register.
OEM Readback Register (OEMRD)
D[7]
reserved
D[6]
reserved
D[5]
reserved
Default Value
D[4]
D[3]
INT
APCSAT
read only
read only
0000 0000b = 00h
Serial Address
A6h
Byte Address
22 = 16h
D[2]
IBFLT
read only
D[1]
TXFLT
read only
D[0]
RSOUT
read only
This register reflects (reads back) the status of the bits corresponding to the parameters defined below. A valid OEM password
is required for access to this register. Otherwise, reads are undefined and writes are ignored.
Bit
D[7:5]
Function
Operation
Reserved
Always write as zero; reads undefined.
Mirrors state of /INT but active-high;
not state of physical pin!
1 = interrupt; 0 = no interrupt.
D[4]
INT
D[3]
APCSAT
APC saturation fault comparator
output state
1 = fault; 0 = normal operation.
D[2]
IBFLT
State of IBIAS over-current fault
comparator output
1 = fault; 0 = normal operation; read-only.
D[1]
TXFLT
State of transmit power fault
comparator output
1 = fault; 0 = normal operation; read-only.
D[0]
RSOUT
State of the rate select output pin,
RSOUT
1 = high; 0 = low; Read-only.
Signal Detect Threshold (LOSFLTn)
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
23 = 17h
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register works in conjunction with the LOSFLT register to control the operation of the loss of signal comparator. The
comparator’s output, RXLOS, is asserted when the input on VRX falls below the level in LOSFLT. The output will then be deasserted when the VRX signal rises above LOSFLTn. The input signal is subject to scaling by the RXPOT. If the LOS
comparator is disabled, i.e., LOSDIS = 1, this register is ignored. A valid OEM password is required for access to this register.
This register is non-volatile and will be maintained through power and reset cycles.
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MIC3002
RX EEPOT Tap Selection (RXPOT)
D[7]
reserved
Default Value
D[6]
reserved
D[5]
reserved
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
24 = 18h
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bit(s)
Function
Operation
D[7:5]
Reserved
Reserved. Always write as zero; reads undefined.
D[4:0]
RXPOT tap selection:
Read/write; non-volatile.
00000 = No divider action; POT
disconnected
00001 = 31/32
00010 = 30/32
•
•
•
11110 = 2/32
11111 = 1/32
OEM Configuration 4 (OEMCFG4)
D[7]
reserved
Default Value
D[6]
reserved
D[5]
reserved
D[4]
D[3]
reserved
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
25 = 19h
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bit(s)
Function
Operation
D[7]
Allows Warnings to assert
TXFAULT
0: Warnings do not assert TXFAULT
1: Warnings assert TXFAULT
The RXPWR low warning flag does not assert TXFAULT
D[6]
Allows Alarms to assert
TXFAULT
0: Alarms do not assert TXFAULT
1: Alarms assert TXFAULT
The RXPWR low alarm flag does not assert TXFAULT
D[5]
Warning Latch
0: Warnings flags are latched. They are cleared by reading the register or
toggling TXDISABLE.
1: Warnings flags are not latched., i.e. they are set and reset with alarm
condition. The flags are also cleared by reading the register or toggling
TXDISABLE.
D[4]
Alarm Latch
0: Alarms flags are latched. They are cleared by reading the register or
toggling TXDISABLE.
1: Alarms flags are not latched., i.e. they are set and reset with alarm
condition. The flags are also cleared by reading the register or toggling
TXDISABLE.
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ISTART[3:0]
MIC3002
ISTART current level selection:
Read/write; non-volatile.
0000 = No ISTART current
0001 - 1111 = 0.375mA x
ISTART[3:0]
ISTART is used to speed up
the laser start-up after a fault
occurs. The charging current
of the compensation cap starts
from ISTART instead of
ramping up from 0.
OEM Configuration 5 (OEMCFG5)
D[7]
reserved
Default Value
D[6]
reserved
D[5]
reserved
D[4]
D[3]
reserved
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
26 = 1Ah
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bit(s)
Function
D[7]
SHDN output enable / disable
Operation
0: SHDN is enabled. TXFAULT will trigger SHDN output
1: SHDN is disabled. TXFAULT has no effect on SHDN output
This applies when pin 7 is set as SHDN output.
D[6]
D[5]
D[4]
Temperature-compensation of
the temperature used to access
the L.U.T.s.
0: The temperature used to index into the LUTs is not compensated (sensed
temperature used)
Temperature-compensation of
the temperature result in the
temperature register.
0: The temperature result in the temperature register is not compensated
(sensed temperature sed)
Polarity of TXFAULT
0: TXFAULT is active high
1: The temperature used to index the LUTs is temperature-compensated
(module case temperature used)
1: The temperature result in the temperature register is compensated
(module case temperature used)
1: TXFAULT is active low
D[3]
SMBUS multipart support
D[2]
OEM password location
0: Multipart mode off
1: Multipart mode on
0: A6h 120-123 (78h-7Bh)
1: A6h 123-126 (7Bh-7Eh)
D[1]
D[0]
SMBUS timeout enable /
disable
0: SMBUS timeout enabled
DACs reset
0: Clear DACs when the laser is off
1: SMBUS timeout disabled
1: Do not clear the DACs when laser is off
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MIC3002
OEM Configuration 6 (OEMCFG6)
D[7]
reserved
Default Value
D[6]
reserved
D[5]
reserved
D[4]
D[3]
reserved
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
27 = 1Bh
D[2]
read/write
D[1]
read/write
D[0]
read/write
This register is non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bit(s)
Function
D[5-7]
Reserved
D[4]
TXDISABLE debounce enable
/ disable
0: TXDISABLE is not debounced
RXLOS Polarity
0: RXLOS low for normal operation and high with a loss of signal condition.
D[3]
Operation
1: TXDISABLE is debounced. Glitches less than 5 ms are rejected. Set the
bit to 1 is a mechanical switch is used for TXDISABLE. Set to 0 for normal
operation to assure compliance to the SFP MSA.
1: RXLOS high for normal operation (signal detected) and low with a loss of
signal (no signal detected) condition.
D[2]
USRCTRL register location
0: A2 255 (FFh)
1: A2 222 (DEh)
D[1]
Temperature resolution
0: Temperature is measured to a resolution of 1ºC
1: Temperature is measured to a resolution of 0.5ºC
D[0]
TXFAULT clear mode
0: TXFAULT remains set until TXDISABLE is toggled
1: TXFAULT is in continuous mode and follows the state of the faults.
Power-On Hour Meter Data (POHDATA)
D[7]
read/write
Default Value
D[6]
read/write
D[5]
read/write
D[4]
D[3]
read/write
read/write
0000 0000b = 00h
Serial Address
A6h
Byte Address
32-39 = 20h - 27h
D[2]
read/write
D[1]
read/write
D[0]
read/write
These registers are used for backing up the POH result during power cycles. At power-up, the POH meter selects the larger of
the two values as the initial count. Incremental results are stored in alternate register pairs. The power-on hour meter may be
reset or preset by writing to these registers. These registers are non-volatile and will be maintained through power and reset
cycles. A valid OEM password is required for access to these registers.
Byte
July 2007
Weight
3
POHA, high-byte
2
POHA, low-byte
1
POHB, high-byte
0
POHB, low-byte
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MIC3002
OEM Scratchpad Registers (SCRATCHn)
Default Value
0000 0000b = 00h
Serial Address
A6h
Byte Address
135-143 (87-8Fh)
156-159 (9C-9Fh)
172-175 (AC-AFh)
188-191 (BC-BFh)
204-207 (CC-CFh)
222-250 (DE-FAh)
The scratchpad registers are general-purpose non-volatile memory locations. They can be freely read from and written to any
time the MIC3002 is in OEM mode.
RX Power Look-up Table (RXLUTn)
Default Value
0000 0000b = 00h
Serial Address
A6h
Byte Address
40-71 = 28h - 47h
These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
Bytes
Definition
RXSLP0h
RX Slope 0, High Byte.
RXSLP0l
RX Slope 0, Low Byte.
RXOFF0h
RX Offset 0, High Byte.
RXOFF0l
RX Offset 0, Low Byte.
RXSLP1h
RX Slope 1, High Byte.
RXSLP1l
RX Slope 1, Low Byte.
RXOFF1h
RX Offset 1, High Byte.
RXOFF1l
•
•
•
RXSLP7h
RX Offset 1, Low Byte.
•
•
•
RX Slope 7, High Byte.
RXSLP7l
RX Slope 7, Low Byte.
RXOFF7h
RX Offset 7, High Byte.
RXOFF7l
RX Offset 7, Low Byte.
Calibration Constants (CALn)
Default Value
0000 0000b = 00h
Serial Address
A6h
Byte Address
74 - 87 = 4A h - 57h
These registers are non-volatile and will be maintained through power and reset cycles. A valid OEM password is required for
access to these registers.
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MIC3002
Bytes
Definition
VSLP0h
Voltage Slope, High Byte.
VSLP0l
Voltage Slope, Low Byte.
VOFFh
Voltage Offset, High Byte.
VOFF0l
Voltage Offset, Low Byte.
ISLP0h
Bias Current Slope, High Byte.
ISLP0l
Bias Current Slope, Low Byte.
IOFFh
Bias Current Offset, High Byte.
IOFF0l
Bias Current Offset, Low Byte.
TXSLPh
TX Power Slope, High Byte.
TXSLPl
TX Power Slope, Low Byte.
TXOFFh
TX Power Offset, High Byte.
TXOFFl
TX Power Offset, Low Byte.
Manufacturer ID Register (MFG_ID)
Identifies Micrel as the manufacturer of the device. Always returns 2Ah
D[7]
read only
Default Value
D[6]
read only
D[5]
read only
D[4]
D[3]
read only
read only
0010 1010b = 2Ah
Serial Address
A6h
Byte Address
254 = FEh
D[2]
read only
D[1]
read only
D[0]
read only
The value in this register, in combination with the DEV_ID register, serve to identify the MIC3002 and its revision number to
software. This register is read-only.
Bit(s)
Function
Operation
D[7:0]
Identifies Micrel as the manufacturer of the device. Always
returns 2Ah.
Read only. Always returns Ah
Device ID Register (DEV_ID)
D[7]
read only
D[6]
read only
D[5]
read only
D[4]
read only
D[3]
read only
MIC3002 DEVICE ID
always reads 0 at D[5-7] and 1 at D[4]
Default Value
0001 xxxxb = 1xh
Serial Address
A6h
Byte Address
255 = FFh
D[2]
read only
D[1]
read only
D[0]
read only
DIE REVISION
The value in this register, in combination with the MFG_ID register, serve to identify the MIC3002 and its revision number to
software. This register is read-only.
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MIC3002
Package Information
24-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury
to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and
Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2007 Micrel, Incorporated.
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