IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK™ FEATURES: DESCRIPTION: • • • • The IDT5V991A is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V991A has eight programmable skew outputs in four banks of 2. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and 3Q1 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. Both devices have LVTTL outputs with 12mA balanced drive outputs. REF is 5V tolerant 4 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Output frequency: 3.75MHz to 85MHz 2x, 4x, 1/2, and 1/4 outputs 3 skew grades: IDT5V991A-2: tSKEW0<250ps IDT5V991A-5: tSKEW0<500ps IDT5V991A-7: tSKEW0<750ps 3-level inputs for skew and PLL range control PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <200ps peak-to-peak Available in 32-pin PLCC Package • • • • • • • • • • FUNCTIONAL BLOCK DIAGRAM GND/sOE 1Q0 Skew Select 1Q1 3 3 1F1:0 VCCQ/PE 2Q0 Skew Select 2Q1 3 3 REF PLL 2F1:0 FB 3 FS 3Q0 Skew Select 3Q1 3 3 3F1:0 4Q0 Skew Select 4Q1 3 3 4F1:0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SEPTEMBER 2001 1 c 2001 Integrated Device Technology, Inc. DSC 5963/3 IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 2F 1 2 TEST V C CQ 3 REF FS 4 Description Supply Voltage to Ground GND 3F 0 Symbol 1 32 31 30 VI Max Unit –0.5 to +7 V DC Input Voltage –0.5 to VCC+0.5 V REF Input Voltage –0.5 to +5.5 V 3F 1 5 29 2F 0 TJ Junction Temperature 150 °C 4F 0 6 28 GND/sO E TSTG Storage Temperature –65 to +150 °C 4F 1 7 27 1F 1 V CCQ /PE 8 26 1F 0 V CC N 9 25 V CC N 4Q 1 10 24 1Q 0 4Q 0 11 23 1Q 1 G ND 12 22 GND G ND 13 21 GND 19 CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V) 20 Parameter 2Q 0 18 2Q 1 FB 17 V C CN 16 V C CN 15 3Q 0 3Q 1 14 NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. CIN PLCC TOP VIEW Description Input Capacitance Typ. Max. Unit 5 7 pF NOTE: 1. Capacitance applies to all inputs except TEST, FS, and nF1:0. PIN DESCRIPTION Pin Name Type Description REF IN Reference Clock Input FB IN Feedback Input TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control Summary Table) remain in effect. Set LOW for normal operation. GND/ sOE (1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation. VCCQ/PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions FS IN nQ[1:0] OUT Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.) VCCN PWR Power supply for output buffers VCCQ PWR Power supply for phase locked loop and other internal circuitry GND PWR Ground Four banks of two outputs with programmable skew NOTE: 1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. PROGRAMMABLE SKEW Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see PLL Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins. 2 IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES EXTERNAL FEEDBACK By providing external feedback, the IDT5V991A gives users flexibility with regard to skew adjustment. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE FS = LOW FS = MID FS = HIGH Timing Unit Calculation (tU) 1/(44 x FNOM) 1/(26 x FNOM) 1/(16 x FNOM) VCO Frequency Range (FNOM)(1,2) 15 to 35MHz 25 to 60MHz 40 to 85 MHz ±9.09ns ±9.23ns ±9.38ns Comments Skew Adjustment Range(3) Max Adjustment: ns ±49º ±83º ±135º Phase Degrees ±14% ±23% ±37% % of Cycle Time Example 1, FNOM = 15MHz tU = 1.52ns — — Example 2, FNOM = 25MHz tU = 0.91ns tU = 1.54ns — Example 3, FNOM = 30MHz tU = 0.76ns tU = 1.28ns — Example 4, FNOM = 40MHz — tU = 0.96ns tU = 1.56ns Example 5, FNOM = 50MHz — tU = 0.77ns tU = 1.25ns Example 6, FNOM = 80MHz — — tU = 0.78ns NOTES: 1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest. 2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value. CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS nF1:0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4) LL(1) –4tU Divide by 2 Divide by 2 LM –3tU –6tU –6tU LH –2tU –4tU –4tU ML –1tU –2tU –2tU MM Zero Skew Zero Skew Zero Skew MH 1tU 2tU 2tU HL 2tU 4tU 4tU HM 3tU 6tU 6tU HH 4tU Divide by 4 Inverted(2) NOTES: 1. LL disables outputs if TEST = MID and GND/sOE = HIGH. 2. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when VCCQ/PE = HIGH, GND/sOE disables pair #4 LOW when VCCQ/PE = LOW. 3 IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RECOMMENDED OPERATING RANGE Symbol Description Vcc Power Supply Voltage TA Ambient Operating Temperature IDT5V991A-2, -5, -7 IDT5V991A-2 (Industrial) (Commercial) Min. Max. Min. Max. Unit 3 3.6 3 3.6 V -40 +85 0 +70 °C DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage (1) Conditions Min. Max. Unit Guaranteed Logic HIGH (REF, FB Inputs Only) 2 — V Guaranteed Logic LOW (REF, FB Inputs Only) — 0.8 V VIHH Input HIGH Voltage VIMM Input MID Voltage(1) VILL Input LOW Voltage(1) IIN Input Leakage Current (REF, FB Inputs Only) VCC = Max. VCC−0.6 3-Level Inputs Only — V VCC/2−0.3 VCC/2+0.3 V 3-Level Inputs Only — 0.6 V VIN = VCC or GND — ±5 µA 3-Level Inputs Only VIN = VCC HIGH Level — ±200 I3 3-Level Input DC Current (TEST, FS, nF1:0) VIN = VCC/2 MID Level — ±50 VIN = GND LOW Level — ±200 IPU Input Pull-Up Current (VCCQ/PE) VCC = Max., VIN = GND — ±100 µA IPD Input Pull-Down Current (GND/sOE) VCC = Max., VIN = VCC — ±100 µA VOH Output HIGH Voltage VCC = Min., IOH = −12mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 12mA — 0.55 V µA NOTE: 1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. POWER SUPPLY CHARACTERISTICS Test Conditions(1) Symbol Parameter ICCQ Quiescent Power Supply Current VCC = Max., TEST = MID, REF = LOW, Typ.(2) Max. Unit 8 25 mA 1 30 μA μA/MHz VCCQ/PE = LOW, GND/sOE = LOW All outputs unloaded ΔICC Power Supply Current per Input HIGH VCC = Max., VIN = 3V ICCD Dynamic Power Supply Current per Output VCC = Max., CL = 0pF ITOT Total Power Supply Current 55 90 CL = 160pF(1) 29 — VCC = 3.3V, FREF = 33MHz, CL = 160pF(1) 42 — CL = 160pF(1) 76 — VCC = 3.3V, FREF = 20MHz, VCC = 3.3V, FREF = 66MHz, mA NOTE: 1. For eight outputs, each loaded with 20pF. INPUT TIMING REQUIREMENTS Description (1) Symbol Min. Max. Unit — 10 ns/V tR, tF Maximum input rise and fall times, 0.8V to 2V tPWC Input clock pulse, HIGH or LOW 3 — ns DH Input duty cycle 10 90 % REF Reference Clock Input 3.75 85 MHz NOTE: 1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies. 4 IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT5V991A-2 Symbol Parameter Min. Typ. IDT5V991A-5 Max. Min. Typ. IDT5V991A-7 Max. Min. FNOM VCO Frequency Range tRPWH REF Pulse Width HIGH(11) 3 — — 3 — — 3 tRPWL REF Pulse Width LOW(11) 3 — — 3 — — 3 tU Typ. Max. Unit — — ns — — ns See PLL Programmable Skew Range and Resolution Table Programmable Skew Time Unit See Control Summary Table (1,2,3) tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1) — 0.05 0.2 — 0.1 0.25 — 0.1 0.25 ns tSKEW0 Zero Output Skew (All Outputs)(1,4,5) — 0.1 0.25 — 0.25 0.5 — 0.3 0.75 ns tSKEW1 Output Skew — 0.25 0.5 — 0.6 0.7 — 0.6 1 ns — 0.3 1.2 — 0.5 1.2 — 1 1.5 ns — 0.25 0.5 — 0.5 0.7 — 0.7 1.2 ns — 0.5 0.9 — 0.5 1 — 1.2 1.7 ns — — 0.75 — — 1.25 — — 1.65 ns 0 0.5 0 0.7 ns (Rise-Rise, Fall-Fall, Same Class Outputs)(1,6) tSKEW2 Output Skew (1,6) (Rise-Fall, Nominal-Inverted, Divided-Divided) tSKEW3 Output Skew (1,6) (Rise-Rise, Fall-Fall, Different Class Outputs) tSKEW4 Output Skew (1,2) (Rise-Fall, Nominal-Divided, Divided-Inverted) tDEV Device-to-Device Skew(1,2,7) tPD REF Input to FB Propagation Delay(1,9) tODCV Output Duty Cycle Variation from 50%(1) tPWH Output HIGH Time Deviation from 50%(1,10) tPWL Output LOW Time Deviation from 50% (1) tORISE Output Rise Time tOFALL Output Fall Time(1) tLOCK tJR PLL Lock Time (1,11) (1,8) Cycle-to-Cycle Output Jitter(1) −0.25 −1.2 0 0.25 0 1.2 −0.5 −1.2 0 1.2 −0.7 −1.2 0 1.2 ns — — 2 — — 2.5 — — 3 ns — — 1.5 — — 3 — — 3.5 ns 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns — — 0.5 — — 0.5 — — 0.5 ms RMS — — 25 — — 25 — — 25 ps Peak-to-Peak — — 200 — — 200 — — 200 NOTES: 1. All timing and jitter tolerances apply for FNOM > 25MHz. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. 4. tSKEW0 is the skew between outputs when they are selected for 0tU. 5. For IDT5V991A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max. 6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divideby-4 mode). 7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) 8. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 9. tPD is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns. 10. Measured at 2V. 11. Measured at 0.8V. 5 IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TEST LOADS AND WAVEFORMS VC C 150 Ω O utput 150 Ω 20pF Test Load t O FALL t OR ISE t PW H 2.0V 0.8V tP W L LVTTL Output Waveform ≤ 1ns 3.0V 2.0V Vth = 1.5V 0.8V 0V LVTTL Input Test Waveform 6 ≤ 1ns IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TIMING DIAGRAM tR P W L t R EF tR P W H RE F tP D tO D C V tO D C V FB t JR Q t S KE W P R t SK E W 0, 1 t S KE W P R t S K EW 0, 1 O TH ER Q t S KE W 2 tS K E W 2 IN V ER TE D Q t SK EW 3, 4 t SK EW 3, 4 t SK E W 3, 4 t SK EW 2, 4 R EF D IVID E D B Y 2 t SK E W 1 , 3 , 4 R EF D IVID E D B Y 4 NOTES: V CCQ/PE: The AC Timing Diagram applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ω to VCC/2. tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0tU. tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tPWH is measured at 2V. tPWL is measured at 0.8V. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 7 IDT5V991A 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) J JG Rectangular Plastic Leaded Chip Carrier PLCC - Green 5V991A-2 5V991A-5 5V991A-7 3.3V Programmable Skew PLL Clock Driver TurboClock CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 8 for Tech Support: [email protected]