LINER LTC1662IN8 Ultralow power, dual 10-bit dac in msop Datasheet

LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
DESCRIPTIO
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FEATURES
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The LTC®1662 is an ultralow power, fully buffered voltage output, dual 10-bit digital-to-analog converter (DAC).
Each DAC channel draws just 1.7µA (typ) total supplyplus-reference operating current, yet is capable of supplying DC output currents in excess of 1mA and reliably
driving capacitive loads of up to 1000pF. A programmable Sleep mode further reduces total operating current to 0.05µA.
Ultralow Power: 1.5µA (Typ) ICC per DAC Plus
0.05µA Sleep Mode for Extended Battery Life
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
Wide 2.7V to 5.5V Supply Range
Double Buffered for Simultaneous DAC Updates
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V-to-VCC Output
Reference Input Impedance Is Code-Independent
(7.1MΩ Typ)—Eliminates External Buffers
3-Wire Serial Interface with
Schmitt Trigger Inputs
Differential Nonlinearity: ±0.75LSB Max
Linear Technology’s proprietary, inherently monotonic
architecture provides excellent linearity and an exceptionally small external form factor. The double-buffered input
logic provides simultaneous update capability and can be
used to write to the DACs without interrupting Sleep mode.
With its tiny operating current and exceptionally small
size, the LTC1662 is ideal for use in the most powerconstrained products. For most designs, there is no
perceptible impact on the power budget; the LTC1662
draws many times less current than even a trimpot, while
providing buffered, low impedance (0.5Ω typical,
VCC = 5V) rail-to-rail outputs.
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APPLICATIO S
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Mobile Communications
Portable Battery-Powered Instruments
Remote or Inaccessible Adjustments
Digitally Controlled Amplifiers and Attenuators
Factory or Field Calibration
The LTC1662 is pin and software compatible with the
LTC1661 dual, 60µA 10-bit DAC. It is available in 8-pin
MSOP and PDIP packages and is specified over the
industrial temperature range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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BLOCK DIAGRA
5
10-BIT
DAC A
LATCH
VOUT B
6
LATCH
VCC
7
LATCH
GND
8
LATCH
VOUT A
Total Supply-Plus-Reference
Operating Current
5.0
10-BIT
DAC B
4.5
5.5V
4.5V
4.0
CONTROL
LOGIC
ICC + IREF (µA)
3.5
ADDRESS
DECODER
3.0
2.5
3.6V
2.0
VCC = 2.7V
1.5
1.0
SHIFT REGISTER
0.5
VREF = VCC
CODE = 1023
0
–55 –35 –15
1
2
3
CS/LD
SCK
SDI
4
REF
5 25 45 65 85 105 125
TEMPERATURE (°C)
1662 G02
1662 BD
1
LTC1662
W W
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AXI U
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ABSOLUTE
RATI GS
(Note 1)
VCC to GND .............................................. – 0.3V to 7.5V
Logic Inputs to GND ................................ – 0.3V to 7.5V
VOUT A, VOUT B, REF to GND ......... – 0.3V to (VCC + 0.3V)
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Operating Temperature Range
LTC1662C ............................................. 0°C to 70°C
LTC1662I ........................................... – 40°C to 85°C
Lead Temperature (Soldering, 10 sec)................ 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
CS/LD
SCK
SDI
REF
1
2
3
4
8
7
6
5
VOUT A
GND
VCC
VOUT B
LTC1662CMS8
LTC1662IMS8
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
TJMAX = 125°C, θJA = 150°C/W
LTKB
LTKC
ORDER PART
NUMBER
TOP VIEW
CS/LD 1
8
VOUT A
SCK 2
7
GND
SDI 3
6
VCC
REF 4
5
VOUT B
LTC1662CN8
LTC1662IN8
N8 PACKAGE
8-LEAD PLASTIC DIP
TJMAX = 125°C, θJA = 100°C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Accuracy
Resolution
DNL
●
10
Bits
Monotonicity
(Note 2)
●
10
Bits
Differential Nonlinearity
(Note 2)
●
±0.12
±0.75
LSB
INL
Integral Nonlinearity
(Note 2)
●
±0.8
±4
LSB
VOS
Offset Error
VCC = 5V, VREF = 4.096V, Measured at Code 20
●
±5
±25
mV
VOS TC
VOS Temperature Coefficient
GE
Gain Error
GE TC
Gain Error Temperature
Coefficient
PSR
Power Supply Rejection
±15
VCC = 5V, VREF = 4.096V
±1
●
VREF = 2.5V
µV/°C
±8
LSB
±12
µV/°C
0.18
LSB/V
Reference Input
Input Voltage Range
Input Resistance
Input Capacitance
2
Active Mode
Sleep Mode
●
0
●
3.9
VCC
V
7.1
2.5
MΩ
GΩ
10
pF
LTC1662
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT Unloaded
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
ICC
Supply Current
VCC = 3V (Note 3)
VCC = 5V (Note 3)
VCC = 3V (Note 3)
VCC = 5V (Note 3)
●
2.7
5.5
V
3.0
3.5
4.0
4.5
5.0
5.5
µA
µA
µA
µA
0.05
0.10
0.18
µA
µA
●
●
Sleep Mode Operating Current Supply Plus Reference Current, VCC = VREF = 5V (Note 3)
●
DC Performance
Short-Circuit Current Low
VOUT = 0V, VCC = VREF = 5V, Code = 1023 (Note 7)
●
5
12
70
mA
Short-Circuit Current High
VOUT = VCC = VREF = 5V, Code = 0 (Note 7)
●
3
10
80
mA
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
Voltage Output Settling Time
Rising 0.1VFS to 0.9VFS ±0.5LSB (Notes 4, 5)
Falling 0.9VFS to 0.1VFS ±0.5LSB (Notes 4, 5)
20
7
Capacitive Load Driving
V/ms
V/ms
0.40
0.75
ms
ms
1000
pF
Digital I/O
VIH
Digital Input High Voltage
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
●
●
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
●
●
ILK
Digital Input Leakage
VIN = GND to VCC
●
CIN
Digital Input Capacitance
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TI I G CHARACTERISTICS
2.4
2.0
V
V
±0.05
0.8
0.6
V
V
±1.0
µA
1.5
pF
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
55
15
MAX
UNITS
VCC = 4.5V to 5.5V
t1
SDI Setup
Relative to SCK Positive Edge
●
t2
t3
ns
SDI Hold
Relative to SCK Positive Edge
●
0
– 10
ns
SCK High Time
(Note 6)
●
30
14
ns
t4
SCK Low Time
(Note 6)
●
30
14
ns
t5
CS/LD Pulse Width
(Note 6)
●
100
27
ns
t6
LSB SCK High to CS/LD High
(Note 6)
●
30
2
ns
t7
CS/LD Low to SCK High
(Note 6)
●
20
– 21
ns
t9
SCK Low to CS/LD Low
(Note 6)
●
0
–5
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
●
20
0
SCK Frequency
Square Wave (Note 6)
●
Relative to SCK Positive Edge (Note 6)
●
ns
16.7
MHz
VCC = 2.7V to 5.5V
t1
SDI Setup
t2
SDI Hold
Relative to SCK Positive Edge (Note 6)
t3
SCK High Time
(Note 6)
t4
SCK Low Time
(Note 6)
75
20
ns
●
0
– 10
ns
●
50
15
ns
●
50
15
ns
3
LTC1662
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
t5
CS/LD Pulse Width
(Note 6)
t6
LSB SCK High to CS/LD High
(Note 6)
t7
CS/LD Low to SCK High
t9
SCK Low to CS/LD Low
t11
●
150
30
ns
●
50
3
ns
(Note 6)
●
30
– 14
ns
(Note 6)
●
0
–5
ns
CS/LD High to SCK Positive Edge
(Note 6)
●
30
0
SCK Frequency
Square Wave (Note 6)
●
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V,
VREF = 4.096V, from code 20 to code 1023. See Figure 2.
Note 3: Digital inputs at 0V or VCC.
MAX
UNITS
ns
10
MHz
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS; i.e.,
codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
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TYPICAL PERFOR A CE CHARACTERISTICS
Total Supply-Plus-Reference
Operating Current
Supply Current vs Temperature
5.0
4.5
4.0
4.5V
4.5V
2.5
2.0
3.6V
VCC = 2.7V
2.5
VCC = 2.7V
0.5
0.5
VREF = VCC
CODE = 1023
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1
5 25 45 65 85 105 125
TEMPERATURE (°C)
1662 G01
0.6
0.5
0.4
0.3
0.2
3
2
1
0
–1
–2
0.1
–3
0
–4
1.5
1 1.5 2 2.5 3 3.5 4
LOGIC INPUT VOLTAGE (V)
4.5
10k 100k 1M
FREQUENCY (Hz)
5
1662 G04
10M 100M
0.75
0.60
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
0.7
0
1k
Differential Nonlinearity (DNL)
4
VCC = 5V
ALL DIGITAL INPUTS
SHORTED TOGETHER
0.8
100
1662 G03
Integral Nonlinearity (INL)
1.0
ICC (mA)
10
1662 G02
Supply Current vs Logic Input
Voltage
0.9
VCC = 3V
10
1.5
1.0
0
–55 –35 –15
3.6V
2.0
1.0
VCC = 5V
100
3.0
ICC (µA)
ICC + IREF (µA)
3.5
3.0
1.5
CS/LD = LOGIC LOW
CODE = 0
5.5V
4.0
5.5V
3.5
ICC (µA)
1000
5.0
VREF = VCC
CODE = 1023
4.5
4
Supply Current vs Clock
Frequency
0.40
0.20
0
–0.20
–0.40
–0.60
–0.75
0
256
512
CODE
768
1023
1662 G05
0
256
512
CODE
768
1023
1662 G06
LTC1662
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TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity (INL) vs
Reference Voltage
Differential Nonlinearity (DNL) vs
Reference Voltage
4
Offset Voltage vs Temperature
0
0.75
VCC = 5.5V
3
VCC = 5V
VREF = 4.096V
VCC = 5.5V
0.50
–1
MAX POS INL
0
–1
MAX NEG INL
0.25
OFFSET ERROR (mV)
1
PEAK DNL (LSB)
PEAK INL (LSB)
2
MAX POS DNL
0
MAX NEG DNL
–0.25
–2
–3
–2
–4
–0.50
–3
–4
1
2
3
4
5
0
6
1
2
3
4
5
Load Regulation vs Output
Current at 5V
Gain Error vs Temperature
0
1.0
VREF = VCC = 5V
VOUT = 2.5V
CODE = 512
TA = 25°C
0.8
–1
0.6
–3
0.6
0.4
0.2
0
–0.2
SOURCE
–0.8
105
–5 –4 –3 –2 –1 0 1
IOUT (mA)
2
3
4
–1 –0.8–0.6–0.4– 0.2 0 0.2 0.4 0.6 0.8
IOUT (mA)
5
Output Amplifier Current Sinking
Capability (Midscale)
5.0
Max/Min Output Voltage vs Source/
Sink Output Current (VCC = 5V)
5.0
3.0
4.0
VCC = 5.5V
VCC = 5V
VCC = 4.5V
3.5
2.5
2.0
1.5
3.0
4.5
3.5
2.5
2.0
1.5
VCC = 3.6V
VCC = 3V
VCC = 2.7V
1.0
0.5
0.5
10µ
100µ
1m
10m
OUTPUT SOURCE CURRENT (A)
100m
1662 G13
VREF = VCC
TA = 25°C
2.5
2.0
1.0
CODE = 0
0.5
0
1µ
3.0
1.5
VCC = 3.6V
VCC = 3V
VCC = 2.7V
1.0
0
CODE = 1023
4.0
VCC = 5.5V
VCC = 5V
VCC = 4.5V
VOUT (V)
3.5
5.0
VREF = VCC
CODE = 512
TA = 25°C
4.5
VOUT (V)
4.0
1
1662 G12
1662 G11
Output Amplifier Current Sourcing
Capability (Midscale)
VREF = VCC
CODE = 512
TA = 25°C
SINK
–1.0
1662 G10
4.5
SOURCE
–0.8
SINK
–1.0
85
0
–0.2
–0.6
–0.6
–5
–55 –35 –15 5
25 45 65
TEMPERATURE (°C)
0.2
–0.4
–0.4
–4
VREF = VCC = 3V
VOUT = 1.5V
CODE = 512
TA = 25°C
0.8
∆VOUT (LSB)
∆VOUT (LSB)
0.4
–2
105
Load Regulation vs Output
Current at 3V
1.0
VCC = 5V
VREF = 4.096V
85
1662 G09
1662 G08
1662 G07
GAIN ERROR (mV)
6
VREF (V)
VREF (V)
VOUT (V)
–5
–55 –35 –15 5
25 45 65
TEMPERATURE (°C)
–0.75
0
0
1µ
10µ
100µ
1m
10m
OUTPUT SINK CURRENT (A)
100m
1662 G14
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
OUTPUT SOURCE/SINK CURRENT (mA)
5
1662 G15
5
LTC1662
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TYPICAL PERFOR A CE CHARACTERISTICS
Max/Min Output Voltage vs Source/
Sink Output Current (VCC = 3V)
Output Minimum Series
Resistance vs Load Capacitance
Large-Signal Step Response
3.0
180
MINIMUM SERIES RESISTANCE (Ω)
5
2.7
CODE = 1023
2.4
4
1.8
VOUT (V)
VOUT (V)
2.1
VREF = VCC
TA = 25°C
1.5
1.2
3
2
0.9
0.6
CODE = 0
1
VREF = VCC = 5V
10% TO 90% STEP
0.3
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
OUTPUT SOURCE/SINK CURRENT (mA)
2
140
120
100
80
60
40
20
0
100p 1000p 0.01µ 0.1µ
1µ
CAPACITANCE (F)
0
0
TIME (0.5ms/DIV)
1662 G16
160
1662 G17
10µ
100µ
1662 G18
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PI FU CTIO S
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on SDI
into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the Control
code, A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 3): Serial Interface Data Input. Input word data on
the SDI pin is shifted into the 16-bit register on the rising
edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs.
The output range is
 1023 
0 ≤ VOUTA , VOUTB ≤ VREF 

 1024 
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
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DEFI ITIO S
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
where ∆VOUT is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Figure 2).
6
Gain Error (GE): The deviation from the slope of the ideal
DAC transfer function, expressed in LSBs at full scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is calculated
as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
LTC1662
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DEFI ITIO S
where VOUT is the output voltage of the DAC measured at
the given input code.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Figure 2).
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
LSB = VREF/1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
WU
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TI I G DIAGRA
t1
t2
t3
t6
t4
SCK
t9
t11
SDI
A3
t5
A1
A2
X1
X0
t7
CS/LD
1662 TD
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OPERATIO
SCK
SDI
1
A3
2
A2
3
A1
CONTROL CODE
4
A0
5
D9
6
D8
7
D7
8
D6
9
D5
10
D4
11
D3
INPUT CODE
12
D2
13
D1
14
D0
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(INSTRUCTION
EXECUTED) 1662 F01
(SCK ENABLED)
Figure 1. Register Loading Sequence
7
LTC1662
U
OPERATIO
Table 1. DAC Control Functions
CONTROL
A3 A2 A1 A0
INPUT REGISTER
STATUS
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE)
COMMENTS
0
0
0
0
No Change
No Update
No Change
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
0
0
0
1
Load DAC A
No Update
No Change
Load Input Register A with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
0
0
1
0
Load DAC B
No Update
No Change
Load Input Register B with Data. DAC Outputs
Unchanged. Power-Down Status Unchanged
1
0
0
0
No Change
Update Outputs
Wake
Load Both DAC Regs with Existing Contents of Input
Regs. Outputs Update. Part Wakes Up
1
0
0
1
Load DAC A
Update Outputs
Wake
Load Input Reg A. Load DAC Regs with New Contents
of Input Reg A and Existing Contents of Reg B. Outputs
Update. Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing Contents
of Input Reg A and New Contents of Reg B. Outputs
Update. Part Wakes Up
1
1
0
1
No Change
No Update
Wake
Part Wakes Up. Input and DAC Regs Unchanged. DAC
Outputs Reflect Existing Contents of DAC Regs
1
1
1
0
No Change
No Update
Sleep
Part Goes to Sleep. Input and DAC Regs Unchanged. DAC
Outputs Set to High Impedance State
1
1
1
1
Load DACs A, B
with Same
10-Bit Code
Update Outputs
Wake
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
Note: All control codes other than those shown are undefined and not subject to test.
Transfer Function
The transfer function for the LTC1662 is:
 k 
VOUT(IDEAL) = 
 VREF
 1024 
at VCC (Pin 6) is in transition. If it is not possible to
sequence the supplies, clamp the voltage at REF by
connecting a Schottky diode between Pin 4 (anode) and
Pin 6 (cathode).
Serial Interface
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 4).
See Table 2. The 16-bit Input word consists of the 4-bit
Control code, the 10-bit Input code and two don’t-care bits.
Power-On Reset
Table 2. LTC1662 Input Word
The LTC1662 actively clears the outputs to zero scale
when power is first applied, making system initialization
consistent and repeatable.
Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Control Code
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage
8
Input Code
Don’t
Care
After the Input word is loaded into the register (see Figure␣ 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide Input code data path is then buffered
by two latch registers.
LTC1662
U
OPERATIO
The first of these, the Input Register, is used for loading new
input codes. The second buffer, the DAC Register, is used
for updating the DAC outputs. Each DAC has its own 10-bit
Input Register and 10-bit DAC Register.
Alternatively, one DAC may be loaded with a new input
code during Sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
By selecting the appropriate 4-bit Control code (see Table␣ 1)
it is possible to perform single operations, such as loading
one DAC or changing Power-Down status (Sleep/Wake).
In addition, some Control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part up.
The DACs can be loaded separately or together, but the
outputs are always updated together.
For example, control code 0001b is used to load DAC A
during Sleep. Then Control code 0101b loads DAC B,
wakes the part and simultaneously updates both DAC
outputs.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the SDI input
is shifted into the 16-bit Shift Register on the positive edge
of SCK. The 4-bit Control code, A3-A0, is loaded first, then
the 10-bit Input code, D9-D0, ordered MSB-to-LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last.
When the full 16-bit Input word has been shifted in, CS/LD
is pulled high, causing the system to respond according to
Table␣ 1. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110b is reserved for the special Sleep
instruction (see Table 1). In this mode, static power
consumption is greatly reduced. The reference input and
analog outputs are set in a high impedance state and all
DAC settings are retained in memory so that when Sleep
mode is exited, the outputs of DACs not updated by the
Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared with
new input codes during Sleep (control codes 0001b and
0010b); then, a single command (1000b) can be used both
to wake the part and to update the output values.
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in the
LTC1662 can typically source or sink at least 1mA
(VCC␣ =␣ 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 130Ω (typical) when driving a load
to the rails. The output amplifiers are stable driving
capacitive loads of up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. Please
see the Output Minimum Resistance vs Load Capacitance curve in the Typical Performance Characteristics
section.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE = VOS + GE) is positive, the output for the highest
codes limits at VCC as shown in Figure 2c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
9
LTC1662
U
OPERATIO
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(2c)
VREF = VCC
OUTPUT
VOLTAGE
0
512
INPUT CODE
1023
(2a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(2b)
1662 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
U
TYPICAL APPLICATIO S
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA
3.3V
0.1µF
R2
1.1M
0.1µF
3.3V
2
LTC1258-2.5
1
2.5V
4
SDI
SCK
3.3V
0.1µF
4 REF
6
VCC
DAC A
CS/LD
R1
11k
2
R1
COARSE
11k
8
VOUT A
8
–
LT1495
3
0.1µF
1
VOUT
+
4
1
3
LTC1662
U1
2
DAC B
5
R2
FINE
1.1M
VOUT B
(
(
VOUT = VREF CODE A + R1 • CODE B
R2
1024
1024
= 2.5V CODE A + 1 • CODE B
100 1024
1024
7 GND
1662 F04
10
)
)
LTC1662
U
TYPICAL APPLICATIO S
Using the LTC1258 and the LTC1662 In a Portable Application
Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA
Li-Ion BATTERY INPUT
VIN ≥ 4.3V
0.1µF
0.1µF
6
2
LTC1258-4.1
4
1
4.096V
4
3
2
1
VCC
VOUT A
REF
8
0V TO 4.096V
(4mV/BIT)
5
0V TO 4.096V
(4mV/BIT)
SDI
LTC1662
SCK
CS/LD
VOUT B
GND
7
1662 F03
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
0.034 ± 0.004
(0.86 ± 0.102)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7 6
5
0° – 6° TYP
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
BSC
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
MSOP (MS8) 1098
1
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
4
2 3
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.400*
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.100
(2.54)
BSC
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1098
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1662
U
TYPICAL APPLICATIO
Ultralow Power DAC Optimizes Mixer Performance
3.3V
0.1µF
0.1µF
3.3V
2
LTC1258-2.5
1
2.5V
4
I
LO
4 REF
6
IP
VCC
3.9k
0.1%
DAC A
CS/LD
SDI
SCK
8
3.9k
0.1%
560k
VOUT A
1
3.9k, 0.1%
3.9k
0.1%
I
3
LO
LTC1662
IP
I+Q
MIXER
Q
2
DAC B
5
RF
QP
3.9k
0.1%
560k
3.9k, 0.1%
VOUT B
3.9k
0.1%
3.9k
0.1%
Q
7 GND
Q
QP
1662 TA01
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1661
Dual 10-Bit VOUT DAC in 8-Lead MSOP Package
VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1663
Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package
VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1664
Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1665/LTC1660
Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC in SO-8 Package
VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC: 2.7V to 5.5V
Low Power Multiplying VOUT DAC. Output Swings from
GND to REF. REF Input Can Be Tied to VCC
12
Linear Technology Corporation
1662f LT/LCG 1000 4K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000
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