PRELIMINARY CY2DP818-2 1:8 Clock Fanout Buffer Features Description ■ Low voltage operation VDD = 3.3V This Cypress series of network circuits is produced using advanced 0.35 micron CMOS technology, achieving the industry’s fastest logic. ■ 1:8 fanout ■ Single-input configurable for LVDS, LVPECL, or LVTTL ■ 8 pairs of LVPECL outputs with enable and disable ■ Drives a 50 ohm load ■ Low input capacitance ■ Low output skew ■ Low propagation delay typical (tpd < 4 ns) ■ Industrial versions available ■ Package available include: TSSOP ■ Does not exceed Bellcore 802.3 standards ■ Operation up to 350 MHz and 700 Mbps The Cypress CY2DP818-2 fanout buffer features a single LVDS or a single-ended LVTTL compatible input and eight LVPECL output pairs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and for the distribution of LVPECL based clock signals. The Cypress CY2DP818-2 has configurable input functions. The input is user configurable through the Inconfig pin for single ended or differential input. Logic Block Diagram EN1 Q1A Q1B EN2 Q2A Q2B EN3 Q3A Q3B INPUT (LVPECL / LVDS / LVTTL) EN4 Q4A INPUT A INPUT B Q4B EN5 Q5A InConfig Q5B EN6 Q6A Q6B Q7A Q7B EN7 Q8A Q8B OUTPUT (LVPECL) Cypress Semiconductor Corporation Document #: 38-07588 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 22, 2008 [+] Feedback CY2DP818-2 PRELIMINARY Pin Configuration Figure 1. Pin Diagram - 38-Pin TSSOP VDD GND INPUT A INPUT B GND VDD EN5 EN6 EN7 VDD GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CY2DP818-2 GND VDD EN1 EN2 EN3 EN4 InConfig 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND Pin Description Pin Number Pin Name 1, 9,12,18,19,20,38 GND Pin Standard Interface Description POWER Ground. 2,8,13,29,17 VDD POWER Power supply. 3,4,5,6,14,15,16 EN(1:7) LVTTL/LVCMOS The respective outputs are enabled when these pins are pulled high. Outputs are disabled when connected to GND. EN7 controls both Q7(A,B) and Q8(A,B) 10,11 Input A, Input B Default: LVPECL/LDVS Optional: LVTTL/LVCMOS single pin Differential input pair or single line. LVPECL/LVDS default. See InConfig, below. 37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 Q1(A,B), Q2(A,B) Q3(A,B), Q4(A,B) Q5(A,B), Q6(A,B) Q7(A,B), Q8(A,B) LVPECL Differential outputs. 7 InConfig LVTTL/LVCMOS Converts inputs from the default LVPECL/LVDS (logic = 0) to LVTTL/LVCMOS (logic = 1) See Input Receiver Configuration for Differential or LVTTL/LVCMOS table, Figure 6 and Figure 7 for additional information Document #: 38-07588 Rev. *A Page 2 of 9 [+] Feedback CY2DP818-2 PRELIMINARY Power Supply Characteristics Parameter Description Test Conditions Min Typ Max Unit 1.5 2.0 mA/ MHz VDD = Max. Input toggling 50% Duty Cycle, Outputs 50 ohms, fL=100 MHz 350 mA VDD = Max. Input toggling 50% Duty Cycle, Outputs Disabled, not connected to VTT fL = 100 MHz 50 mA ICCD Dynamic Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current IC Core Core Current when Output Loads are Disabled Input Receiver Configuration for Differential or LVTTL/LVCMOS INCONFIG Pin 7 Binary Value Input Receiver Family Input Receiver Type 1 LVTTL in LVCMOS Single ended, non inverting, inverting, void of bias resistors 0 LVDS Low voltage differential signaling LVPECL Low voltage pseudo (positive) emitter coupled logic Function Control of the TTL Input Logic used to Accept or Invert the Input Signal LVTTL/LVCMOS Input Logic Input Condition Ground True Input Invert Input Invert Input True Input A (+) Pin 10 Input B (–) Pin 11 VDD Input Input B (–) Pin 11 Input A (+) Pin 10 Ground Output Logic Q Pins, Q1A or Q1 Input B (–) Pin 11 Input A (+) Pin 10 VDD Input Logic Input A (+) Pin 10 Input B (–) Pin 11 Document #: 38-07588 Rev. *A Page 3 of 9 [+] Feedback CY2DP818-2 PRELIMINARY Absolute Maximum Conditions Parameter Description VDD DC Supply Voltage Min Max Unit Inputs and VCC Condition –0.3 4.6 V VDD DC Operating Voltage Outputs –0.3 VDD + 0.3 V VIN DC Input Voltage Relative to VSS, with or VDD applied –0.3 VDD + 0.3 V VOUT DC Output Voltage Relative to VSS –0.3 VDD + 0.9 V VTT Output Termination Voltage – VDD ÷ 2 V TS Temperature, Storage –65 +150 °C TA Temperature, Operating Ambient 0 70 °C –40 +85 Non Functional Commercial Functional Industrial Functional Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. DC Electrical Specifications 3.3V – LVDS Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C Parameter Description Conditions Min VID Magnitude of Differential Input Voltage 100 VIC Common Mode of Differential Input VoltageIVIDI (minimum and maximum) IVIDI/2 IIH Input High Current VDD = Max. VIN = VDD IIL Input Low Current VDD = Max. VIN = VSS Typ Max Unit 600 mV 2.4–(IVIDI/2) V – ±10 ± 20 μA – ±10 ± 20 μA Min Typ Max Unit 3.3V – LVPECL Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C Parameter Description Conditions VID Differential Input Voltage p-p Guaranteed Logic High Level 400 – 2600 mV VIH Input High Voltage Guaranteed Logic High Level 2.15 – 2.4 V VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max. VIN = VDD IIL Input Low Current VDD = Max. VIN = VSS VCM Common-mode Voltage 1.5 – 1.8 V – ±10 ±20 μA – ±10 ±20 μA 1650 – 2250 mV Min Typ Max Units 3.3V – LVTTL/LVCMOS Input at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C Parameter Description Conditions VIH Input High Voltage Guaranteed Logic High Level 2 – – V VIL Input Low Voltage Guaranteed Logic Low Level – – 0.8 V IIH Input High Current VDD = Max VIN = 2.7V – – 1 μA IIL Input Low Current VDD = Max VIN = 0.5V – – –1 μA II Input High Current VDD = Max, VIN = VDD (Max) VIK Clamp Diode Voltage VDD = Min, IIN = –18 mA – –0.7 –1.2 V – 80 VH Input Hysteresis[1] mV Note 1. Guaranteed but not tested. Document #: 38-07588 Rev. *A Page 4 of 9 [+] Feedback CY2DP818-2 PRELIMINARY 3.3V – LVPECL Output at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C Parameter VOD Description Driver Differential Output Voltage p-p Conditions Min Typ Max Unit VDD = Min, VIN = VIH or VIL RL = 50 ohm 1000 – 3600 mV – – ΔVOC Driver common-Mode Variation p-p VDD = Min, VIN = VIH or VIL RL = 50 ohm Rise Time Differential 20% to 80% CL–10 pF RL and CL to GND RL = 50 ohm 300 VOH Output High Voltage 2.1 VOL Output Low Voltage VDD = Min, VIN = VIH or VIL IOH = –12 mA VDD = Min, VIN = VIH or VIL User-defined by VTT RTT. IOS Short Circuit Current VDD = Max, VOUT = GND Fall Time 300 mV 1200 ps – 3.0 V 0.8 – 1.3 V – – –150 mA Min Typ Max Unit 3 4 5 ns AC Switching Characteristics (at VDD = 3.3V ± 5%, TA = 0°C to 70°C or –40°C to 85°C) Parameter Description Conditions tPLH Propagation Delay – Low to High VOD = 100 mV tPHL Propagation Delay – High to Low 3 4 5 ns TPE Enable (EN) to Functional Operation – – 6 ns TPD Functional Operation to Disable – – 5 ns tSK(0) Output Skew: Skew between outputs of the same package (in phase) – – 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) – 0.2 tSK(t) Package Skew: Skew between outputs of different packages at the VID = 100 mV same power supply voltage, temperature, and package type. Same input signal level and output load. – – 1 ns Min Typ Max Unit – – 350 MHz ns High Frequency Parametrics Parameter Fmax Description Maximum Frequency VDD = 3.3V Conditions 45% to 55% duty cycle Standard load circuit Figure 2. Driver Design Document #: 38-07588 Rev. *A Page 5 of 9 [+] Feedback CY2DP818-2 PRELIMINARY Figure 3. Differential Receiver to Driver Propagation Delay and Driver Transition Time[2,3,4,5] A TPA 150 Pulse Generator B 150 50 10pF TPC VDD-2V 50 GND TPB Standard Termination INA INB 1.4 V 1.2 V CM 0V Differential 1.0 V QXA 1.4 V 1.2 V CM 0V Differential 1.0 V QXB T PLH T PHL 80% 0V Differential QXA - QXB 20% tR tF Figure 4. Test Circuit and Voltage Definitions for the Driver Common-Mode Output Voltage[2,3,4,5] A TPA 150 Pulse Generator 50 TPC B 150 50 GND TPB VOC Standard Termination VI(A) 2.0V VI(B) 1.6V VOD Next Device Notes 2. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns. 3. RL = 50 ohm ± 1%; Zline = 50 ohm 6”. 4. CL includes instrumentation and fixture capacitance within 6” of the DUT. 5. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2. Document #: 38-07588 Rev. *A Page 6 of 9 [+] Feedback CY2DP818-2 PRELIMINARY Figure 5. Test Circuit and Voltage Definitions for the Differential Output Signal[2,3,4,5] A TPA 150 Pulse Generator B 50 10pF TPC VDD-2V 50 GND 150 TPB Standard Termination VI(A) 1.4V VI(B) 1.0V 100% 80% 0.0V 20% 0% tF Figure 6. LVTTL/LVCMOS[6] tR Figure 7. LVDS/LVPECL[6] LVPECL & LVDS INPUT A LVCM OS / LVTTL INPUT B GND In C o n fig InConfig 0 1 L V D S /L V P E C L LVTTL/LVCMOS Ordering Information Part Number Package Type Product Flow CY2DP818ZI-2 38-Pin TSSOP Industrial, –40° to 85°C CY2DP818ZI-2T 38-Pin TSSOP–Tape and Reel Industrial, –40° to 85°C CY2DP818ZC-2 38-Pin TSSOP Commercial, 0°C to 70°C CY2DP818ZC-2T 38-Pin TSSOP–Tape and Reel Commercial, 0°C to 70°C 38-Pin TSSOP Industrial, –40° to 85°C Pb Free Devices CY2DP818ZXI-2 CY2DP818ZXI-2T 38-Pin TSSOP–Tape and Reel Industrial, –40° to 85°C CY2DP818ZXC-2 38-Pin TSSOP Commercial, 0°C to 70°C CY2DP818ZXC-2T 38-Pin TSSOP–Tape and Reel Commercial, 0°C to 70°C Note 6. LVPECL or LVDS differential input value. Document #: 38-07588 Rev. *A Page 7 of 9 [+] Feedback PRELIMINARY CY2DP818-2 Package Drawing and Dimensions Figure 8. 38-Pin TSSOP (4.40 mm Body) Z38 51-85151-*A Document #: 38-07588 Rev. *A Page 8 of 9 [+] Feedback PRELIMINARY CY2DP818-2 Document History Page Document Title: CY2DP818-2 1:8 Clock Fanout Buffer Document Number: 38-07588 Rev. ECN No. Submission Date Orig. of Change ** 129879 11/07/03 RGL *A 2595534 10/23/08 Description of Change New Data Sheet CXQ/PYRS Removed “Preliminary”, added Pb-free devices to Ordering Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07588 Rev. *A Revised October 22, 2008 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback