Infineon HYS72D32500GR-8-B Registered ddr sdram-module Datasheet

D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
HYS72D32500GR–[7F/7/8]–B
HYS72D64500GR–[7F/7/8]–B
HYS72D1285[20/21]GR–[7F/7]–B
HYS72D128521GR–8–B
Registered DDR SDRAM-Modules
D D R SD R A M
M e m or y P r o du c t s
N e v e r
s t o p
t h i n k i n g .
Edition 2004-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
Edition
2004-01 Germany
81669 München,
Published
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Life
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or to to
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orand/or
system.
Life support
support
devices ordevice
systems
intended
be implanted
human body,
or todevice
support
maintain
and
devices
or systems
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intended
implanted
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D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4
D ata
Sh ee t, Re v . 1 .0 3, J an . 2 00 4
H Y S 72 D 3 2 5 0 0 G R – [ 7 F / 7 / 8 ] – B
HYS72D64500GR–[7F/7/8]–B
HYS72D1285[20/21]GR–[7F/7]–B
HYS72D128521GR–8–B
Registered DDR SDRAM-Modules
D D R SD R A M
M
Pdu
r ocdt su c t s
M eemm
oroyr y
Pro
N e v e r
s t o p
t h i n k i n g .
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
HYS72D32500GR–[7F/7/8]–B, HYS72D64500GR–[7F/7/8]–B, HYS72D1285[20/21]GR–[7F/7]–B
Revision History:
Rev. 1.03
Previous Version:
V.092
2004-01
Page
Subjects (major changes since last revision)
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Data Sheet
4
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data Sheet
5
14
14
15
18
Rev. 1.03, 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Overview
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
184-Pin Registered 8-Byte Dual-In-Line
DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications
One rank 32M × 72, 64M × 72 and two ranks 128M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V (± 0.2 V) power
supply
Built with DDR SDRAMs in 66-Lead TSOPII package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL devices.
Serial Presence Detect with E2PROM
Low Profile Modules form factor:
133.35 mm × 30,48 mm (1.2”) × 4.00 mm
(6,80 mm with stacked components)
Based on JEDEC standard reference card layouts Raw Card L,M,N
Gold plated contacts
Table 1
Performance
Part Number Speed Code
–7F
–7
–8
Unit
Module Speed Grade
DDR266F
DDR266A
DDR200A
–
Component Module
PC2100
PC2100
PC1600
–
max. Clock
Frequency
1.2
@ CL = 2.5
fCK
143
143
125
MHz
@ CL = 2
fCK
133
133
100
MHz
Description
The HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B are low profile versions of the standard Registered DIMM
modules with 1.2” inch (30,48 mm) height for 1U Server Applications. The Low Profile DIMM versions are available
as 32M × 72 (256MB), 64M × 72 (512MB) and 128M × 72 (1 GB).
The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and
address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors
are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using
the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer.
Data Sheet
6
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Overview
Table 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM
Technology
PC2100 (CL = 2):
HYS72D32500GR-7F-B
PC2100R-20220-L
one rank 256 MB Registered DIMM
256 Mbit (x8)
HYS72D32500GR-7-B
PC2100R-20330-L
one rank 256 MB Registered DIMM
256 Mbit (x8)
HYS72D64500GR-7F-B
PC2100R-20220-M
one rank 512 MB Registered DIMM
256 Mbit (x4)
HYS72D64500GR-7-B
PC2100R-20330-M
one rank 512 MB Registered DIMM
256 Mbit (x4)
HYS72D128520GR-7F-B
PC2100R-20220-N
two ranks 1 GByte Registered DIMM
256 MBit (x4)
(stacked with
soldering process)
HYS72D128520GR-7-B
PC2100R-20330-N
two ranks 1 GByte Registered DIMM
256 MBit (x4)
(stacked with
soldering process)
HYS72D128521GR-7F-B
PC2100R-20220-N
two ranks 1 GByte Registered DIMM
256 MBit (x4)
(stacked with laser
welding process)
HYS72D128521GR-7-B
PC2100R-20330-N
two ranks 1 GByte Registered DIMM
256 MBit (x4)
(stacked with laser
welding process)
HYS72D32500GR-8-B
PC1600R-20220-L
one rank 256 MB Registered DIMM
256 Mbit (x8)
HYS72D64500GR-8-B
PC1600R-20220-M
one rank 512 MB Registered DIMM
256 Mbit (x4)
HYS72D128521GR-8-B
PC1600R-20220-M
two ranks 1GByte Registered DIMM
256Mbit (x4)
(stacked with laser
welding process)
PC1600 (CL = 2):
Note: All “product type” end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D32500GR-7-B, indicating rev. C dies are used for SDRAM components. The
“compliance code” is printed on the module labels describing the speed sort (for example “PC2100”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
2
Pin Configuration
Table 3
Pin Definitions and Functions
Symbol
Type
Function
A0 – A11, A12
Input
Address Inputs (A12 for 256 MB & 512 MB based modules)
BA0, BA1
Input
Bank Selects
DQ0 – DQ63
Input/Output
Data Input/Output
CB0 – CB7
Input/Output
Check Bits (×72 organization only)
RAS
Input
Row Address Strobe
CAS
Input
Column Address Strobe
WE
Input
Read/Write Input
CKE0, CKE1
Input
Clock Enable
DQS0 – DQS8
Input/Output
SDRAM low data strobes
CK0, CK0
Input
Differential Clock Input
DM0 – DM8
Input
SDRAM low data mask
DQS9 – DQS17
Input/Output
high data strobes
CS0, CS1
Input
Chip Selects
VDD
VSS
VDDQ
VDDID
VDDSPD
VREF
Supply
Power (+2.5 V)
Supply
Ground
Supply
I/O Driver power supply
Output
VDD Indentification flag
Supply
EEPROM power supply
Supply
I/O reference supply
SCL
Input
Serial bus clock
SDA
Output
Serial bus data line
SA0 – SA2
Input
slave address select
NC
Input
no connect
DU
Input
don’t use
RESET
Input
Reset pin (forces register inputs low) *)
*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the Application Note at the
end of this datasheet
Data Sheet
8
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
Table 4
Address Format
Organization
Memory
Ranks
SDRAMs
# of
SDRAMs
# of
row/rank/
columns
bits
Refresh Period Interval
256 MB
32M x 72
1
256Mbit
32M × 8
9
13 / 2 / 10
8K
64 ms
7.8 µs
512 MB
64M × 72
1
256Mbit
64M × 4
18
13 / 2 / 11
8K
64 ms
7.8 µs
1 GB
128M × 72
2
256Mbit
64M × 4
36 (stacked)
13 / 2 / 11
8K
64 ms
7.8 µs
Table 5
Pin Configuration
Density
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
94
DQ4
141
A10
2
DQ0
49
CB2
95
DQ5
142
CB6
3
VSS
50
VSS
96
VDDQ
143
VDDQ
4
DQ1
51
CB3
97
DM0/DQS9
144
CB7
5
DQ0
52
BA1
98
DQ6
6
DQ2
99
DQ7
145
VSS
7
VDD
53
DQ32
100
VSS
146
DQ36
8
DQ3
54
VDDQ
101
NC
147
DQ37
9
NC
55
DQ33
102
NC
148
VDD
10
RESET
56
DQS4
103
NC
149
DM4/DQS13
11
VSS
57
DQ34
104
VDDQ
150
DQ38
12
DQ8
58
VSS
105
DQ12
151
DQ39
13
DQ9
59
BA0
106
DQ13
152
VSS
14
DQS1
60
DQ35
107
DM1/DQS10
153
DQ44
15
VDDQ
61
DQ40
108
VDD
154
RAS
16
DU
62
VDDQ
109
DQ14
155
DQ45
17
DU
63
WE
110
DQ15
156
VDDQ
18
VSS
64
DQ41
111
CKE1
157
CS0
19
DQ10
65
CAS
112
VDDQ
158
CS1
20
DQ11
66
VSS
113
NC
159
DM5/DQS14
21
CKE0
67
DQS5
114
DQ20
160
VSS
22
VDDQ
68
DQ42
115
NC / A12
161
DQ46
23
DQ16
69
DQ43
116
VSS
162
DQ47
24
DQ17
70
VDD
117
DQ21
163
NC
25
DQS2
71
NC
118
A11
164
VDDQ
KEY
KEY
26
VSS
72
DQ48
119
DM2/DQS11
165
DQ52
27
A9
73
DQ49
120
VDD
166
DQ53
28
DQ18
74
VSS
121
DQ22
167
NC
29
A7
75
DU
122
A8
168
VDD
30
VDDQ
76
DU
123
DQ23
169
DM6/DQS15
Data Sheet
9
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
Table 5
PIN#
Pin Configuration (cont’d)
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
31
DQ19
77
VDDQ
124
VSS
170
DQ54
32
A5
78
DQS6
125
A6
171
DQ55
33
DQ24
79
DQ50
126
DQ28
172
VDDQ
34
VSS
80
DQ51
127
DQ29
173
NC
35
DQ25
81
VDDQ
174
DQ60
DQS3
82
VSS
VDDID
128
36
129
DM3/DQS12
175
DQ61
37
A4
83
DQ56
130
A3
176
VSS
38
VDD
84
DQ57
131
DQ30
177
DM7/DQS16
39
DQ26
85
VDD
132
VSS
178
DQ62
40
DQ27
86
DQS7
133
DQ31
179
DQ63
41
A2
87
DQ58
134
CB4
180
VDDQ
42
VSS
88
DQ59
135
CB5
181
SA0
43
A1
89
VSS
136
VDDQ
182
SA1
44
CB0
90
NC
137
CK0
183
SA2
45
CB1
91
SDA
138
CK0
184
VDDSPD
46
VDD
92
SCL
139
VSS
–
–
47
DQS8
93
VSS
140
DM8/DQS17
–
–
Note: A12 is used for 256Mbit and 512Mbit based modules only
Data Sheet
10
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
D0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D1
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DQS
D3
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
R
E
G
I
S
T
E
R
CKE0
WE
PCK
PCK
Figure 1
Data Sheet
S
DQS
D5
S
DQS
D6
DQS7
DM7/DQS16
DQS3
DM3/DQS12
RAS
CAS
D4
DQS6
DM6/DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
BA0-BA1
A0-An7
DQS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
S0
S
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
Serial PD
DQS
SCL
D8
SDA
WP A0
A1
A2
DQS
D7
VDDSPD
Serial PD
VDDQ
D0- D8
VDD
D0-D8
D0-D8
VREF
VSS
SA0 SA1 SA2
VDDID
D0-D8
Strap: see Note 4
Notes:
RS0 -> CS: SDRAMs D0-D8
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
RA0-RAn7 -> A0-An7: SDRAMs D0-D8
RRAS -> RAS: SDRAMs D0-D8
RCAS -> CAS: SDRAMs D0-D8
RCKE0 -> CKE: SDRAMs D0- D8
RWE -> WE: SDRAMs D0-D8
CK0, CK0 --------- PLL*
RESET
S
* Wire per Clock Loading Table/Wiring Diagrams
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD,
VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. SDRAM placement alternates between the back
and front sides of the DIMM.
6. Address and control resistors should be 22 Ohms.
7. A13 is not wired for raw card A.
Block Diagram: One Rank 32M × 72 DDR SDRAM DIMM Module (×8 components)
HYS72D32500GR on Raw Card L
11
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
VSS
RS0
DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D0
D1
DQS
S
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
DQ20
DQ21
DQ22
DQ23
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
DM
D10
DQS11
DM
D2
DQS3
S
DM
D11
DQS12
S
DM
D3
DQS4
DQS13
S
D4
S
DM
DQS6
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
DQS14
D5
S
DQS
DM
DQS5
DQS
D6
S
DM
D12
S
DM
D13
S
DM
VDDSPD
Serial PD
VDDQ
D0-D17
VDD
D0-D17
VREF
D0-D17
VSS
D0-D17
VDDID
Strap: see Note 4
D14
Serial PD
DQS15
DQ52
DQ53
DQ54
DQ55
DQS S
I/O 0
I/O 1
D15
I/O 2
I/O 3
DQ60
DQ61
DQ62
DQ63
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DQS7
DM
SCL
SDA
WP A0
A1
A2
SA0 SA1 SA2
DQS16
DQ56
DQ57
DQ58
DQ59
CB0
CB1
CB2
CB3
R
E
G
I
S
T
E
R
S0
BA0-BA1
A0-An6
RAS
CAS
CKE0
WE
PCK
PCK
Data Sheet
D9
DM
DQS2
Figure 2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS10
DQS1
DQS8
DQ4
DQ5
DQ6
DQ7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D7
D8
DM
DQS17
S
DM
D16
S
D17
DM
Notes:
1. DQ-to-I/O wiring may be changed
within a byte.
2. DQ/DQS/CKE/S relationships
must be maintained as shown.
3. DQ/DQS resistors should be 22
Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. Address and control resistors
should be 22 Ohms.
6. A13 is not wired for raw card B.
RS0 -> CS : SDRAMs D0-D17
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17
RA0-RAn6 -> A0-An6: SDRAMs D0-D17
RRAS -> RAS: SDRAMs D0-D17
RCAS -> CAS: SDRAMs D0-D17
RCKE0A -> CKE: SDRAMs D0-D17
CK0, CK0 --------- PLL*
RWE -> WE: SDRAMs D0-D17
* Wire per Clock Loading Table/Wiring Diagrams
RESET
Block Diagram: One Rank 64M × 72 DDR SDRAM DIMM Module (×4 components)
HYS72D64500GR on Raw Card M
12
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Pin Configuration
VSS
RS1
RS0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ8
DQ9
DQ10
DQ11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ16
DQ17
DQ18
DQ19
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ32
DQ33
DQ34
DQ35
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ40
DQ41
DQ42
DQ43
S
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ56
DQ57
DQ58
DQ59
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
CB0
CB1
CB2
CB3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D0
DQS
I/O 3
I/O 2
I/O 1
I/O 0
S
DM
D18
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
DM
D9
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D27
DM1/DQS10
DQS1
DM
D1
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
DQ12
DQ13
DQ14
DQ15
D19
DQS2
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D10
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D28
DM2/DQS11
DQS3
DM
D2
DM
DQ20
DQ21
DQ22
DQ23
D20
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D11
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D29
DM3/DQS12
S
DM
D3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
DQ28
DQ29
DQ30
DQ31
D21
DQS4
DM4/DQS13
DM
D4
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQ36
DQ37
DQ38
DQ39
DQS5
DM
D5
DM5/DQS14
DM
DQS6
DM
I/O 0
I/O 1
I/O 2
I/O 3
D6
S
DM6/DQS15
DM
DQ52
DQ53
DQ54
DQ55
DQS7
D7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
DQ60
DQ61
DQ62
DQ63
D25
D8
DM
WE
PCK
PCK
Figure 3
Data Sheet
DM
D13
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D14
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
D15
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D16
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
D30
S
DM
D31
S
DM
D32
S
DM
D33
S
DM
D34
DM8/DQS17
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
D26
CK0, CK0 --------- PLL*
* Wire per Clock Loading Table/Wiring Diagrams
R
E
G
I
S
T
E
R
S
I/O 0
I/O 1
I/O 2
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM7/DQS16
DM
DQS8
S0
S1
BA0-BA1
A0-A13
RAS
CAS
CKE0
CKE1
DM
D12
DQS
DQ44
DQ45
DQ46
DQ47
D23
S
DQS
DM
D22
DQS
I/O 0
I/O 1
I/O 2
I/O 3
SCL
RESET
WP A0
A1
D17
VDDSPD
Serial PD
RSO -> S : SDRAMs D0-D17
RS1 -> S : SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35
RA0-RA13 -> A0-A13: SDRAMs D0- D35
RRAS -> RAS: SDRAMs D0-D35
RCAS -> CAS: SDRAMs D0-D35
RCKE0 -> CKE: SDRAMs D0-D17
RCKE1 -> CKE: SDRAMs D18-D35
RWE -> WE: SDRAMs D0-D35
S
A2
SA0 SA1 SA2
VDDQ
SDA VDD
VREF
VSS
VDDID
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
S
DM
D35
Serial PD
D0-D35
D0-D35
D0-D35
D0-D35
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. Address and control resistors should be 22 Ohms.
6. Each Chip Select and CKE pair alternate between decks for thermal enhancement.
Block Diagram: Two Ranks 128M × 72 DDR SDRAM DIMM Modules (×4 components)
HYS72D128520GR on Raw Card N
13
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 6
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
min.
max.
–0.5
3.6
V
–0.5
3.6
V
Storage temperature range
VIN, VOUT
VDD, VDDQ
TSTG
–55
+150
o
Power dissipation (per SDRAM component)
PD
–
1
W
Data out current (short circuit)
IOS
–
50
mA
Input/Output voltage relative to VSS
Power supply voltage on VDD/VDDQ to VSS
C
Attention: Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional
operation should be restricted to recommended operation conditions. Exposure to higher than
recommended voltage for extended periods of time affect device reliability
Table 7
Supply Voltage Levels
Parameter
Symbol
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
Termination Voltage
EEPROM supply voltage
Values
VDD
VDDQ
VREF
VTT
VDDSPD
Unit/
Notes
min.
nom.
max.
2.3
2.5
2.7
V
2.3
2.5
2.7
V 1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V 2)
VREF – 0.04
VREF
VREF + 0.04
V 3)
2.3
2.5
3.6
V
Note:
1. Under all conditions, VDDQ must be less than or equal to VDD
2. Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).
VREF is also expected to track noise variations in VDDQ.
3. VTT of the transmitting device must track VREF of the receiving device
.
Table 8
DC Operating Conditions (SSTL_2 Inputs)
(VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS)
Parameter
Symbol
Values
min.
VREF +0.15
Input Leakage Current
VIH, (DC)
VIL, (DC)
IIL
Output Leakage Current
IOL
DC Input Logic High
DC Input Logic Low
max.
Unit/
Notes
V 1)
–0.30
VDDQ +0.3
VREF –0.15
–5
5
µA 1)
–5
5
µA 2)
V
Note:
1. The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines
noise margins. However, in the case of VIH (max.) (input overdrive), it is the VDDQ of the receiving device that is
referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2
outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input
overdrive to 3.0 V (High corner VDDQ + 300 mV).
2. For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component
Data Sheet
14
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
3.2
Current Specification and Conditions
Table 9
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Data Sheet
15
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
HYS72D128521GR–7–B
HYS72D128520GR–7–B
HYS72D64500GR–7–B
HYS72D32500GR–7–B
HYS72D128520GR–7F–B
HYS72D128521GR–7F–B
HYS72D32500GR–7F–B
Product Type & Organisation
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
HYS72D64500GR–7F–B
IDD Specifications –7F/–7
Table 10
Unit
Note/ Test
Conditions5)
256 MB 512 MB 1 GByte 1 GByte 256 MB 512 MB 1 GByte 1 GByte
×72
×72
×72
×72
×72
×72
×72
×72
1 Rank 1 Rank
2 Ranks 2 Ranks 1 Rank
1 Rank
2 Ranks 2 Ranks
–7F
–7F
–7F
–7F
–7
–7
–7
–7
max.
max.
max.
max.
max.
max.
max.
max.
990
1980
2970
2970
900
1800
2790
2790
mA
1)4)
1080
2160
3150
3150
990
1980
2970
2970
mA
1)3)4)
72
144
288
288
72
144
288
288
mA
2)4)
360
720
1440
1440
360
720
1440
1440
mA
2)4)
225
450
900
900
225
450
900
900
mA
2)4)
162
324
648
648
162
324
648
648
mA
2)4)
495
990
1980
1980
495
990
1980
1980
mA
2)4)
1035
2070
3060
3060
1035
2070
3060
3060
mA
1)3)4)
1125
2250
3240
3240
1125
2250
3240
3240
mA
1)4)
1620
3240
4230
4230
1620
3240
4230
4230
mA
1)4)
23
45
90
90
23
45
90
90
mA
2)4)
2025
4050
5040
5040
2025
4050
5040
5040
mA
1)3)4)5)
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) DRAM component currents only: module
currents
IDD will be measured differently depending upon register and PLL operation
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
16
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
Note/ Test
Conditions5)
HYS72D128521GR–8–B
Unit
HYS72D64500GR–8–B
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
IDD Specifications –8
HYS72D32500GR–8–B
Product Type & Organisation
Table 11
256 MB
512 MB
1 GByte
×72
×72
×72
1 Rank
1 Rank
2 Ranks
–8
–8
–8
max.
max.
max.
810
1620
2430
mA
1)4)
900
1800
2610
mA
1)3)4)
63
126
252
mA
2)4)
315
630
1260
mA
2)4)
198
396
792
mA
2)4)
144
288
576
mA
2)4)
405
810
1620
mA
2)4)
855
1710
2520
mA
1)3)4)
945
1890
2700
mA
1)4)
1530
3060
3870
mA
1)4)
22,5
45
90
mA
2)4)
1890
3780
4590
mA
1)3)4)5)
1) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
n * IDD×[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)
2) The module IDD values are calculated from the component IDD datasheet values are:
n * IDD×[component] for single bank modules (n: number of components per module bank)
2 * n * IDD×[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
4) DRAM component currents only: module
currents
IDD will be measured differently depending upon register and PLL operation
5) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
Data Sheet
17
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
3.3
AC Characteristics
Table 12
AC Timing - Absolute Specifications –8/–7/-7F
Parameter
Symbol
–8
–7
–7F
DDR200
DDR266A
DDR266F
Min. Max.
Min.
Max.
Min. Max.
Unit Note/
Test
Condition 1)
DQ output access time from
CK/CK
tAC
–0.8 +0.8
–0.75 +0.75
–
+0.75
0.75
ns
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.8 +0.8
–0.75 +0.75
–
+0.75
0.75
ns
2)3)4)5)
CK high-level width
tCH
tCL
tHP
tCK2.5
tCK2
tDH
tDS
tIPW
0.45 0.55
0.45
0.55
0.45 0.55
2)3)4)5)
0.45 0.55
0.45
0.55
0.45 0.55
tCK
tCK
DQ and DM input pulse width
(each input)
CK low-level width
Clock Half Period
min. (tCL, tCH)
min. (tCL, tCH)
2)3)4)5)
2)3)4)5)
min. (tCL, tCH) ns
8
12
7
12
7
12
ns
CL = 2.5 2)3)4)5)
10
12
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
0.6
—
0.5
—
0.5
—
ns
2)3)4)5)
0.6
—
0.5
—
0.5
—
ns
2)3)4)5)
2.5
—
2.2
—
2.2
—
ns
2)3)4)5)6)
tDIPW
2.0
—
1.75
—
1.75 —
ns
2)3)4)5)6)
Data-out high-impedance time
from CK/CK
tHZ
–0.8 +0.8
–0.75 +0.75
–
+0.75
0.75
ns
2)3)4)5)7)
Data-out low-impedance time
from CK/CK
tLZ
–0.8 +0.8
–0.75 +0.75
–
+0.75
0.75
ns
2)3)4)5)7)
Write command to 1st DQS
latching transition
tDQSS
0.75 1.25
0.75
1.25
0.75 1.25
tCK
2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
—
—
+0.5
—
ns
2)3)4)5)
Data hold skew factor
tQHS
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse
width (each input)
+0.6
+0.5
ns
—
1.0
—
0.75
—
0.75
2)3)4)5)
ns
ns
DQ/DQS output hold time
tQH
tHP – —
tQHS
tHP –
tQHS
—
tHP – —
tQHS
ns
2)3)4)5)
DQS input low (high) pulse
width (write cycle)
tDQSL,H
0.35 —
0.35
—
0.35 —
tCK
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge hold time from tDSH
CK (write cycle)
0.2
—
0.2
—
0.2
—
tCK
2)3)4)5)
Mode register set command
cycle time
tMRD
2
—
2
—
2
—
tCK
2)3)4)5)
Write preamble setup time
tWPRES
tWPST
tWPRE
0
—
0
—
0
—
ns
2)3)4)5)8)
0.40 0.60
0.40
0.60
0.40 0.60
2)3)4)5)9)
0.25 —
0.25
—
0.25 —
tCK
tCK
Write postamble
Write preamble
Data Sheet
18
2)3)4)5)
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
Table 12
AC Timing - Absolute Specifications –8/–7/-7F
Parameter
Symbol
Address and control input setup tIS
time
–8
–7
–7F
DDR200
DDR266A
DDR266F
Min. Max.
Min.
Max.
Min. Max.
1.1
0.9
—
0.9
—
—
Unit Note/
Test
Condition 1)
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input hold
time
tIH
1.1
—
0.9
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read preamble setup time
Read postamble
tRPRE
tRPRES
tRPST
tRAS
tRC
0.9
1.1
0.9
1.5
—
NA
0.40 0.60
0.40
1.1
0.60
0.9
1.1
NA
—
0.40 0.60
tCK
tCK
CL > 1.5 2)3)4)5)
ns
2)3)4)5)
2)3)4)5)11)
50
120E+3 45
120E+3 45
120E+3 tCK
2)3)4)5)
70
—
65
—
65
—
ns
2)3)4)5)
tRFC
80
—
75
—
75
—
ns
2)3)4)5)
tRCD
Precharge command period
tRP
Active to Autoprecharge delay tRAP
Active bank A to Active bank B tRRD
20
—
20
—
20
—
ns
2)3)4)5)
20
—
20
—
20
—
ns
2)3)4)5)
20
—
20
—
20
—
ns
2)3)4)5)
15
—
15
—
15
—
ns
2)3)4)5)
15
—
15
—
15
—
ns
2)3)4)5)
tCK
2)3)4)5)12)
Active to Precharge command
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Autorefresh command period
Active to Read or Write delay
command
tWR
Auto precharge write recovery + tDAL
Write recovery time
(twr/tCK) + (trp/tCK)
precharge time
Internal write to read command tWTR
delay
1
—
1
—
1
—
tCK
CL > 1.5 2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
80
—
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read
command
tXSRD
200
—
200
—
200
—
tCK
2)3)4)5)
Average Periodic Refresh
Interval
tREFI
—
7.8
—
7.8
—
7.8
µs
2)3)4)5)13)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266a, DDR266F and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Data Sheet
19
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Electrical Characteristics
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes
were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in
progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac).
11) tRPRES is defined for CL = 1.5 operation only
12) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
13) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Codes for HYS72D32500GR–[7F/7/8]-B
HYS72D32500GR–7F–B
Table 13
HYS72D32500GR–7–B
SPD Contents
Product Type & Organization
4
HYS72D32500GR–8–B
SPD Contents
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC1600R –
20220
PC2100R –
20330
PC2100R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
Byte#
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0A
0A
0A
5
Number of DIMM Ranks
01
01
01
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
80
70
70
10
tAC SDRAM @ CLmax (Byte 18) [ns]
80
75
75
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
08
08
08
14
Error Checking SDRAM Width
08
08
08
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
0C
0C
0C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C0
C0
C0
23
tCK @ CLmax -0.5 (Byte 18) [ns]
A0
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
80
75
75
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
Data Sheet
21
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D32500GR–7F–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC1600R –
20220
PC2100R –
20330
PC2100R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
27
tRPmin [ns]
50
50
3C
28
tRRDmin [ns]
3C
3C
3C
29
tRCDmin [ns]
50
50
3C
30
tRASmin [ns]
32
2D
2D
31
Module Density per Rank
40
40
40
32
tAS, tCS [ns]
B0
90
90
33
tAH, TCH [ns]
B0
90
90
34
tDS [ns]
60
50
50
35
tDH [ns]
60
50
50
36-40
not used
00
00
00
41
tRCmin [ns]
46
41
3C
42
tRFCmin [ns]
50
4B
4B
43
tCKmax [ns]
30
30
30
44
tDQSQmax [ns]
3C
32
32
45
tQHSmax [ns]
A0
75
75
46
not used
00
00
00
47
DIMM PCB Height
00
00
00
48-61
not used
00
00
00
62
SPD Revision
00
00
00
63
Checksum of Byte 0-62
BF
CA
9D
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65
JEDEC ID Code of Infineon (2)
49
49
49
66
JEDEC ID Code of Infineon (3)
4E
4E
4E
67
JEDEC ID Code of Infineon (4)
46
46
46
68
JEDEC ID Code of Infineon (5)
49
49
49
69
JEDEC ID Code of Infineon (6)
4E
4E
4E
Product Type & Organization
HYS72D32500GR–7–B
SPD Codes for HYS72D32500GR–[7F/7/8]-B
HYS72D32500GR–8–B
Table 13
Byte#
Data Sheet
22
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D32500GR–7F–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC1600R –
20220
PC2100R –
20330
PC2100R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
70
JEDEC ID Code of Infineon (7)
45
45
45
71
JEDEC ID Code of Infineon (8)
4F
4F
4F
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
33
33
33
77
Part Number, Char 5
32
32
32
78
Part Number, Char 6
35
35
35
79
Part Number, Char 7
30
30
30
80
Part Number, Char 8
30
30
30
81
Part Number, Char 9
47
47
47
82
Part Number, Char 10
52
52
52
83
Part Number, Char 11
38
37
37
84
Part Number, Char 12
42
42
46
85
Part Number, Char 13
20
20
42
86
Part Number, Char 14
20
20
20
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
xx
xx
xx
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
Product Type & Organization
HYS72D32500GR–7–B
SPD Codes for HYS72D32500GR–[7F/7/8]-B
HYS72D32500GR–8–B
Table 13
Byte#
Data Sheet
23
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D32500GR–7F–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC1600R –
20220
PC2100R –
20330
PC2100R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
99-127
not used
00
00
00
Product Type & Organization
HYS72D32500GR–7–B
SPD Codes for HYS72D32500GR–[7F/7/8]-B
HYS72D32500GR–8–B
Table 13
Byte#
HYS72D64500GR–8–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC2100R –
20220
PC2100R –
20330
PC1600R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
80
1
Total number of Bytes in E2PROM
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
3
Number of Row Addresses
0D
0D
0D
4
Number of Column Addresses
0B
0B
0B
5
Number of DIMM Ranks
01
01
01
Product Type & Organization
HYS72D64500GR–7–B
SPD Codes for HYS72D64500GR–[7F/7/8]–B
HYS72D64500GR–7F–B
Table 14
Byte#
Data Sheet
24
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D64500GR–8–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC2100R –
20220
PC2100R –
20330
PC1600R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
6
Data Width (LSB)
48
48
48
7
Data Width (MSB)
00
00
00
8
Interface Voltage Levels
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
70
70
80
Product Type & Organization
HYS72D64500GR–7–B
SPD Codes for HYS72D64500GR–[7F/7/8]–B
HYS72D64500GR–7F–B
Table 14
Byte#
10
tAC SDRAM @ CLmax (Byte 18) [ns]
75
75
80
11
Error Correction Support
02
02
02
12
Refresh Rate
82
82
82
13
Primary SDRAM Width
04
04
04
14
Error Checking SDRAM Width
04
04
04
15
tCCD [cycles]
01
01
01
16
Burst Length Supported
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
18
CAS Latency
0C
0C
0C
19
CS Latency
01
01
01
20
Write Latency
02
02
02
21
DIMM Attributes
26
26
26
22
Component Attributes
C0
C0
C0
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
A0
24
tAC SDRAM @ CLmax -0.5 [ns]
75
75
80
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
27
tRPmin [ns]
3C
50
50
28
tRRDmin [ns]
3C
3C
3C
29
tRCDmin [ns]
3C
50
50
30
tRASmin [ns]
2D
2D
32
31
Module Density per Rank
80
80
80
32
tAS, tCS [ns]
90
90
B0
Data Sheet
25
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D64500GR–8–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC2100R –
20220
PC2100R –
20330
PC1600R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
33
tAH, TCH [ns]
90
90
B0
34
tDS [ns]
50
50
60
35
tDH [ns]
50
50
60
36-40
not used
00
00
00
Product Type & Organization
HYS72D64500GR–7–B
SPD Codes for HYS72D64500GR–[7F/7/8]–B
HYS72D64500GR–7F–B
Table 14
Byte#
41
tRCmin [ns]
3C
41
46
42
tRFCmin [ns]
4B
4B
50
43
tCKmax [ns]
30
30
30
44
tDQSQmax [ns]
32
32
3C
45
tQHSmax [ns]
75
75
A0
46
not used
00
00
00
47
DIMM PCB Height
00
00
00
48-61
not used
00
00
00
62
SPD Revision
00
00
00
63
Checksum of Byte 0-62
D6
03
F8
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
65
JEDEC ID Code of Infineon (2)
49
49
49
66
JEDEC ID Code of Infineon (3)
4E
4E
4E
67
JEDEC ID Code of Infineon (4)
46
46
46
68
JEDEC ID Code of Infineon (5)
49
49
49
69
JEDEC ID Code of Infineon (6)
4E
4E
4E
70
JEDEC ID Code of Infineon (7)
45
45
45
71
JEDEC ID Code of Infineon (8)
4F
4F
4F
72
Module Manufacturer Location
xx
xx
xx
73
Part Number, Char 1
37
37
37
74
Part Number, Char 2
32
32
32
75
Part Number, Char 3
44
44
44
76
Part Number, Char 4
36
36
36
Data Sheet
26
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D64500GR–8–B
×72
×72
×72
1 rank
1 rank
1 rank
reg
reg
reg
Label Code
PC2100R –
20220
PC2100R –
20330
PC1600R –
20220
Jedec SPD Revision
Rev. 0.0
Rev. 0.0
Rev. 0.0
Description
HEX
HEX
HEX
77
Part Number, Char 5
34
34
34
78
Part Number, Char 6
35
35
35
79
Part Number, Char 7
30
30
30
80
Part Number, Char 8
30
30
30
81
Part Number, Char 9
47
47
47
82
Part Number, Char 10
52
52
52
83
Part Number, Char 11
37
37
38
84
Part Number, Char 12
46
42
42
85
Part Number, Char 13
42
20
20
86
Part Number, Char 14
20
20
20
87
Part Number, Char 15
20
20
20
88
Part Number, Char 16
20
20
20
89
Part Number, Char 17
20
20
20
90
Part Number, Char 18
20
20
20
91
Module Revision Code
xx
xx
xx
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
99-127
not used
00
00
00
Product Type & Organization
HYS72D64500GR–7–B
SPD Codes for HYS72D64500GR–[7F/7/8]–B
HYS72D64500GR–7F–B
Table 14
Byte#
Data Sheet
27
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D128520GR–7F–B
HYS72D128521GR–8–B
HYS72D128521GR–7–B
HYS72D128521GR–7F–B
Label Code
HYS72D128520GR–7–B
SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8
Part Number & Organization
Table 15
×72
×72
×72
×72
×72
2 Ranks
2 Ranks
2 Ranks
2 Ranks
2 Ranks
reg
reg
reg
reg
reg
PC2100R20330-N
PC2100R20220-N
PC1600R20220-N
PC2100R20330-N
PC2100R20220-N
HEX
HEX
HEX
HEX
HEX
80
80
80
80
80
Jedec SPD Revision
Byte# Description
0
Programmed SPD Bytes in E2PROM
1
Total number of Bytes in E2PROM
08
08
08
08
08
2
Memory Type (DDR = 07h)
07
07
07
07
07
3
Number of Row Addresses
0D
0D
0D
0D
0D
4
Number of Column Addresses
0B
0B
0B
0B
0B
5
Number of DIMM Ranks
02
02
02
02
02
6
Data Width (LSB)
48
48
48
48
48
7
Data Width (MSB)
00
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
70
70
80
70
70
10
tAC SDRAM @ CLmax (Byte 18) [ns]
75
75
80
75
75
11
Error Correction Support
02
02
02
02
02
12
Refresh Rate
82
82
82
82
82
13
Primary SDRAM Width
04
04
04
04
04
14
Error Checking SDRAM Width
04
04
04
04
04
15
tCCD [cycles]
01
01
01
01
01
16
Burst Length Supported
0E
0E
0E
0E
0E
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
CAS Latency
0C
0C
0C
0C
0C
19
CS Latency
01
01
01
01
01
20
Write Latency
02
02
02
02
02
21
DIMM Attributes
26
26
26
26
26
22
Component Attributes
C0
C0
C0
C0
C0
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
A0
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
75
75
80
75
75
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
00
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
00
00
00
Data Sheet
28
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D128520GR–7F–B
HYS72D128521GR–8–B
HYS72D128521GR–7–B
HYS72D128521GR–7F–B
Label Code
HYS72D128520GR–7–B
SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8
Part Number & Organization
Table 15
×72
×72
×72
×72
×72
2 Ranks
2 Ranks
2 Ranks
2 Ranks
2 Ranks
reg
reg
reg
reg
reg
PC2100R20330-N
PC2100R20220-N
PC1600R20220-N
PC2100R20330-N
PC2100R20220-N
HEX
HEX
HEX
HEX
HEX
Jedec SPD Revision
Byte# Description
27
tRPmin [ns]
50
3C
50
50
3C
28
tRRDmin [ns]
3C
3C
3C
3C
3C
29
tRCDmin [ns]
50
3C
50
50
3C
30
tRASmin [ns]
2D
2D
32
2D
2D
31
Module Density per Rank
80
80
80
80
80
32
tAS, tCS [ns]
90
90
B0
90
90
33
tAH, TCH [ns]
90
90
B0
90
90
34
tDS [ns]
50
50
60
50
50
35
tDH [ns]
50
50
60
50
50
36
not used
00
00
00
00
00
37
not used
00
00
00
00
00
38
not used
00
00
00
00
00
39
not used
00
00
00
00
00
40
not used
00
00
00
00
00
41
tRCmin [ns]
41
3C
46
41
3C
42
tRFCmin [ns]
4B
4B
50
4B
4B
43
tCKmax [ns]
30
30
30
30
30
44
tDQSQmax [ns]
32
32
3C
32
32
45
tQHSmax [ns]
75
75
A0
75
75
46
not used
00
00
00
00
00
47
DIMM PCB Height
00
00
00
00
00
48-61 not used
00
00
00
00
00
62
SPD Revision
00
00
00
00
00
63
Checksum of Byte 0-62
04
D7
F9
04
D7
64
JEDEC ID Code of Infineon (1)
C1
C1
C1
C1
C1
65
JEDEC ID Code of Infineon (2)
49
49
49
49
49
66
JEDEC ID Code of Infineon (3)
4E
4E
4E
4E
4E
Data Sheet
29
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D128520GR–7F–B
HYS72D128521GR–8–B
HYS72D128521GR–7–B
HYS72D128521GR–7F–B
Label Code
HYS72D128520GR–7–B
SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8
Part Number & Organization
Table 15
×72
×72
×72
×72
×72
2 Ranks
2 Ranks
2 Ranks
2 Ranks
2 Ranks
reg
reg
reg
reg
reg
PC2100R20330-N
PC2100R20220-N
PC1600R20220-N
PC2100R20330-N
PC2100R20220-N
HEX
HEX
HEX
HEX
HEX
Jedec SPD Revision
Byte# Description
67
JEDEC ID Code of Infineon (4)
46
46
46
46
46
68
JEDEC ID Code of Infineon (5)
49
49
49
49
49
69
JEDEC ID Code of Infineon (6)
4E
4E
4E
4E
4E
70
JEDEC ID Code of Infineon (7)
45
45
45
45
45
71
JEDEC ID Code of Infineon (8)
4F
4F
4F
4F
4F
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Part Number, Char 1
37
37
37
37
37
74
Part Number, Char 2
32
32
32
32
32
75
Part Number, Char 3
44
44
44
44
44
76
Part Number, Char 4
31
31
31
31
31
77
Part Number, Char 5
32
32
32
32
32
78
Part Number, Char 6
38
38
38
38
38
79
Part Number, Char 7
35
35
35
35
35
80
Part Number, Char 8
32
32
32
32
32
81
Part Number, Char 9
30
31
31
31
31
82
Part Number, Char 10
47
47
47
47
47
83
Part Number, Char 11
52
52
52
52
52
84
Part Number, Char 12
37
37
38
37
37
85
Part Number, Char 13
42
46
42
42
46
86
Part Number, Char 14
20
42
20
20
42
87
Part Number, Char 15
20
20
20
20
20
88
Part Number, Char 16
20
20
20
20
20
89
Part Number, Char 17
20
20
20
20
20
90
Part Number, Char 18
20
20
20
20
20
91
Module Revision Code
xx
xx
xx
xx
xx
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
Data Sheet
30
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
SPD Contents
HYS72D128520GR–7F–B
HYS72D128521GR–8–B
HYS72D128521GR–7–B
HYS72D128521GR–7F–B
Label Code
HYS72D128520GR–7–B
SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8
Part Number & Organization
Table 15
×72
×72
×72
×72
×72
2 Ranks
2 Ranks
2 Ranks
2 Ranks
2 Ranks
reg
reg
reg
reg
reg
PC2100R20330-N
PC2100R20220-N
PC1600R20220-N
PC2100R20330-N
PC2100R20220-N
HEX
HEX
HEX
HEX
HEX
Jedec SPD Revision
Byte# Description
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95
Module Serial Number (1)
xx
xx
xx
xx
xx
96
Module Serial Number (2)
xx
xx
xx
xx
xx
97
Module Serial Number (3)
xx
xx
xx
xx
xx
98
Module Serial Number (4)
xx
xx
xx
xx
xx
99127
not used
00
00
00
00
00
Data Sheet
31
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Package Outlines
5
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
30.48 ±0.13
4 ±0.1
1)
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 4
Data Sheet
Package Outlines Raw Card L (L-DIM-184-13)
32
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
4 MAX.
A
30.48 ±0.13
4 ±0.1
1)
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
1)
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 5
Data Sheet
Package Outlines Raw Card M (L-DIM-184-12)
33
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Package Outlines
0.1 A B C
133.35
0.15 A B C
128.95
6.81 MAX.
A
30.48 ±0.13
4 ±0.1
1)
1
2.5 ±0.1
ø0.1 A B C
92
6.62
B C
2.175
0.4
6.35
64.77
1.27 ±0.1
49.53
0.1 A B C
93
184
17.8
1.8 ±0.1
10
3.8 ±0.13
95 x 1.27 = 120.65
1)
3 MIN.
0.2
2.5 ±0.2
Detail of contacts
1.27
1 ±0.05
0.1 A B C
1) On ECC modules only
Burr max. 0.4 allowed
Figure 6
Data Sheet
Package Outlines Raw Card N (L-DIM-184-14)
34
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Application Note
6
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item
1173)
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and
to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements
permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked
Loop) when the memory is in Self-Refresh mode.
The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other SDRAM
inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low level, all the
register outputs are forced to a low level, and all differential register input receivers are powered down, resulting
in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as
an asynchronous signal according to the attached details. Using this function also permits the system and DIMM
clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh
mode.
Table 16
RESET Truth Table
Register Inputs
Register
Outputs
RESET
CK
CK
Data in (D)
Data out (Q)
H
Rising
Falling
H
H
H
Rising
Falling
L
L
H
L or H
L or H
X
Qo
H
High Z
High Z
X
Illegal input
conditions
L
X or Hi-Z
X or Hi-Z
X or Hi-Z
L
X: Don’t care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling
As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are
maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low
maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until
activated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.
The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz
or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating
frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual
detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made
High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less than
1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied
inactive on the DIMM.
This application note describes the required and optional system sequences associated with the DDR Registered
DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control
CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
35
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Application Note
Power-Up Sequence with RESET — Required
1. The system sets RESET at a valid low level.
This is the preferred default state during power-up. This input condition forces all register outputs to a low state
independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level
at the DDR SDRAMs.
2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR
SDRAMs.
3. Stabilization of Clocks to the SDRAM
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a
stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior to
SDRAM operation.
4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would
be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
5. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs
must remain stable).
6. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows their clock receivers, data input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence).
Self Refresh Entry (RESET low, clocks powered off) — Optional
Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down
and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.
Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption
(RESET low deactivates register CK and CK, data input receivers, and data output drivers).
1. 1. The system applies Self Refresh entry command.
(CKE→Low, CS→Low, RAS → Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares— with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the registerm
inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level
at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a
specific clock edge is not required.
3. The system turns off clock inputs to the DIMM. (Optional)
a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
36
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Application Note
inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the
register (t (INACT). The deactivate time defines the time in which the clocks and the control and address
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b.The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which
the clocks and the control and the address signals must maintain valid levels after RESET low has been
applied. It is highly recommended that CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM.
The system must drive clocks to the application frequency (PLL operation is not assured until the input clock
reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,
and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL,
the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector).
CKE must be maintained low and all other inputs should be driven to a known state. In general these
commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command
(with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to
be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
RESET timing relationship to a specific clock edge is not required (during this period, register inputs must
remain stable).
4. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE
outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time
(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to
accept an input signal, is specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. 1. System enters Self Refresh entry command.
(CKE→ Low, CS→ Low, RAS→ Low, CAS→ Low, WE→ High)
Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level.
This input condition forces all register outputs to a low state, independent of the condition on the data and clock
register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z.
This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes
the time in which the clocks and the control and the address signals must maintain valid levels after RESET
low has been applied. It is highly recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
37
Rev. 1.03 2004-01
HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B
Registered DDR SDRAM-Modules
Application Note
Self Refresh Exit (RESET low, clocks running) — Optional
1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this
would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be
consistent with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is t (ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note. In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
Data Sheet
38
Rev. 1.03 2004-01
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