White Electronic Designs EDI88512CA 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES Access Times of 15, 17, 20, 25, 35, 45, 55ns Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx8 Commercial, Industrial and Military Temperature Ranges 32 lead JEDEC Approved Evolutionary Pinout The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MILPRF-38535. • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Package 321) • Ceramic SOJ (Package 140) 36 lead JEDEC Approved Revolutionary Pinout • Ceramic Flatpack (Package 316) • Ceramic SOJ (Package 327) *This product is subject to change without notice. • Ceramic LCC (Package 502) Single +5V (±10%) Supply Operation FIG. 1 PIN CONFIGURATION PIN DESCRIPTION I/O0-7 36 PIN TOP VIEW A0 A1 A2 A3 A4 CS# I/O0 I/O1 Vcc Vss I/O2 I/O3 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 36 pin 9 Revolutionary 10 11 12 13 14 15 16 17 18 32 PIN TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE# I/O7 I/O6 Vss Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A0-18 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 pin Evolutionary Vcc A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 WE# CS# OE# VCC VSS NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected BLOCK DIAGRAM Memory Array A0-18 Address Buffer Address Decoder I/O Circuits I/O0-7 WE# CS# OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss TRUTH TABLE Value Unit -0.5 ≤ TA ≤ 7.0 V OE# X H L X Operating Temperature TA (Ambient) CS# H L L L 0 ≤ TA ≤ +70 °C Industrial -40 ≤ TA ≤ +85 °C Military -55 ≤ TA ≤ +125 °C Parameter Storage Temperature, Plastic -65 ≤ TA ≤ +150 °C Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Commercial Power Dissipation 1.5 W Output Current 20 mA Junction Temperature, TJ 175 °C WE# X H H L Mode Standby Output Deselect Read Write Output High Z High Z Data Out Data In Power Icc2, Icc3 Icc1 Icc1 Icc1 RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit VCC VSS VIH VIL 4.5 0 2.2 -0.3 5.0 0 — — 5.5 0 3.0 +0.8 V V V V CAPACITANCE NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (TA = +25°C) Parameter Symbol Condition Max Unit Address Lines CI VIN = Vcc or Vss, f = 1.0MHz 12 pF Data Lines CO VOUT = Vcc or Vss, f = 1.0MHz 14 pF These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, TA = -55°C to +125°C) Parameter Symbol Conditions Min Max Units Input Leakage Current ILI VIN = 0V to VCC -10 10 A Output Leakage Current ILO VI/O = 0V to VCC -10 10 A Operating Power Supply Current ICC1 WE#, CS# = VIL, II/O = 0mA, Min Cycle — — 250 225 mA mA Standby (TTL) Power Supply Current ICC2 CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH — 60 mA Full Standby Power Supply Current ICC3 CS# ≥ VCC -0.2V VIN ≥ Vcc -0.2V or VIN ≤ 0.2V — — 25 20 mA mA Output Low Voltage VOL IOL = 6.0mA — 0.4 V Output High Voltage VOH IOH = -4.0mA 2.4 — V (17ns) (20 -55ns) CA LPA NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V AC TEST CONDITIONS Figure 1 Figure 2 Vcc Input Pulse Levels Vcc VSS to 3.0V Input Rise and Fall Times Input and Output Timing Levels 480Ω Q 480Ω Output Load 30pF Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2) Q 255Ω 5ns 1.5V 255Ω 5pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA AC CHARACTERISTICS – READ CYCLE (VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C) Symbol Parameter 15ns 17ns Alt. Min tAVAV tRC 15 Address Access Time tAVQV tAA 15 17 20 25 35 Chip Enable Access Time tELQV tACS 15 17 20 25 35 tELQX tCLZ 2 tEHQZ tCHZ 0 Output Hold from Address Change tAVQX tOH 0 Output Enable to Output Valid tGLQV tOE Output Enable to Output in Low Z (1) tGLQX tOLZ 0 Output Disable to Output in High Z(1) tGHQZ tOHZ 0 Max 17 Min 20 3 7 Min 7 8 10 Units 45 55 ns 45 55 ns ns 0 0 20 0 15 30 0 0 20 ns ns 25 0 0 ns 3 20 15 10 Max 55 0 0 0 Min 3 15 12 8 Max 55ns 45 0 0 0 Min 0 10 7 45ns 3 0 0 0 Max 35 0 8 0 Min 3 0 0 8 Max 25 3 0 0 7 Max 35ns JEDEC Chip Disable to Output in High Z (1) Min 25ns Read Cycle Time Chip Enable to Output in Low Z (1) Max 20ns ns ns 0 20 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – WRITE CYCLE (VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C) Symbol Parameter 15ns 17ns Max Max Min Min Max Min tWC 15 17 20 25 35 45 55 ns Chip Enable to End of Write tELWH tELEH tCW tCW 13 13 14 14 15 15 17 17 25 25 30 30 50 50 ns ns Address Setup Time tAVWL tAVEL tAS tAS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns Address Valid to End of Write tAVWH tAVEH tAW tAW 13 13 14 14 15 15 17 17 25 25 30 30 50 50 ns ns Write Pulse Width tWLWH tWLEH tWP tWP 13 13 14 14 15 15 17 17 25 25 30 30 45 45 ns ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns 8 0 10 0 25 Min 0 Max 55ns Alt. 0 Max 45ns tAVAV 8 Min 35ns JEDEC 0 Max 25ns Write Cycle Time 8 Min 20ns 30 Min 0 Max 30 Units Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 8 8 8 8 10 10 12 12 20 20 25 25 40 30 ns ns ns Output Active from End of Write (1) tWHQX tWLZ 0 0 0 0 0 0 0 ns 1. This parameter is guaranteed by design but not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA FIG. 2 TIMING WAVEFORM - READ CYCLE tAVAV ADDRESS tAVQV tAVAV ADDRESS DATA I/O CS# ADDRESS 1 ADDRESS 2 tAVQV tAVQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE# DATA 1 DATA 2 DATA OUT READ CYCLE 1 (WE# HIGH; OE#, CS# LOW) READ CYCLE 2 (WE# HIGH) FIG. 3 WRITE CYCLE - WE# CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS# tAVWL tWLWH WE# tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH Z DATA OUT WRITE CYCLE 1, WE# CONTROLLED FIG. 4 WRITE CYCLE - CS# CONTROLLED tAVAV ADDRESS tAVEH tELEH tEHAX CS# tAVEL tWLEH WE# tDVEH DATA IN DATA OUT tEHDX DATA VALID HIGH Z WRITE CYCLE 2, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY) (-55°C ≤ TA ≤ +125°C) Characteristic Low Power Version only Sym Conditions Min Typ Max Units Data Retention Voltage Data Retention Quiescent Current VCC ICCDR VCC = 2.0V CS# ≥ VCC -0.2V 2 – – – – 2 V mA Chip Disable to Data Retention Time Operation Recovery Time tCDR TR VIN ≥ VCC -0.2V or VIN ≤ 0.2V 0 tAVAV – – – – ns ns FIG. 5 DATA RETENTION - CS# CONTROLLED DATA RETENTION MODE 4.5V VCC WS32K32-XHX VCC 4.5V tCDR CS# tR CS# = VCC -0.2V DATA RETENTION, CS# CONTROLLED White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA 1.616 1.584 0.200 0.125 0.100 TYP 0.020 0.016 0.061 0.017 0.620 0.600 0.060 0.040 Pin 1 Indicator 0.155 0.115 0.600 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP 1.616 1.584 0.420 0.400 Pin 1 Indicator 1 0.200 0.125 0.100 TYP 0.020 0.016 0.061 0.017 0.155 0.115 1 0.400 NOM 15 x 0.100 = 1.500 ALL DIMENSIONS ARE IN INCHES PACKAGE 140: 32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA 0.010 0.006 0.019 0.015 0.840 0.820 0.444 0.430 0.379 0.050 TYP 0.155 0.106 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA 0.920 ± 0.010 0.007 0.003 0.370 0.250 1.00 REF 0.395 0.385 0.515 0.505 0.040 0.030 Pin 1 0.045 0.020 0.019 0.015 0.125 0.100 0.050 TYP ALL DIMENSIONS ARE IN INCHES PACKAGE 321: 32 PIN THINPACK™ FLATPACK, SMD 5962-95600XXMYA 0.838 MAX 0.567 0.427 0.559 0.429 0.050 TYP 0.016 ± 0.008 0.008 0.005 0.020 0.030 0.118 MAX. ALL DIMENSIONS ARE IN INCHES PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A +0.002 0.006 -0.001 0.423 ± 0.004 0.024 REF. 0.112 MAX. 0.838 MAX. 0.050 ± 0.002 TYP. 0.016 ± 0.008 0.300 ± 0.010 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA 0.010 0.006 0.019 0.015 0.920 0.940 0.050 TYP 0.444 0.434 0.379 0.155 0.106 ALL DIMENSIONS ARE IN INCHES PACKAGE 502: 36 LEAD CERAMIC LCC, SMD 5962-95600XXMNA (PENDING) 0.135 0.115 0.100 0.080 36 1 0.100 TYP 0.009 TYP 0.930 0.910 0.028 0.022 0.860 0.840 0.050 BSC 0.460 0.445 0.066 0.054 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88512CA ORDERING INFORMATION EDI 8 8 512 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 512Kx8 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) K = 36 lead Ceramic LCC (Package 502) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 326) B32 = 32 pin Ceramic Thinpack™ Flatpack (Package 321) F32 = 32 pin Ceramic Flatpack (Package 344) F36 = 36 pin Ceramic Flatpack (Package 316) N36 = 36 lead Ceramic SOJ (Package 327) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55°C ≤ TA ≤ +125°C I = Industrial -40°C ≤ TA ≤ +85°C C = Commercial 0°C ≤ TA ≤ +70°C White Electronic Designs Corp. reserves the right to change products or specifications without notice. October 2004 Rev. 11 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com