2.5 Gbit/s Retiming Laser Driver GD16571 an Intel company Preliminary General Description Features The GD16571 is a high performance low power 2.5 Gbit/s Laser Driver with optional on chip retiming of data. The GD16571 is designed to meet and exceed ITU-T STM-16 or SONET OC-48 fiberoptic communication systems requirements. The GD16571 is designed to sink a Modulation Current into the IOUT pin and a Pre-Bias Current into the IPRE pin. The Modulation Current is adjustable up to 70 mA by means of the pin VMOD. The Pre-Bias Current may be adjusted up to 50 mA by means of the VPRE pin. VADJEF Retiming of the data signal connected to the pins DIN, DINQ is made by means of a DFF clocked by an external clock signal at the data rate fed to the pins CKIN and CKINQ. A Mark-Space monitor is available on the pins MARKP and MARKN. Together with the symmetry adjustment pin (SYM) this may be used to control the mark space ratio of the output signal. The GD16571 is implemented in a Silicon Bipolar process and requires a single +5 V supply or a single -5.2 V supply. The circuit is available in a thermally enhanced 32-pin TQFP plastic package. VMOD Modulation Current Control VADJBUF VPRE Pre-Bias Current Control CKSEL Input Buffer D DINQ 50 Input Buffer CKIN CKINQ Mark/Space Monitor Complies with ITU-T STM-16 and SONET OC-48 standards. l Intended for driving a 25 W load, e.g. a laser diode with 25 W input impedance. l Clocked or non-clocked operation. l Large modulation current adjustment range from 5 mA to 70 mA. l Output voltage over / under shoot less than ±2 % respectively ± 5 %. l Rise / fall times less than 100 ps. l Laser diode pre-bias adjustable up to 50 mA. l Mark-Space monitor. l Symmetry adjustment. l Internal 50 W termination of data and clock inputs. l Operates up to 3.5 Gbit/s. l Power dissipation: 0.38 W. Excluding Modulation Current and Pre-bias Current. l Silicon Bipolar process. l 32 pin thermally enhanced TQFP plastic package. IPRE VDD VDDR VDDCONT IOUT IOUTN 50 DINT VEE VEEP VEEB VEER MARKP MARKN 50 CKINT Q MUX DIN Output Driver l 50 SYM Applications l Tele Communication: – SDH STM-16 – SONET OC-48 l Datacom up to 3.125 Gbit/s. l Electro Absorption laser driver. l Direct Modulation laser driver. Data Sheet Rev.: 10 Functional Details GD16571 the voltage overshoot is less than 2 % across the full modulation current range, when driving a 25 W load. Similarly the voltage undershoot is less than 5 %. The output modulation current is controlled by the pin VMOD and can be controlled in the range from 0 mA to 70 mA, however the specifications is only valid in the range from 5 mA to 70 mA. The output voltage swing across the external load may be varied accordingly. The modulation current control on pin VMOD is implemented as a current mirror and therefore sinks a current proportional to the modulation current. The current sink into the VMOD pin is approximately 3/80 of the modulation current. Two additional pins (VADJBUF and VADJEF) are available in order to optimise the performance of the output signal quality, specifically with respect to overshoot and undershoot. Typically best performance is obtained if these pins are connected to VMOD. GD16571 is a 2.5 Gbit/s laser driver with an optional retiming of the data signal. It is capable of driving high power laser diodes, typically having input impedance of 25 W, at a maximum modulation current of 70 mA and a maximum pre-bias current of 50 mA. Data (DIN, DINQ) is input to GD16571 and retimed within a DFF clocked by an external clock (CKIN, CKINQ). Optionally the retiming may be bypassed controlled by a select pin (CKSEL). Both the differential data (DIN, DINQ) and clock inputs (CKIN, CKINQ) are internally terminated to 50 W. Termination is made with a 50 W resistor from the two differential inputs to a common pin called DINT and CKINT respectively. The input sensitivity when driven with a single ended signal is better than 150 mV on both clock and data inputs. A mark-space monitor is provided through the pins MARKP and MARKN. These may be connected as shown in the application diagram below, with a capacitor across the two outputs and a comparator (or Op-amp) to determine the mark density. Symmetry input (SYM) is available which may be used to control the mark-space ratio. AC Coupled Output When DC coupled the output swing will be limited by IOUT output voltage specified to -2 V. For maximum output voltage swing the output should be AC coupled. The pre-bias current is controlled by the pin VPRE and can be controlled from 0 mA to 50 mA. The pre-bias current control on pin VPRE is implemented as a current mirror and therefore sinks a current proportional to the pre-bias current. The current sink into the VPRE pin is approximately 3/500 of the pre-bias current. The output pin (IOUT) is an open collector output designed for driving external loads with 25 W characteristic impedance. Because of the nature of an open collector the output therefore may be regarded as a current switch, with infinite output impedance. The characteristic impedance through the package is approximately 25 W. Optimum performance of GD16571 therefore is achieved if the output is terminated into a 25 W impedance. VDD L1 220uH L3 220uH L2 L4 100nF IOUTN 25W VDD Figure 2. AC Coupled Output Control Voltage from Pre-Bias Current Control System VMOD / 20 VPRE / 16 Modulation Current Control Pre-Bias Current Control Laser Diode Equivalent 25 W Input Impedance VDD IPRE / 19 VDD Differential or Single-ended Data Signal 50 DIN / 27 50 DINQ / 26 100n Differential or Single-ended Clock Signal Input Buffer DINT / 28 50 50 CKIN / 31 50 CKINQ / 32 50 100n CKINT / 30 25 L Output Driver 25 C IOUT / 13, 14 C 25 IOUTN / 11, 12 50 L Input Buffer L1 and L3 = Siemens Chip Inductors (B82432A1224K). L2 and L4 = Siemens ferrite cores B64290-A36-X33 with 8 turns of 0.22mm Cu-Wire. 100nF IOUT An important parameter for laser drivers is voltage overshoot on the output pin (IOUT), because it determines the extinction ratio. GD16571 has been designed with special emphasis on achieving a very small voltage overshoot. For Control Voltage from Modulation Current Control System VDD Mark/Space Monitor VDD VDD MARKP / 7 100n MARKN / 6 50 - VEEP / 18 Negative Supply + Ref. Figure 1. Application Diagram Data Sheet Rev.: 10 GD16571 Page 2 of 7 Pin List Mnemonic: Pin No.: Pin Type: DIN DINQ 27 26 AC IN Data inputs. Internally terminated in 50 W to DINT. Internally biased to -1.3 V DINT 28 ANL IN Termination voltage for DIN and DINQ. CKIN CKINQ 31 32 AC IN Clock inputs. Internally terminated in 50 W to CKINT. Internally biased to -1.3 V. CKINT 30 ANL IN Termination voltage for CKIN and CKINQ. IOUT IOUTN 13, 14 11, 12 OPEN COLLECTOR Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modulation current, which is controlled by the pin VMOD. The current into IOUT is high when data is high on DIN. IPRE 19 OPEN COLLECTOR Pre-bias current output. IPRE sinks a current, which is controlled by the pin VPRE. VMOD 20 ANL IN Modulation current control input. The control system is made as a current mirror. VMOD sinks a current proportional to the modulation current. This current is approximately 3/80 times “The modulation current”. VPRE 16 ANL IN Pre-bias current control input. The control system is made as a current mirror. VPRE sinks a current proportional to the pre-bias current. This current is approximately 3/500 times “The pre-bias current”. CKSEL 1 ECL IN When CKSEL is low data is retimed. Otherwise data is bypassed the retiming. SYM 24 ANL IN SYM controls the mark-space ratio of the output. Decreasing the voltage of the SYM pin decreases the pulse width of a current high into the IOUT pin. MARKP MARKN 7 6 ANL OUT Mark-space monitor outputs. High impedance CML outputs. The output voltage of the MARKP pin is the same as the voltage on the DIN input. VADJBUF VADJEF 22 21 ANL IN 2, 4, 10, 15 PWR Ground pins for laser driver part. VDDCONT 3 PWR Ground pin for modulation current control system. VDDR 29 PWR Ground pin for retiming part. 5, 8, 23 PWR Negative supply pins for laser driver part. VEEP 18 PWR Negative supply pin for output driver. VEEB 17 PWR Negative supply pin for pre-bias circuitry. VEER 25 PWR Negative supply pin for retiming part. NC 9 VDD VEE Heat sink Data Sheet Rev.: 10 Package back Description: Pins used to optimise the performance of the output in terms of overshoot and undershoot. Typically optimum performance will be achieved when shorted to VMOD. Not Connected. Connected to VEE. GD16571 Page 3 of 7 Package Pinout CKINQ CKIN CKINT VDDR DINT DIN DINQ VEER 32 31 30 29 28 27 26 25 CKSEL 1 24 SYM VDD 2 23 VEE VDDCONT 3 22 VADJBUF VDD 4 21 VADJEF VEE 5 20 VMOD MARKN 6 19 IPRE MARKP 7 18 VEEP VEE 8 17 VEEB 9 10 11 12 13 14 15 16 NC VDD IOUTN IOUTN IOUT IOUT VDD VPRE Figure 3. Package 32 TQFP, Top View Maximum Ratings These are the limits beyond which the component may be damaged. All voltages in table are referred to VDD. All currents in table are defined positive out of the pin. Symbol: Characteristic: VEE Power Supply VO MAX.: UNIT: -6 0 V Applied Voltage (All Outputs) VEE -0.5 2 V VI Applied Voltage (All Inputs) VEE -0.5 0.5 V II AC IN Input Current (AC IN) -1 1 mA II VMOD Input Current (VMOD) -4 1 mA II VPRE Input Current (VPRE, VADJBUF and VADJEF) Note 1 -1 1 mA TO Operating Temperature Base -55 +125 °C TS Storage Temperature -65 +165 °C Note 1: Conditions: MIN.: TYP.: Voltage and/or current should be externally limited to specified range. Data Sheet Rev.: 10 GD16571 Page 4 of 7 DC Characteristics TCASE = -40 °C to 85 °C, appropriate heat sinking may be required. All voltages in table are referred to VDD. All currents in table are defined positive out of the pin. Symbol: Characteristic: Conditions: VEE Power Supply IEE Negative Supply Current IOUT = 0 A PDISS Power Dissipation VEE = -5.0 V, IOUT = 0 A, IPRE = 0 A Vpp AN IN Peak-peak Voltage when Input is Driven Single VVTH= -1.3 V ended. V VMOD MIN.: TYP.: MAX.: UNIT: -5.5 -5.2 -4.7 V 75 0.5 W 150 800 mV Voltage Range for VMOD VEE VDD V I VMOD Sink Current into Pin VMOD -4 0 mA VIN NN Input Voltage Range for VPRE, VADJBUF, VADJEF and SYM VEE VDD V ISINK NN Sink Current into pin VPRE, VADJBUF, VADJEF and SYM -1 0 mA VIN SYM Input Voltage Range for SYM VEE VDD V ILEAK SYM Leakage Current for CKSEL -1 1 mA VIN CKSEL Input Voltage Range for CKSEL VEE VDD V ILEAK CKSEL Leakage Current for SYM -1 1 mA VLO MARK Low Output Voltage for Mark-Space Monitor -2.0 V RO MARK Output Impedance for Mark-Space Monitor 4.0 kW VO IPRE IPRE Output Voltage -2.0 I IPRE IPRE Current -50 VO IOUT IOUT Output Voltage Note 1 -2.0 IMod,HI IOUT IOUT High Modulation Current Note 1,2 -70 0 mA IMod,LO IOUT IOUT Low Modulation Current Note 1,3 -3 1 mA Note 1: Note 2: Note 3: 0.38 mA V 0 mA V RLOAD = 25 W to VDD connected to pin IOUT. Sink current is controlled by the VMOD pin, and may be adjusted in the range as specified. Notice that high modulation current means that the output voltage level is low. The AC parameters are only specified in the range from -70 mA to -5 mA. However at TCASE = 0 °C to 70 °C AC parameters are specified from -80 mA to -5 mA. This is a leakage current. Max leakage current is present at max modulation current (i.e. at 70 mA modulation current). The leakage current decreases for smaller leakage currents. Data Sheet Rev.: 10 GD16571 Page 5 of 7 AC Characteristics TCASE = -40 °C to 85 °C, appropriate heat sinking may be required. Symbol: Characteristic: fMAX OUT Data Output Frequency Jpp OUT Added Output Jitter Note 1 20 ps tRISE OUT Output Rise Time Note 1 100 ps tFALL OUT Output Fall Time Note 1 100 ps tPM Phase Margin Clock to Data 300 tS Data Set-up Time 60 30 ps tH Data Hold Time 20 5 ps DCROSS_OVER Output Cross Over Control Range Note 1: Conditions: MIN.: TYP.: MAX.: UNIT: 2500 Note 1 Mbit/s ps ± 30 % RLOAD = 25 W to VDD connected to pin IOUT. ILD = 70 mA. Rise/Fall times at 20 – 80 % of HI/LO voltage levels. Package Outline Figure 4. Package 32 pin. All dimensions are in mm. Data Sheet Rev.: 10 GD16571 Page 6 of 7 Device Marking <1> = Wafer ID <2> = Design ID <3> = Wafer Lot# <4> = Assembly Lot# GD16571 <1> - <2> - <3> <4> - YYWW Pin 1 - Mark Figure 5. Device Marking, Top View. Ordering Information To order, please specify as shown below: Product Name: Intel Order Number: Package Type: Temperature Range: GD16571-32BA FAGD1657132BA 32L TQFP EDQUAD -40..85 °C MM#: 836125 GD16571, Data Sheet Rev.: 10 - Date: 24 July 2001 an Intel company Mileparken 22, DK-2740 Skovlunde Denmark Phone : +45 7010 1062 Fax : +45 7010 1063 E-mail : [email protected] Web site : http://www.intel.com/ixa Please check our Internet web site for latest version of this data sheet. The information herein is assumed to be reliable. GIGA assumes no responsibility for the use of this information, and all such information shall be at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. GIGA does not authorise or warrant any GIGA Product for use in life support devices and/or systems. Distributor: Copyright © 2001 GIGA ApS An Intel company All rights reserved