CY62148EV30 MoBL® 4-Mbit (512K x 8) Static RAM Functional Description [2] Features • Very high speed: 45 ns The CY62148EV30 is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). — Wide voltage range: 2.20V – 3.60V • Pin compatible with CY62148DV30 • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 7 µA (Industrial) • Ultra low active power • • • • — Typical active current: 2 mA @ f = 1 MHz Easy memory expansion with CE, and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin SOIC [1] packages To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. Logic Block Diagram IO0 INPUT BUFFER IO1 IO2 SENSE AMPS ROW DECODER 512K x 8 ARRAY IO3 IO4 IO5 IO6 CE IO7 POWER DOWN A18 A17 A13 A14 OE A15 COLUMN DECODER WE A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Notes 1. SOIC package is available only in 55 ns speed bin. 2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05576 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 18, 2007 [+] Feedback CY62148EV30 MoBL® Pin Configuration [1, 3] 36-Ball VFBGA Pinout 32-Pin SOIC/TSOP II Pinout Top View Top View A0 A1 NC A3 A6 IO 4 A2 WE A4 A7 NC A5 A8 A IO 0 B IO 1 C VSS Vcc D VCC Vss E IO 2 F IO 5 IO 6 A18 A17 IO 7 OE CE A16 A15 IO 3 G A9 A10 A11 A12 A13 A14 H A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO3 Product Portfolio Power Dissipation Product Range VCC Range (V) Speed (ns) Operating ICC (mA) f = 1 MHz CY62148EV30LL VFBGA Industrial Min Typ[4] Max 2.2 3.0 3.6 2.2 3.0 3.6 f = fmax Standby ISB2 (µA) Typ[4] Max Typ[4] Max Typ[4] Max 45 2 2.5 15 20 1 7 55 2 2.5 15 20 1 7 TSOP II CY62148EV30LL SOIC Industrial Notes 3. NC pins are not connected on the die. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05576 Rev. *F Page 2 of 12 [+] Feedback CY62148EV30 MoBL® DC Input Voltage [5, 6] .....................–0.3V to VCC(max) + 0.3V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................... 55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Supply Voltage to Ground Potential ......................................... –0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State [5, 6] ........................ –0.3V to VCC(max) + 0.3V Product Range Ambient Temperature VCC [7] CY62148EV30 Industrial –40°C to +85°C 2.2V to 3.6V Electrical Characteristics (Over the Operating Range) Parameter Description Test Conditions 55 ns [1] 45 ns Min Typ[4] Max Min Typ[4] Max Unit VOH Output HIGH Voltage IOH = –0.1 mA 2.0 IOH = –1.0 mA, VCC > 2.70V 2.4 VOL Output LOW Voltage IOL = 0.1 mA 0.4 0.2 V IOL = 2.1 mA, VCC > 2.70V 0.4 0.4 V Input HIGH Voltage VCC = 2.2V to 2.7V 1.8 VCC + 0.3V 1.8 VCC + 0.3V V VCC= 2.7V to 3.6V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V Input LOW Voltage VCC = 2.2V to 2.7V For VFBGA and TSOP II package –0.3 VIH VIL 2.0 2.4 V 0.6 For SOIC package VCC = 2.7V to 3.6V For VFBGA and TSOP II package V V 0.4 [8] –0.3 –0.3 0.8 For SOIC package V V –0.3 0.6 [8] IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC Operating Supply Current f = fmax = 1/tRC mA ISB1 Automatic CE Power Down Current — CMOS Inputs CE > VCC – 0.2V, VIN > VCC – 0.2V, VIN < 0.2V f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60V ISB2 [9] Automatic CE CE > VCC – 0.2V, Power Down VIN > VCC – 0.2V or VIN < 0.2V, Current — CMOS f = 0, VCC = 3.60V Inputs f = 1 MHz VCC = VCC(max), IOUT = 0 mA, CMOS levels 15 20 15 20 2 2.5 2 2.5 1 7 1 7 µA 1 7 1 7 µA Notes 5. VIL(min) = –2.0V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 8. Under DC conditions the device meets a VIL of 0.8V (for VCC range of 2.7V to 3.6V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to AN13470 for details. 9. Only chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05576 Rev. *F Page 3 of 12 [+] Feedback CY62148EV30 MoBL® Capacitance (For All packages) [10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max TA = 25°C, f = 1 MHz, VCC = VCC(typ) Unit 10 pF 10 pF Thermal Resistance [10] Parameter Test Conditions VFBGA Package TSOP II Package SOIC Package Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 72 75.13 55 °C/W 8.86 8.95 22 °C/W Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) AC Test Loads and Waveforms R1 VCC OUTPUT ALL INPUT PULSES VCC R2 30 pF INCLUDING JIG AND SCOPE 90% 10% GND Rise Time = 1 V/ns Equivalent to: 90% 10% Fall Time = 1 V/ns THEVENIN EQUIVALENT OUTPUT RTH V Parameters 2.50V 3.0V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR Conditions VCC for Data Retention [9] Typ [4] Max Operation Recovery Time Unit V 0.8 VCC = 1.5V, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Chip Deselect to Data Retention Time [11] Min 1.5 Data Retention Current tCDR [10] tR Description 7 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5V tCDR VCC(min) tR CE Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. Document #: 38-05576 Rev. *F Page 4 of 12 [+] Feedback CY62148EV30 MoBL® Switching Characteristics (Over the Operating Range) [12] Parameter Description 55 ns [1] 45 ns Min Max Min Max Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 55 ns tDOE OE LOW to Data Valid 22 25 ns tLZOE 45 OE LOW to Low Z tHZOE [13] OE HIGH to High Z CE LOW to Low Z tLZCE CE HIGH to High Z tPU CE LOW to Power Up Write Cycle 10 55 10 ns 20 10 18 0 ns ns 20 0 45 ns ns 5 18 CE HIGH to Power Up ns 10 5 [13, 14] tHZCE tPD 45 [13, 14] [13] 55 ns ns 55 ns [15] tWC Write Cycle Time 45 55 ns tSCE CE LOW to Write End 35 40 ns tAW Address Setup to Write End 35 40 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 35 40 ns tSD Data Setup to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE tLZWE WE LOW to High Z [13, 14] WE HIGH to Low Z [13] 18 10 20 10 ns ns Notes 12. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05576 Rev. *F Page 5 of 12 [+] Feedback CY62148EV30 MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA OUT DATA VALID tLZCE tPD tPU VCC SUPPLY CURRENT HIGH IMPEDANCE 50% 50% ICC ISB Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO NOTE 21 tHD DATA VALID tHZOE Notes 16. Device is continuously selected. OE, CE = VIL. 17. WE is HIGH for read cycles. 18. Address valid before or similar to CE transition LOW. 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 21. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05576 Rev. *F Page 6 of 12 [+] Feedback CY62148EV30 MoBL® Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [19, 20] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATA IO tHD DATA VALID Write Cycle No. 3 (WE Controlled, OE LOW) [20] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD NOTE 21 DATA IO tHD DATA VALID tLZWE tHZWE Truth Table CE WE OE Inputs/Outputs H X X High Z Deselect/Power down Standby (ISB) L H L Data Out Read Active (ICC) L H H High Z Output Disabled Active (ICC) L L X Data in Write Active (ICC) Document #: 38-05576 Rev. *F Mode Power Page 7 of 12 [+] Feedback CY62148EV30 MoBL® Ordering Information Speed (ns) Ordering Code 45 CY62148EV30LL-45BVXI 55 Package Diagram Operating Range Package Type 51-85149 36-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial CY62148EV30LL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free) CY62148EV30LL-55SXI 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(36X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B Document #: 38-05576 Rev. *F 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85149-*C Page 8 of 12 [+] Feedback CY62148EV30 MoBL® Package Diagrams (continued) Figure 2. 32-pin TSOP II, 51-85095 51-85095-** Document #: 38-05576 Rev. *F Page 9 of 12 [+] Feedback CY62148EV30 MoBL® Package Diagrams (continued) Figure 3. 32-pin (450 MIL) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] SEATING PLANE 51-85081-*B MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05576 Rev. *F Page 10 of 12 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62148EV30 MoBL® Document History Page Document Title: CY62148EV30 MoBL®, 4-Mbit (512K x 8) Static RAM Document Number: 38-05576 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 223225 See ECN AJU New data sheet *A 247373 See ECN SYT Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCC stabilization time in footnote #7 from 100 µs to 200 µs Changed ICCDR from 2.0 µA to 2.5 µA Changed typo in Data Retention Characteristics (tR) from 100 µs to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages *B 414807 See ECN ZSD Changed from Preliminary information to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62148EV30 Changed ball C3 from DNU to NC. Removed the redundant footnote on DNU. Changed ICC (max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to 7 µA. Changed the AC test load capacitance value from 50pF to 30pF. Changed ICCDR from 2.5 µA to 7 µA. Added ICCDR typical value. Changed tLZOE from 3 ns to 5 ns Changed tLZCE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns. Changed tSD from 22 ns to 25 ns. Updated the package diagram 36-pin VFBGA from *B to *C Added 32-pin SOIC package diagram and pin diagram Updated the ordering information table and replaced the Package Name column with Package Diagram. *C 464503 See ECN NXR Included Automotive Range in product offering Updated Thermal Resistance table Updated the Ordering Information *D 833080 See ECN VKN Added footnote #8 Added VILspec for SOIC package *E 890962 See ECN VKN Removed Automotive part and its related information Added footnote #2 related to SOIC package Added footnote #9 related to ISB2 Added AC values for 55 ns Industrial-SOIC range Updated Ordering Information table Document #: 38-05576 Rev. *F Page 11 of 12 [+] Feedback CY62148EV30 MoBL® Document Title: CY62148EV30 MoBL®, 4-Mbit (512K x 8) Static RAM Document Number: 38-05576 REV. ECN NO. Issue Date Orig. of Change *F 987940 See ECN VKN Document #: 38-05576 Rev. *F Description of Change Changed VOL spec from 0.4V to 0.2V for SOIC package at IOL = 0.1 mA Changed VIL spec from 0.6V to 0.4V for SOIC package at VCC = 2.2V to 2.7V Updated footnote #8 Made footnote #9 applicable for both ISB2 and ICCDR Page 12 of 12 [+] Feedback