ISSI IS61LV5128-12KI 512k x 8 high-speed cmos static ram Datasheet

ISSI
®
IS61LV5128
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times:
10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 36-pin 400-mil SOJ
– 36-pin miniBGA
– 44-pin TSOP (Type II)
JULY 2001
DESCRIPTION
The ISSI IS61LV5128 is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The IS61LV5128
is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS61LV5128 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV5128 is available in 36-pin 400-mil SOJ, 36pin mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
1
ISSI
IS61LV5128
®
PIN CONFIGURATION
44-Pin TSOP (Type II)
36 mini BGA
1
2
3
4
5
6
A
A0
A1
NC
A3
A6
A8
B
I/O4
A2
WE
A4
A7
I/O0
C
I/O5
NC
A5
D
GND
Vcc
E
Vcc
GND
F
I/O6
G
I/O7
H
A9
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
I/O1
A18
A17
I/O2
OE
CE
A16
A15
I/O3
A10
A11
A12
A13
A14
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
36-Pin SOJ
PIN DESCRIPTIONS
A0-A18
Address Inputs
A0
1
36
NC
CE
Chip Enable Input
A1
2
35
A18
Output Enable Input
A2
3
34
A17
A3
4
33
A16
A4
5
32
A15
OE
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
Vcc
Power
GND
Ground
NC
No Connection
TRUTH TABLE
Mode
WE
Not Selected
X
(Power-down)
Output Disabled H
Read
H
Write
L
2
CE
OE
I/O Operation Vcc Current
H
X
High-Z
ISB1, ISB2
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
CE
6
31
OE
I/O0
7
30
I/O7
I/O1
8
29
I/O6
Vcc
9
28
GND
GND
10
27
Vcc
I/O2
11
26
I/O5
I/O3
12
25
I/O4
WE
13
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
ISSI
IS61LV5128
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
1.0
Unit
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
10 ns
VCC
12 ns, 15 ns
VCC
0°C to +70°C
3.3V +10%, -5%
3.3V ± 10%
–40°C to +85°C
3.3V +10%, -5%
3.3V ± 10%
Commercial
Industrial
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
3
ISSI
IS61LV5128
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
–0.3
0.8
V
(1)
VIL
Input LOW Voltage
ILI
Input Leakage
GND ≤ VIN ≤ VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
-10 ns
Min.
Max.
Test Conditions
-12 ns
Min.
Max.
-15 ns
Min.
Max.
Unit
ICC
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX.
Com.
Ind.
—
—
145
155
—
—
135
145
—
—
125
135
mA
ISB
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
Com.
Ind.
—
—
70
80
—
—
60
70
—
—
50
60
mA
ISB1
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
20
25
—
—
20
25
—
—
20
25
mA
ISB2
CMOS Standby
Current
(CMOS Inputs)
VCC = Max.,
CE ≤ VCC – 0.2V,
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
—
—
10
15
—
—
10
15
—
—
10
15
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
ISSI
IS61LV5128
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 ns
Min.
Max.
-12 ns
Min.
Max.
-15 ns
Min.
Max.
Symbol
Parameter
tRC
Read Cycle Time
10
—
12
—
15
—
ns
tAA
Address Access Time
—
10
—
12
—
15
ns
tOHA
Output Hold Time
3
—
3
—
3
—
ns
tACE
CE Access Time
—
10
—
12
—
15
ns
OE Access Time
—
4
—
5
—
7
ns
OE to Low-Z Output
0
—
0
—
0
—
ns
tHZOE
OE to High-Z Output
0
4
0
5
0
6
ns
tLZCE(2)
CE to Low-Z Output
3
—
3
—
3
—
ns
tHZCE(2)
tPU
tPD
CE to High-Z Output
0
4
0
6
0
8
ns
Power Up Time
0
—
0
—
0
—
ns
Power Down Time
—
10
—
12
—
15
ns
tDOE
tLZOE
(2)
(2)
Unit
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
Figure 1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
5 pF
Including
jig and
scope
353 Ω
Figure 2
5
ISSI
IS61LV5128
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t ACE
t HZCE
t LZCE
DOUT
HIGH-Z
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
ISSI
IS61LV5128
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 ns
Min.
Max.
-12 ns
Min.
Max.
-15 ns
Min.
Max.
Symbol
Parameter
tWC
Write Cycle Time
10
—
12
—
15
—
ns
tSCE
CE to Write End
8
—
9
—
10
—
ns
tAW
Address Setup Time to
8
—
Write End
9
—
10
—
ns
tHA
Address Hold from
0
—
Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
ns
tPWE1
WE Pulse Width
8
—
8
—
10
—
ns
tPWE2
WE Pulse Width (OE = LOW)
10
—
12
—
12
—
ns
tSD
Data Setup to Write End
6
—
6
—
7
—
ns
tSA
(4)
tHD
Data Hold from Write End
0
—
0
—
0
—
ns
(2)
WE LOW to High-Z Output
0
5
0
6
0
7
ns
(2)
WE HIGH to Low-Z Output
0
—
0
—
0
—
ns
tHZWE
tLZWE
Unit
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
7
ISSI
IS61LV5128
®
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
ISSI
IS61LV5128
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Speed (ns)
Order Part No.
10
10
10
IS61LV5128-10K
IS61LV5128-10T
IS61LV5128-10B
400-mil Plastic SOJ
TSOP (Type II)
mini BGA (8mmx10mm)
10
10
10
IS61LV5128-10KI
IS61LV5128-10TI
IS61LV5128-10BI
400-mil Plastic SOJ
TSOP (Type II)
mini BGA (8mmx10mm)
12
12
12
IS61LV5128-12K
IS61LV5128-12T
IS61LV5128-12B
400-mil Plastic SOJ
TSOP (Type II)
mini BGA (8mmx10mm)
12
12
12
IS61LV5128-12KI
IS61LV5128-12TI
IS61LV5128-12BI
400-mil Plastic SOJ
TSOP (Type II)
mini BGA (8mmx10mm)
15
15
15
IS61LV5128-15K
IS61LV5128-15T
IS61LV5128-15B
400-mil Plastic SOJ
TSOP (Type II)
mini BGA (8mmx10mm)
15
15
15
IS61LV5128-15KI
IS61LV5128-15TI
IS61LV5128-15BI
400-mil Plastic SOJ
TSOP (Type II)
mini BGA (8mmx10mm)
Package
Package
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
9
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