HP HCPL-060L High speed lvttl compatible 3.3 volt optocoupler Datasheet

Agilent HCPL-260L/ 060L/263L/063L
High Speed LVTTL Compatible
3.3 Volt Optocouplers
Data Sheet
Features
• Low power consumption
• 15 kV/µs minimum Common Mode
Rejection (CMR) at VCM = 50 V
• High speed: 15 MBd typical
• LVTTL/LVCMOS compatible
Description
The HCPL-260L/060L/263L/063L
are optically coupled gates that
combine a GaAsP light emitting
diode and an integrated high gain
photo detector. An enable input
allows the detector to be strobed.
The output of the detector IC is an
open collector Schottky-clamped
transistor. The internal shield
provides a guaranteed common
mode transient immunity
specification of 15 kV/ µs.
• Low input current capability:
5 mA
This unique design provides
maximum AC and DC circuit
isolation while achieving
LVTTL/LVCMOS compatibility.
The optocoupler AC and DC
operational parameters are
guaranteed from –40˚C to +85˚C
allowing trouble-free system
performance.
• Guaranteed AC and DC performance
over temperature: –40˚C to +85˚C
• Available in 8-pin DIP, SOIC-8
• Strobable output (single channel
products only)
• Safety approvals; UL, CSA, VDE
(pending)
Applications
• Isolated line receiver
• Computer-peripheral interfaces
Functional Diagram
• Microprocessor system interfaces
HCPL-260L/060L
ANODE 1
1
8
VCC
VE
CATHODE 1
2
7
VO1
• Instrument input/output isolation
6
VO
CATHODE 2
3
6
VO2
• Ground loop elimination
5
GND
ANODE 2
4
5
GND
• Pulse transformer replacement
NC
1
8
VCC
ANODE
2
7
CATHODE
3
NC
4
SHIELD
• Digital isolation for A/D, D/A
conversion
HCPL-263L/063L
SHIELD
• Switching power supply
• Field buses
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.
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These optocouplers are suitable
for high speed logic interfacing,
input/output buffering, as line
receivers in environments that
conventional line receivers
cannot tolerate and are
recommended for use in
extremely high ground or induced
noise environments.
These optocouplers are available
in an 8-pin DIP and industry
standard SO-8 package. The part
numbers are as follows:
8-pin DIP
HCPL-260L
HCPL-263L
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-260L #XXX
060 = VDE 0884 VIORM = 630 Vpeak Option
500 = Tape and Reel Packaging Option
Option data sheets available. Contact Agilent sales representative or
authorized distributor for information.
SO-8 Package
HCPL-060L
HCPL-063L
Schematic
IF
HCPL-263L/063L
HCPL-260L/060L
ICC
8
2+
IO
6
ICC
VCC
1
VO
8
IF1
IO1
+
7
VCC
VO1
VF1
–
VF
–
3
2
SHIELD
5
IE
GND
7
SHIELD
3
VE
IF2
IO2
–
USE OF A 0.1 F BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
6
VO2
VF2
+
4
5
SHIELD
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GND
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
OPTION CODE*
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A XXXXZ
YYWW RU
1
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
5° TYP.
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
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Small Outline SO-8 Package
8
7
6
5
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
2
PIN ONE 1
3
4
0.406 ± 0.076
(0.016 ± 0.003)
1.270 BSG
(0.050)
* 5.080 ± 0.127
(0.200 ± 0.005)
7°
3.175 ± 0.127
(0.125 ± 0.005)
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
0.305 MIN.
(0.012)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
TEMPERATURE – °C
Solder Reflow Temperature Profile
(Surface Mount Option Parts)
260
240
220
200
180
160
140
120
100
80
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
UL
Approval (pending) under UL
1577, Component Recognition
Program, File E55361.
60
40
20
0
Regulatory Information
The HCPL-260L/060L/263L/063L
are pending by the following
organizations:
0
1
∆T = 100°C, 1.5°C/SEC
CSA
2
Approval (pending) under CSA
Component Acceptance Notice
#5, File CA 88324.
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS HIGHLY RECOMMENDED.
VDE
Approval (pending) according to
VDE 0884/06.92.
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Insulation and Safety Related Specifications
Parameter
Minimum External Air
Gap (External Clearance)
Minimum External Tracking
(External Creepage)
Minimum Internal Plastic
Gap (Internal Clearance)
Minimum Internal Tracking
(Internal Creepage)
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
Symbol
L (101)
8-Pin DIP
(300 Mil)
Value
7.1
SO-8
Value
4.9
Units
mm
L (102)
7.4
4.8
mm
0.08
0.08
mm
NA
NA
mm
200
200
Volts
IIIa
IIIa
CTI
Conditions
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along body.
Through insulation distance, conductor to
conductor, usually the direct distance
between the photoemitter and photodetector
inside the optocoupler cavity.
Measured from input terminals to output
terminals, along internal cavity.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
VDE 0884 Insulation Related Characteristics
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, V IO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/85/21
2
630
Vpeak
VPR
1181
Vpeak
VPR
945
Vpeak
VIOTM
6000
Vpeak
TS
IS,INPUT
PS,OUTPUT
RS
175
230
600
≥ 109
˚C
mA
mW
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
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Absolute Maximum Ratings (No Derating Required up to 85˚C)
Parameter
Storage Temperature
Operating Temperature†
Average Forward Input Current
Symbol
TS
TA
IF
Reverse Input Voltage
VR
Input Power Dissipation
Supply Voltage (1 Minute Maximum)
Enable Input Voltage (Not to Exceed
VCC by more than 500 mV)
Enable Input Current
Output Collector Current
Output Collector Voltage
Output Collector Power Dissipation
PI
VCC
VE
Lead Solder Temperature
(Through Hole Parts Only)
Package**
Min.
–55
–40
Single 8-Pin DIP
Single SO-8
Dual 8-Pin DIP
Dual SO-8
8-Pin DIP, SO-8
Single 8-Pin DIP
Single SO-8
Dual 8-Pin DIP
Dual SO-8
8-Pin DIP
TLS
Solder Reflow Temperature Profile
(Surface Mount Parts Only)
SO-8
Units
˚C
˚C
mA
15
Single 8-Pin DIP
Single SO-8
IE
IO
VO
PO
Max.
125
85
20
Note
2
1, 3
5
3
40
7
VCC + 0.5
V
mW
V
V
5
50
7
85
mA
mA
V
mW
60
1
1
1
1, 4
260˚C for 10 sec., 1.6 mm below
seating plane
260˚C for 10 sec., up to seating
plane
See Package Outline Drawings
section
**Ratings apply to all devices except otherwise noted in the Package column.
Recommended Operating Conditions
Parameter
Input Current, Low Level
Input Current, High Level[1]
Power Supply Voltage
Low Level Enable Voltage
High Level Enable Voltage
Operating Temperature
Fan Out (at RL = 1 kΩ )[1]
Output Pull-up Resistor
Symbol
IFL*
IFH**
VCC
VEL
VEH
TA
N
RL
Min.
0
5
2.7
0
2.0
–40
330
Max.
250
15
3.3
0.8
VCC
85
5
4k
Units
µA
mA
V
V
V
˚C
TTL Loads
Ω
*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used
for best performance and to permit at least a 20% LED degradation guardband.
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Electrical Specifications
Over Recommended Temperature (T A = –40˚C to +85˚C) unless otherwise specified. All Typicals at V CC = 3.3 V,
TA = 25˚C. All enable test conditions apply to single channel products only. See Note 5.
Parameter
High Level Output Current
Sym.
IOH*
Input Threshold Current
Typ.
4.5
Max.
50
Units
µA
ITH
3.0
5.0
mA
Low Level Output Voltage
VOL*
0.35
0.6
V
High Level Supply Current
ICCH
4.7
7.0
mA
Low Level Supply Current
ICCL
7.0
10.0
mA
High Level Enable Current
Low Level Enable Current
High Level Enable Voltage
Low Level Enable Voltage
Input Forward Voltage
Input Reverse Breakdown
Voltage
Input Diode Temperature
Coefficient
IEH
IEL*
VEH
VEL
VF
BVR*
–0.5
–0.5
–1.2
–1.2
1.5
0.8
1.75*
mA
mA
V
V
V
V
Input Capacitance
CIN
∆V F/
∆T A
Min.
2.0
1.4
5
Test Conditions
V CC = 3.3 V, V E = 2.0 V,
VO = 3.3 V, IF = 250 µA
VCC = 3.3 V, V E = 2.0 V,
VO = 0.6 V,
IOL (Sinking) = 13 mA
VCC = 3.3 V, V E = 2.0 V,
IF = 5 mA,
IOL (Sinking) = 13 mA
VE = 0.5 V VCC = 3.3 V
IF = 0 mA
VE = 0.5 V VCC = 3.3 V
IF = 10 mA
VCC = 3.3 V, V E = 2.0 V
VCC = 3.3 V, V E = 0.5 V
Fig.
1
Note
1, 15
2
15
3
15
15
TA = 25˚C IF = 10 mA
IR = 10 µA
5
1
1
–1.6
mV˚C
IF = 10 mA
1
–1.9
60
pF
f = 1 MHz, VF = 0 V
1
*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.
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Switching Specifications
Over Recommended Temperature (T A = –40˚C to +85˚C), VCC = 3.3 V, I F = 7.5 mA unless otherwise specified. All Typicals
at TA = 25˚C, V CC = 3.3 V.
Parameter
Propagation Delay
Time to High Output
Level
Propagation Delay
Time to Low Output
Level
Pulse Width
Distortion
Propagation Delay
Skew
Output Rise Time
(10-90%)
Output Fall Time
(90-10%)
Propagation Delay
Time of Enable from
VEH tp VEL
Propagation Delay
Time of Enable from
VEL to VEH
Sym.
tPLH
Package** Min. Typ.
Max. Units
90
ns
Test Conditions
TA = 25˚C
RL = 350 Ω
CL = 15 pF
Fig.
Note
6, 7, 8 1, 6, 15
tPHL
75
ns
1, 7, 15
|tPHL – tPLH| 8-Pin DIP
SO-8
tPSK
25
ns
40
ns
8, 9, 15
8
9, 15
tr
45
ns
1, 15
tf
20
ns
1, 15
tELH
45
ns
tEHL
30
ns
RL = 350 Ω,
CL = 15 pF,
VEL = 0 V, V EH = 3 V
9
10
11
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter
Logic High
Common
Mode
Transient
Immunity
Logic Low
Common
Mode
Transient
Immunity
Sym.
|CMH|
|CML|
Device
Min. Typ.
Units Test Conditions
HCPL-263L 15,000 25,000 V/µs |VCM | = 10 V
VCC = 3.3 V, I F = 0 mA,
HCPL-063L
VO(MIN) = 2 V,
RL = 350 Ω, TA = 25˚C
HCPL-260L 15,000 25,000
|VCM | = 50 V
HCPL-060L
HCPL-263L 15,000 25,000 V/µs |VCM | = 10 V
VCC = 3.3 V, I F = 7.5 mA,
HCPL-063L
VO(MAX) = 0.8 V,
RL = 350 Ω, TA = 25˚C
|VCM| = 50 V
HCPL-260L 15,00 25,000
HCPL-060L
Fig.
11
Note
12, 14, 15
11
13, 14, 15
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Package Characteristics
All Typicals at T A = 25˚C.
Parameter
Sym. Package
Input-Output
I I-O*
Single 8-Pin DIP
Insulation
Single SO-8
Input-Output
VISO
8-Pin DIP, SO-8
Momentary
Withstand
Voltage**
Input-Output
RI-O
8-Pin, SO-8
Resistance
Input-Output
CI-O
8-Pin DIP, SO-8
Capacitance
Input-Input
II-I
Dual Channel
Insulation
Leakage
Current
Resistance
RI-I
Dual Channel
(Input-Input)
Capacitance
CI-I
Dual 8-Pin Dip
(Input-Input)
Dual SO-8
Min.
Typ.
Max
1
2500
Units
µA
V rms
Test Conditions
Fig. Note
45% RH, t = 5 s,
16, 17
VI-O = 3 kV DC, TA = 25˚C
RH ≤ 50%, t = 1 min,
16, 17
TA = 25˚C
1012
Ω
VI-O =500 V dc
1, 16, 19
0.6
pF
f = 1 MHz, TA = 25˚C
1, 16, 19
0.005
µA
RH ≤ 45%, t = 5 s,
VI-I = 500 V
20
1011
Ω
0.03
pG
20
f = 1 MHz
20
0.25
*The JEDEC Registration specifies 0˚C to +70˚C. Agilent specifies –40˚C to +85˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level
safety specification or Agilent Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
of the output pulse.
7. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
of the output pulse.
8. t PSK is equal to the worst case difference in t PHL and/or tPLH that will be seen between units at any given temperature and specified test
conditions.
9. See test circuit for measurement details.
10. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tELH enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. CM H is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
(i.e., V o > 2.0 V).
13. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., V o < 0.8 V).
14. For sinusoidal voltages, (|dVCM | / dt)max = πfCMVCM (p-p).
15. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
VDE 0884 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage
detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
VDE 0884 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
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VCC = 3.3 V
VO = 3.3 V
VE = 2.0 V*
IF = 250 µA
10
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
5
0
-60 -40 -20
0
20
40
60
80 100
8-PIN DIP, SO-8
12
10
VCC = 3.3 V
VO = 0.6 V
8
RL = 350 Ω
6
RL = 1 KΩ
4
2
RL = 4 KΩ
0
-60 -40 -20
TA – TEMPERATURE – °C
IF – FORWARD CURRENT – mA
IOL – LOW LEVEL OUTPUT CURRENT – mA
60
50
IF = 5.0 mA
40
20
40
10
0.1
0
-60 -40 -20
20
40
80 100
60
Figure 3. Typical low level output voltage vs.
temperature.
0.1
0.01
1.2
1.4
1.3
1.5
3.3 V
1
2
7
3
6
GND
0
TA – TEMPERATURE – °C
1.6
PULSE GEN.
ZO = 50 Ω
tf = tr = 5 ns
VCC 8
4
0.2
1.0
0.1 F
BYPASS
RL
IF
DUAL CHANNEL
3.3 V
1
VCC 8
2
7
3
6
RL
INPUT
MONITORING
NODE
OUTPUT V O
MONITORING
NODE
*CL
RM
IO = 13 mA
0.3
Figure 5. Typical input diode forward
characteristic.
SINGLE CHANNEL
INPUT
MONITORING
NODE
0.5
0.4
VF – FORWARD VOLTAGE – V
Figure 4. Typical low level output current vs.
temperature.
IF
0.6
IF
+
VF
–
TA – TEMPERATURE – °C
PULSE GEN.
ZO = 50 Ω
t f = t r = 5 ns
80 100
60
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
TA = 25 °C
100
0.001
1.1
80 100
60
40
0.7
VCC = 3.3 V
VE = 2.0 V*
IF = 5.0 mA
8-PIN DIP, SO-8
1000
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
0
20
Figure 2. Typical input threshold current vs.
temperature.
70
20
-60 -40 -20
0
8-PIN DIP, SO-8
0.8
TA – TEMPERATURE – °C
Figure 1. Typical high level output current vs.
temperature.
VCC = 3.3 V
VE = 2.0 V*
VOL = 0.6 V
VOL – LOW LEVEL OUTPUT VOLTAGE – V
ITH – INPUT THRESHOLD CURRENT – mA
IOH – HIGH LEVEL OUTPUT CURRENT – µA
15
RM
CL*
4
5
0.1 F
BYPASS
GND
5
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
IF = 7.50 mA
INPUT
IF
IF = 3.75 mA
tPHL
tPLH
OUTPUT
VO
1.5 V
Figure 6. Test circuit for t PHL and t PLH.
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OUTPUT V O
MONITORING
NODE
PWD – PULSE WIDTH DISTORTION – ns
tP – PROPAGATION DELAY – ns
150
VCC = 3.3 V
IF = 7.5 mA
120
tPLH , R L = 350 Ω
90
60
tPHL , R L = 350 Ω
30
0
-60 -40 -20
0
20
40
80 100
60
50
VCC = 3.3 V
IF = 7.5 mA
40
30
RL = 350 Ω
20
10
0
-60 -40 -20
TA – TEMPERATURE – °C
Figure 7. Typical propagation delay vs.
temperature.
PULSE GEN.
ZO = 50 Ω
tf = tr = 5 ns
0
20
40
60
80 100
TA – TEMPERATURE – °C
Figure 8. Typical pulse width distortion vs.
temperature.
INPUT V E
MONITORING NODE
+3.3 V
7.5 mA
IF
3.0 V
VCC 8
1
2
0.1 F
BYPASS
7
3
6
*CL
4
GND
INPUT
VE
RL
1.5 V
tEHL
OUTPUT V O
MONITORING
NODE
tELH
OUTPUT
VO
1.5 V
5
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
Figure 9. Test circuit for t EHL and tELH.
IF
SINGLE CHANNEL
IF
1
B
A
VFF
2
7
3
4
+3.3 V
0.1 F
BYPASS
VCC 8
1
A
RL
2
7
3
6
VFF
5
4
GND
VCM
VCM
–
+
PULSE
GENERATOR
ZO = 50 Ω
–
+
PULSE
GENERATOR
ZO = 50 Ω
VCM
VO
VO
VCM (PEAK)
0V
3.3 V
+3.3 V
RL
OUTPUT V O
MONITORING
NODE
6
GND
DUAL CHANNEL
B
VCC 8
SWITCH AT A: I F = 0 mA
OUTPUT V O
MONITORING
NODE
0.1 F
BYPASS
5
CMH
VO (MIN.)
SWITCH AT B: I F = 7.5 mA
VO (MAX.)
0.5 V
CML
Figure 10. Test circuit for common mode transient immunity and typical waveforms.
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GND BUS (BACK)
VCC BUS (FRONT)
NC
ENABLE
0.1 F
NC
OUTPUT
10 mm MAX.
(SEE NOTE 5)
SINGLE CHANNEL
DEVICE ILLUSTRATED.
Figure 11. Recommended printed circuit board layout.
SINGLE CHANNEL DEVICE
VCC1
3.3 V
3.3 V
8
VCC2
RL
220 Ω
IF
2
6
+
D1*
VF
–
GND 1
0.1 F
BYPASS
3
5
SHIELD
GND 2
VE 7
1
2
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
VCC1 3.3 V
3.3 V
8
VCC2
RL
220 Ω
IF
1
7
2
5
+
D1*
0.1 F
BYPASS
VF
–
GND 1
GND 2
SHIELD
1
2
Figure 12. Recommended LVTTL interface circuit.
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Application Information
Common-Mode Rejection for
HCPL-260L Families:
Figure 13 shows the recommended drive circuit for optimal
common-mode rejection
performance. Two main points to
note are:
1. The enable pin is tied to V CC
rather than floating (this
applies to single-channel parts
only).
2. Two LED-current setting
resistors are used instead of
one. This is to balance ILED
variation during commonmode transients.
If the enable pin is left floating, it
is possible for common-mode
transients to couple to the enable
pin, resulting in common-mode
failure. This failure mechanism
only occurs when the LED is on
and the output is in the Low
State. It is identified as occurring
when the transient output voltage
rises above 0.8 V. Therefore, the
enable pin should be connected
to either V CC or logic-level high
for best common-mode
performance with the output low
(CMRL ). This failure mechanism
is only present in single-channel
parts which have the enable
function.
Also, common-mode transients
can capacitively couple from the
LED anode (or cathode) to the
output-side ground causing
current to be shunted away from
the LED (which can be bad if the
LED is on) or conversely cause
current to be injected into the
LED (bad if the LED is meant to
be off). Figure 14 shows the
parasitic capacitances which
exists between LED
anode/cathode and output ground
(C LA and C LC). Also shown in
Figure 14 on the input side is an
AC-equivalent circuit.
*
HCPL-260L
1
VCC
8
VCC+
0.01 F
220 Ω
220 Ω
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
350 Ω
2
7
3
6
VO
5
GND
4
SHIELD
*
GND1
GND2
* HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
Figure 13. Recommended drive circuit for High-CMR.
1
8
2
7
1/2 RLED
VCC+
0.01 F
350 Ω
ILP
1/2 RLED
3
CLA
ILN
6
VO
15 pF
CLC
4
5
GND
SHIELD
.
+
–
VCM
Figure 14. AC equivalent circuit.
For transients occurring when the
LED is on, common-mode rejection (CMR L, since the output is in
the “low” state) depends upon the
amount of LED current drive (I F).
For conditions where IF is close
to the switching threshold (ITH),
CMRL also depends on the extent
which ILP and ILN balance each
other. In other words, any
condition where common-mode
transients cause a momentary
decrease in I F will cause
common-mode failure for
transients which are fast enough.
Likewise for common-mode
transients which occur when the
LED is off (i.e. CMR H, since the
output is “high”), if an imbalance
between ILP and ILN results in a
transient IF equal to or greater
than the switching threshold of
the optocoupler, the transient
“signal” may cause the output to
spike below 2 V (which constitutes a CMRH failure).
By using the recommended
circuit in Figure 13, good CMR
can be achieved. The balanced
ILED -setting resistors help equalize
ILP and ILN to reduce the amount
by which ILED is modulated from
transient coupling through C LA
and CLC
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CMR with Other Drive
Circuits
CMR performance with drive
circuits other than that shown in
Figure 13 may be enhanced by
following these guidelines:
1. Use of drive circuits where
current is shunted from the
LED in the LED off” state (as
shown in Figures 15 and 16).
This is beneficial for good
CMRH .
2. Use of I FH > 3.5 mA. This is
good for high CMRL.
VCC
HCPL-260L
420 Ω
(MAX)
2N3906
(ANY PNP)
74L504
(ANY
TTL/CMOS
GATE)
1
2
LED
3
”
Figure 15 shows a circuit which
can be used with any totem-poleoutput TTL/LSTTL/HCMOS logic
gate. The buffer PNP transistor
allows the circuit to be used with
logic devices which have low
current-sinking capability. It also
helps maintain the driving-gate
power-supply current at a
constant level to minimize ground
shifting for other devices
connected to the input-supply
ground.
When using an open-collector
TTL or open-drain CMOS logic
gate, the circuit in Figure 16 may
be used. When using a CMOS
gate to drive the optocoupler, the
circuit shown in Figure 17 may
be used. The diode in parallel
with the RLED speeds the turn-off
of the optocoupler LED.
4
Figure 15. TTL interface circuit.
VCC
HCPL-260L
1
R
2
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
LOGIC GATE)
LED
3
4
Figure 16. TTL open-collector/open drain gate drive circuit.
VCC
HCPL-260L
1N4148
1
2
220 Ω
74HC04
(OR ANY
TOTEM-POLE
OUTPUT LOGIC
GATE)
LED
3
4
Figure 17. CMOS gate drive circuit.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
5980-2523EN (11/00)
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