ASAHI KASEI [AK4556] AK4556 3V 192kHz 24Bit ∆Σ CODEC GENERAL DESCRIPTION The AK4556 is a low voltage 24bit 192kHz CODEC for high performance battery powered digital audio subsystems. The dynamic performance to power supply voltage ratio is very high, attaining 103dB and 106dB SNR for ADC and DAC, respectively. Sampling rates up to 216kHz are supported. The AK4556 reduces jitter sensitivity by using an integrated switched-capacitor filter. The analog inputs and outputs are single-ended to minimize pin count and external filtering requirements. Packaged in a very small 20-pin TSSOP, the AK4556 is ideal for space-sensitive applications. FEATURES Single-ended ADC - Dynamic Range, S/N: 103dB@VA=3.0V - S/(N+D): 91dB@VA=3.0V - HPF for DC-offset cancel (fc = 1Hz @ fs=48kHz) - HPF can be disabled Single-ended DAC - Dynamic Range, S/N: 106dB@VA=3.0V - S/(N+D): 90dB@VA=3.0V - Digital de-emphasis for 32kHz, 44.1kHz and 48kHz sampling Audio I/F format: MSB First, 2’s Complement - ADC: 24bit MSB justified or I2S compatible - DAC: 24bit MSB justified, 24bit LSB justified or I2S compatible Input/Output Voltage: ADC = 2.1Vpp @ VA=3.0V DAC = 2.1Vpp @ VA=3.0V Master/Slave mode Sampling Rate: - Normal Speed: 8kHz to 54kHz (256fs or 512fs) 8kHz to 48kHz (384fs or 768fs) - Double Speed: 54kHz to 108kHz (256fs) 48kHz to 96kHz (384fs) - Quad Speed: 108kHz to 216kHz (128fs) 96kHz to 192kHz (192fs) Master Clock: - Slave mode: 256fs, 384fs, 512fs or 768fs (Normal Speed) 256fs or 384fs (Double Speed) 128fs or 192fs (Quad Speed) - Master mode: 256fs or 512fs (Normal Speed) 256fs (Double Speed) 128fs (Quad Speed) Power Supply: 2.4 to 3.6V (Normal Speed, Double Speed) 2.7 to 3.6V (Quad Speed) Power Supply Current: 27.5mA Ta = -40 to 85°C Very Small Package: 20pin TSSOP Upper compatible with AK4552 MS0559-E-00 2006/11 -1- ASAHI KASEI [AK4556] VA LIN RIN VCOM VSS VD PDN ∆Σ Modulator Decimation Filter ∆Σ Modulator Decimation Filter Clock Divider MCLK LRCK BCLK Serial I/O Interface Common Voltage SDTO SDTI CKS3 LOUT ROUT LPF ∆Σ Modulator LPF ∆Σ Modulator 8X Interpolator CKS2 CKS1 CKS0 8X DEM0 Interpolator DEM1 Figure 1. Block Diagram Compatibility with the AK4552 1. Function Function fs (max) HFP Cut-off HPF Disable ADC Input Level Input Resistance Init Cycle S/(N+D) DR, S/N DF SA SB GD DAC Output Level Road Resistance S/(N+D) DR, S/N DF SA GD MCLK (Slave) Monitor Mode M/S mode Audio I/F ADC DAC Idd (Vdd = 3V) VDD Package AK4552 100kHz 3.7Hz @ fs = 48kHz No AK4556 216kHz 1Hz @ fs = 48kHz Yes 0.617 x VA 34kΩ @ fs = 44.1kHz, 24kΩ @ fs = 96kHz 2081/fs 89dB 97dB 65dB 29.4kHz 17/fs 0.7 x VA 8kΩ@ fs = 48kHz, 96kHz, 192kHz 4134/fs @ Normal Speed, Slave mode 91dB 103dB 68dB 28kHz 18/fs 0.583 x VA 10kΩ 88dB 100dB 43dB 15.4/fs 256/384/512/768fs @ Normal Speed mode 256/384fs @ Double Speed Mode 128/192fs @ Double Speed Monitor 64/96/128/192fs @ Quad Speed Monitor Yes (Double / Quad) Slave 24bit MSB justified 24bit LSB justified 14mA 2.4V to 4.0V 0.7 x VA 5kΩ 90dB 106dB 54dB 21/fs 256/384/512/768fs @ Normal Speed 16TSSOP (5.0mm x 6.4mm, 0.65mm Pitch) MS0559-E-00 256/384fs @ Double Speed 128/192fs @ Quad Speed No Master / Slave 24bit MSB justified / I2S 24bit MSB justified /24bit LSB justified / I2S 27.5mA 2.4V to 3.6V (Normal/Double Speed) 2.7V to 3.6V (Quad Speed) 20TSSOP (6.5mm x 6.4mm, 0.65mm Pitch) 2006/11 -2- ASAHI KASEI [AK4556] 2. Pin Layout RIN 1 20 ROUT LIN 2 19 LOUT VSS 3 18 VCOM VA 4 17 PDN VD 5 16 BCLK DEM0 6 15 MCLK DEM1 7 14 LRCK SDTO 8 13 SDTI CKS0 9 12 CKS3 CSK1 10 11 CSK2 AK4552 Top View MS0559-E-00 AK4556 2006/11 -3- ASAHI KASEI [AK4556] Ordering Guide AK4556VT AKD4556 -40 ∼ +85°C 20pin TSSOP (0.65mm pitch) Evaluation Board for AK4556 Pin Layout RIN 1 20 ROUT LIN 2 19 LOUT VSS 3 18 VCOM VA 4 17 PDN VD 5 16 BCLK DEM0 6 15 MCLK DEM1 7 14 LRCK SDTO 8 13 SDTI CKS0 9 12 CKS3 CSK1 10 11 CSK2 Top View MS0559-E-00 2006/11 -4- ASAHI KASEI [AK4556] PIN/FUNCTION No. Pin Name I/O 1 2 3 4 5 6 7 RIN LIN VSS VA VD DEM0 DEM1 I I I I 8 SDTO O 9 10 11 12 13 CKS0 CSK1 CSK2 CSK3 SDTI I I I I I Function Rch Analog Input Pin Lch Analog Input Pin Ground Pin Analog Power Supply Pin Digital Power Supply Pin De-emphasis Control Pin De-emphasis Control Pin Audio Serial Data Output Pin When PDN pin is “L”, SDTO pin outputs “L”. Mode Setting Pin #0 Mode Setting Pin #1 Mode Setting Pin #2 Mode Setting Pin #3 Audio Serial Data Input Pin Input/Output Channel Clock Pin 14 LRCK I/O When PDN pin is “L”, LRCK pin outputs “L” in master mode. 15 MCLK I Master Clock Input Pin Audio Serial Data Clock Pin 16 BCLK I/O When PDN pin is “L”, BCLK pin outputs “L” in master mode. Power-Down & Reset Mode Pin 17 PDN I “L”: Power-down and Reset, “H”: Normal operation The AK4556 should be reset once by bringing PDN pin = “L”. 18 VCOM O Common Voltage Output Pin, 0.5 x VA Lch Analog Output Pin 19 LOUT O When PDN pin is “L”, LOUT pin becomes Hi-Z. Rch Analog Output Pin 20 ROUT O When PDN pin is “L”, ROUT pin becomes Hi-Z. Note: Do not allow digital input pins except analog input pins (LIN and RIN) to float. Handling of Unused Pin The unused I/O pin should be processed appropriately as below. Classification Analog Input Analog Output Pin Name LIN, RIN LOUT, ROUT Setting These pins should be open. These pins should be open. MS0559-E-00 2006/11 -5- ASAHI KASEI [AK4556] ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Power Supplies Analog Digital Input Current (Any Pin Except Supplies) Analog Input Voltage (LIN, RIN pin) Digital Input Voltage (Note 2) Ambient Temperature (power applied) Storage Temperature Symbol VA VD IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -40 -65 max 4.6 4.6 ±10 VA+0.3 VD+0.3 85 150 Units V V mA V V °C °C Note 1. All voltages with respect to ground. Note 2. DEM1, DEM0, CKS3, CKS2, CKS1, CKS0, SDTI, LRCK, BCLK, MCLK and PDN pins WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (Normal/Double Speed) (VSS=0V; Note 1) Parameter Symbol min typ max Power Supplies (Note 3) Analog VA 2.4 3.0 3.6 Digital VD 2.4 3.0 3.6 Difference VD - VA 0.3 Units V V V RECOMMENDED OPERATING CONDITIONS (Quad Speed) (VSS=0V; Note 1) Parameter Power Supplies (Note 3) Analog Digital Difference Symbol VA VD VD - VA min 2.7 2.7 - typ 3.0 3.0 - max 3.6 3.6 0.3 Units V V V Note 1. All voltages with respect to ground. Note 3. The power up sequence between VA and VD is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this data sheet. MS0559-E-00 2006/11 -6- ASAHI KASEI [AK4556] ANALOG CHARACTERISTICS (Ta=25°C; VA=VD=3.0V; VSS=0V; fs=48kHz, 96kHz, 192kHz; Signal Frequency=1kHz; BCLK=64fs; Data=24bit Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Resolution 24 Bits Input Voltage (Note 4) 1.9 2.1 2.3 Vpp S/(N+D) fs=48kHz −1dBFS 82 91 dB BW=20kHz −60dBFS 40 dB fs=96kHz −1dBFS 80 90 dB BW=40kHz −60dBFS 37 dB fs=192kHz −1dBFS 90 dB BW=40kHz −60dBFS 37 dB DR (−60dBFS with A-weighted) 95 103 dB S/N (A-weighted) 95 103 dB Input Resistance 6 8 kΩ Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 100 ppm/°C Power Supply Rejection (Note 8) 50 dB DAC Analog Output Characteristics: Resolution 24 Bits Output Voltage (Note 5) 1.9 2.1 2.3 Vpp S/(N+D) fs=48kHz 0dBFS 80 90 dB BW=20kHz −60dBFS 43 dB fs=96kHz 0dBFS 78 88 dB BW=40kHz −60dBFS 40 dB fs=192kHz 0dBFS 88 dB BW=40kHz −60dBFS 40 dB DR (−60dBFS with A-weighted) 98 106 dB S/N (A-weighted) 98 106 dB Load Capacitance (Note 6) 30 pF Load Resistance (Note 7) 5 kΩ Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 100 ppm/°C Power Supply Rejection (Note 8) 50 dB Note 4. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage. Vin = 0.7 x VA (Vpp). Note 5. This value is the full scale (0dB) of the output voltage. Output voltage is proportional to VA voltage. Vout = 0.7 x VA (Vpp). Note 6. When LOUT/ROUT drives some capacitive load, a 220Ω resistor should be added in series between LOUT/ROUT and capacitive load. In this case, LOUT/ROUT pins can drive a capacitor of 400pF. Note 7. For AC-load Note 8. PSR is applied to VA and VD with 1kHz, 50mVpp. VCOM pin is connected to a 2.2µF electrolytic capacitor and a 0.1µF ceramic capacitor. MS0559-E-00 2006/11 -7- ASAHI KASEI [AK4556] Parameter min typ max Units - 19.5 8 11 14 29 12 17 21 mA mA mA mA - 10 100 µA Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) VA VD fs=48kHz (Note 9) fs=96kHz fs=192kHz Power down mode (PDN pin = “L”) VA+VD (Note 10) Note 9. These values are in slave mode. In master mode, these values are 8.3mA (typ.) @ fs=48kHz, 11.6mA (typ.) @ fs=96kHz, 15.2mA (typ.) @ fs=192kHz. Note 10. All digital input pins are held VD or VSS. FILTER CHARACTERISTICS (fs=48kHz) (Ta= -40 ∼ +85°C; VA, VD=2.4∼ 3.6V; DEM=OFF) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 11) ±0.1dB PB 0 −0.2dB 20.0 −3.0dB 23.0 Stopband (Note 11) SB 28 Passband Ripple PR Stopband Attenuation SA 68 Group Delay Distortion ∆GD 0 Group Delay (Note 12) GD 18 ADC Digital Filter (HPF): Frequency Response (Note 11) −3dB FR 1.0 −0.1dB 6.5 DAC Digital Filter (LPF): Passband (Note 11) ±0.06dB PB 0 −6.0dB 24.0 Stopband (Note 11) SB 26.2 Passband Ripple PR Stopband Attenuation SA 54 Group Delay Distortion ∆GD 0 Group Delay (Note 12) GD 21 DAC Digital Filter + Analog Filter: Frequency Response (Note 13) 20kHz FR -0.1 MS0559-E-00 max Units 18.9 ±0.04 - kHz kHz kHz kHz dB dB µs 1/fs - Hz Hz 21.8 ±0.02 - kHz kHz kHz dB dB µs 1/fs - dB 2006/11 -8- ASAHI KASEI [AK4556] FILTER CHARACTERISTICS (fs=96kHz) (Ta= -40 ∼ +85°C; VA, VD=2.4∼ 3.6V; DEM=OFF) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 11) ±0.1dB PB 0 −0.2dB 40.0 −3.0dB 46.0 Stopband (Note 11) SB 56 Passband Ripple PR Stopband Attenuation SA 68 Group Delay Distortion ∆GD 0 Group Delay (Note 12) GD 18 ADC Digital Filter (HPF): Frequency Response (Note 11) −3dB FR 2.0 −0.1dB 13.0 DAC Digital Filter (LPF): Passband (Note 11) ±0.06dB PB 0 −6.0dB 48.0 Stopband (Note 11) SB 52.4 Passband Ripple PR Stopband Attenuation SA 54 Group Delay Distortion ∆GD 0 Group Delay (Note 12) GD 21 DAC Digital Filter + Analog Filter: Frequency Response (Note 13) 40kHz FR -0.3 FILTER CHARACTERISTICS (fs=192kHz) (Ta= -40 ∼ +85°C; VA, VD=2.7∼ 3.6V; DEM=OFF) Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 11) ±0.1dB PB 0 −0.2dB 57.0 −3.0dB 90.3 Stopband (Note 11) SB 112 Passband Ripple PR Stopband Attenuation SA 70 Group Delay Distortion ∆GD 0 Group Delay (Note 12) GD 18 ADC Digital Filter (HPF): Frequency Response (Note 11) −3dB FR 4.0 −0.1dB 26.0 DAC Digital Filter (LPF): Passband (Note 11) ±0.5dB PB 0 −6.0dB 96.0 Stopband (Note 11) SB 104.9 Passband Ripple PR Stopband Attenuation SA 54 Group Delay Distortion ∆GD 0 Group Delay (Note 12) GD 21 DAC Digital Filter + Analog Filter: Frequency Response (Note 13) 40kHz FR -0.3 MS0559-E-00 max Units 37.8 ±0.04 - kHz kHz kHz kHz dB dB µs 1/fs - Hz Hz 43.6 ±0.02 - kHz kHz kHz dB dB µs 1/fs - dB max Units 56.6 ±0.02 - kHz kHz kHz kHz dB dB µs 1/fs - Hz Hz 87.0 ±0.02 - kHz kHz kHz dB dB µs 1/fs - dB 2006/11 -9- ASAHI KASEI [AK4556] Note 11. The passband and stopband frequencies scales with fs (sampling frequency). For example, ADC: Passband (±0.1dB) = 0.39375 x fs (@ fs=48kHz), DAC: Passband (±0.06dB) = 0.45412 x fs. Note 12. The calculated delay time resulting from digital filtering. For the ADC, this time is from the input of an analog signal to the setting of 24bit data for both channels to the ADC output register. For the DAC, this time is from setting the 24 bit data both channels at the input register to the output of an analog signal. Note 13. The reference frequency is 1kHz. DC CHARACTERISTICS (Ta=-40 ∼ +85°C; VA, VD=2.4 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-100µA) Low-Level Output Voltage (Iout=100µA) Input Leakage Current Symbol VIH VIL VOH VOL Iin MS0559-E-00 min 70%VD VD-0.5 - typ - max 30%VD 0.5 ± 10 Units V V V V µA 2006/11 - 10 - ASAHI KASEI [AK4556] SWITCHING CHARACTERISTICS (Ta=-40 ∼ +85°C; VA, VD=2.4 ∼ 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing (MCLK) Frequency: 128fs, 256fs, 512fs fCLK 2.048 192fs, 384fs, 768fs fCLK 3.072 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK (VA, VD = 2.4V∼3.6V) Normal Speed: 256fs, 512fs Frequency 384fs, 768fs Double Speed: 256fs 384fs Duty Cycle Slave mode Master mode LRCK (VA, VD = 2.7V∼3.6V) Frequency Quad Speed: 128fs 192fs Duty Cycle Slave mode Master mode Audio Interface Timing Slave mode (VA, VD = 2.4V ∼ 2.7V) BCLK Period: Normal Speed Double Speed BCLK Pulse Width Low Pulse Width High LRCK Edge to BCLK “↑” (Note 14) BCLK “↑” to LRCK Edge (Note 14) LRCK to SDTO (MSB) (Except I2S mode) BCLK “↓” to SDTO SDTI Hold Time SDTI Setup Time Slave mode (VA, VD = 2.7V ∼ 3.6V) BCLK Period: Normal Speed Double / Quad Speed BCLK Pulse Width Low Pulse Width High LRCK Edge to BCLK “↑” (Note 14) BCLK “↑” to LRCK Edge (Note 14) LRCK to SDTO (MSB) (Except I2S mode) BCLK “↓” to SDTO SDTI Hold Time SDTI Setup Time typ max Units - 27.648 36.864 - MHz MHz ns ns fs fs fs fs 8 8 54 48 45 - 50 54 48 108 96 55 - kHz kHz kHz kHz % % fs fs 108 96 45 - 50 216 192 55 - kHz kHz % % tBCK tBCK tBCKL tBCKH tLRB tBLR tDLR tBSD tSDH tSDS 1/128fs 1/64fs 60 60 20 20 20 20 - 40 40 - ns ns ns ns ns ns ns ns ns ns tBCK tBCK tBCKL tBCKH tLRB tBLR tDLR tBSD tSDH tSDS 1/128fs 1/64fs 33 33 20 20 13 13 - 20 20 - ns ns ns ns ns ns ns ns ns ns Note 14. BCLK rising edge must not occur at the same time as LRCK edge. MS0559-E-00 2006/11 - 11 - ASAHI KASEI [AK4556] SWITCHING CHARACTERISTICS (Continued) (Ta=-40 ∼ +85°C; VA, VD=2.4 ∼ 3.6V; CL=20pF) Parameter Symbol min typ Master mode (VA, VD = 2.4V ∼ 2.7V) BCLK Frequency fBCK 64fs BCLK Duty dBCK 50 BCLK “↓” to LRCK tMBLR −20 BCLK “↓” to SDTO tBSD −20 SDTI Hold Time tSDH 20 SDTI Setup Time tSDS 20 Master mode (VA, VD = 2.7V ∼ 3.6V) BCLK Frequency fBCK 64fs BCLK Duty dBCK 50 BCLK “↓” to LRCK tMBLR −20 BCLK “↓” to SDTO tBSD −20 SDTI Hold Time tSDH 13 SDTI Setup Time tSDS 13 Reset Timing PDN Pulse Width (Note 15) PDN “↑” to SDTO valid (Note 16) Slave Mode Noraml Speed Double Speed Quad Speed Master Mode Normal Speed Double Speed Quad Speed max Units 40 40 - Hz % ns ns ns ns 20 20 - Hz % ns ns ns ns tPW 150 - - ns tPWV tPWV tPWV tPWV tPWV tPWV - 4134 8262 16518 4131 8259 16515 - 1/fs 1/fs 1/fs 1/fs 1/fs 1/fs Note 15. The AK4556 can be reset by bringing the PDN pin = “L”. Note 16. This cycle is the number of LRCK rising edges from the PDN pin = “H”. Timing Diagram 1/fCLK VIH VIL MCLK tCLKH tCLKL 1/fs VIH VIL LRCK tBCK VIH VIL BCLK tBCKH tBCKL Figure 2. Clock Timing MS0559-E-00 2006/11 - 12 - ASAHI KASEI [AK4556] VIH VIL LRCK tBLR tLRB VIH VIL BCLK tDLR tDBS 50%VD SDTO tSDS tSDH VIH VIL SDTI Figure 3. Audio Data Input/Output Timing (Slave) LRCK 50%VD tLRB BCLK 50%VD tDLR tBSD 50%VD SDTO tSDS tSDH VIH VIL SDTI Figure 4. Audio Data Input/Output Timing (Master) tPW PDN VIL tPWV SDTO 50%VD Figure 5. Reset Timing MS0559-E-00 2006/11 - 13 - ASAHI KASEI [AK4556] OPERATION OVERVIEW System Clock MCLK, BCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. MCLK frequency, BCLK frequency, HPF (ON or OFF) and master/slave are selected by CKS3-0 pins as shown in Table 3. When MCLK is 192fs, 384fs or 768fs, the sampling frequency does not support variable pitch (Table 2). All external clocks (MCLK, BCLK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not provided, the AK4556 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4556 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless the PDN pin = “L”. fs 32kHz 44.1kHz 48kHz 96kHz 192kHz 128fs N/A N/A N/A N/A 24.576MHz MCLK 192fs 256fs 384fs 512fs N/A 8.192MHz 12.288MHz 16.384MHz N/A 11.2896MHz 16.9344MHz 22.5792MHz N/A 12.288MHz 18.432MHz 24.576MHz N/A 24.576MHz 36.864MHz N/A 36.864MHz N/A N/A N/A Table 1. System Clock Example (N/A: Not Available) 768fs 24.576MHz 33.8688MHz 36.864MHz N/A N/A Mode Sampling Frequency MCLK 256fs/512fs 8kHz ≤ fs ≤ 54kHz Normal Speed 384fs/768fs 8kHz ≤ fs ≤ 48kkHz 256fs 54kHz < fs ≤ 108kHz Double Speed 384fs 48kHz < fs ≤ 96kHz 128fs 108kHz < fs ≤ 216kHz Quad Speed 192fs 96kHz < fs ≤ 192kHz Table 2. Sampling Frequency Range MS0559-E-00 2006/11 - 14 - ASAHI KASEI [AK4556] Mode CKS3 pin CKS2 pin CKS1 pin CKS0 pin HPF M/S 0 (*) L L L L ON Slave 1 L L L H ON Slave 2 L L H L OFF Slave 3 L L H H OFF Slave 4 L H L L ON Slave 5 L H L H ON Slave 6 L H H L OFF Slave 7 L H H H OFF Slave 8 H L L L ON Slave 9 H L L H ON Slave 10 H L H L OFF Slave 11 H L H H OFF Slave 12 H H L 13 H H L 14 H H H 15 H H H * AK4552 Compatible mode L H L H ON ON ON ON Master Master Master Master MCLK 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 128/192fs (Quad Speed) 256/384fs (Double Speed) 512/768fs (Normal Speed) 256/384/512/768fs (Normal Speed) 256fs (Double Speed) 512fs (Normal Speed) 128fs (Quad Speed) 256fs (Normal Speed) Audio Interface Format (See Table 4) LJ/RJ LJ/RJ LJ/RJ LJ/RJ I 2S I 2S I 2S I 2S LJ LJ LJ LJ I 2S I 2S I 2S I 2S Table 3. Mode Setting Audio Serial Interface Format Three modes are supported and selected by the CKS3-0 pins as shown in Table 3 and Table 4. In all modes the serial data format is MSB first, 2’s complement. The SDTO is clocked out on the falling edge of BCLK and the SDTI is latched on the rising edge. The audio interface supports both master and slave modes. In slave mode, BCLK and LRCK are input. In master mode, BCLK and LRCK are output with the BCLK frequency fixed to 64fs and the LRCK frequency fixed to 1fs. Also audio interface format is fixed to I2S mode. Mode LJ I2S LJ/RJ SDTO 24bit, MSB justified 24bit, I2S Compatible 24bit, MSB justified SDTI LRCK 24bit, MSB justified H/L 24bit, I2S Compatible L/H 24bit, LSB justified H/L Table 4. Audio Interface Format MS0559-E-00 BCLK (Slave) ≥ 48fs ≥ 48fs or 32fs ≥ 48fs BCLK (Master) 64fs - 2006/11 - 15 - ASAHI KASEI [AK4556] LRCK 0 1 2 18 19 20 21 22 23 24 25 0 1 2 18 19 20 21 22 23 24 25 0 1 BCLK(64fs) SDTO(o) 23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 SDTI(i) 23 22 5 4 3 2 1 0 Don’t Care 23 22 5 4 3 2 1 0 Don’t Care 23:MSB, 0:LSB Lch Data 23 Rch Data Figure 6. Mode LJ Timing LRCK 0 1 2 3 19 20 21 22 23 24 25 0 1 2 3 19 20 21 22 23 24 25 0 1 BCLK(64fs) SDTO(o) 23 22 5 4 3 2 1 0 23 22 5 4 3 2 1 0 SDTI(i) 23 22 5 4 3 2 1 0 Don’t Care 23 22 5 4 3 2 1 0 Don’t Care 23:MSB, 0:LSB Lch Data Rch Data 2 Figure 7. Mode I S Timing LRCK 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 1 BCLK(64fs) SDTO(o) SDTI(i) 23 22 16 15 14 Don’t Care 23:MSB, 0:LSB 0 23 22 12 11 23 22 1 0 16 15 14 Don’t Care Lch Data 23 22 0 12 11 23 1 0 Rch Data Figure 8. Mode LJ/RJ Timing De-emphasis Filter The DAC includes a digital de-emphasis filter (tc=50/15µs) via an integrated by IIR filter. This filter corresponds to three frequencies (32kHz, 44.1kHz, 48kHz). This setting is done by DEM0 and DEM1 pins. This filter is always OFF in double and quad speed modes. DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz Table 5. De-emphasis filter control MS0559-E-00 2006/11 - 16 - ASAHI KASEI [AK4556] Digital High Pass Filter The ADC has a Digital High Pass Filter (HPF) for DC-offset cancellation. The cut-off frequency of the HPF is 1Hz at fs=48kHz and the frequency response at 20Hz is -0.12dB. It also scales with the sampling frequency (fs). The HPF is controlled by CKS3-0 pins (Table 3). If the HPF setting (ON/OFF) is changed at operating, click noise occurs by changing DC offset. Power-down & Reset The ADC and DAC are placed in power-down mode by bringing the PDN pin = “L”, and each digital filter is also reset at the same time. These resets should always be done after power-up. For the ADC, an analog initialization cycle starts after exiting the power-down mode. The output data, (SDTO) becomes available after 4131 cycles (@ Normal Speed) of LRCK in master mode or 4134 cycles (@ Normal Speed) of LRCK in slave mode. During initialization, the ADC digital data outputs of both channels are forced to a 2’s complement “0”. The ADC output data settles and correlates to the input signal after the end of initialization (settling time is approximately equal to the group delay time.) The initialization cycle does not affect the DAC operation. PDN (1) ADC Internal State Normal Operation DAC Internal State Normal Operation Power-down Init Cycle Normal Operation Normal Operation Power-down GD GD ADC In (Analog) ADC Out (Digital) “0”data Idle Noise DAC In (Digital) “0”data GD DAC Out (Analog) Clock In MCLK,LRCK,BCLK Idle Noise GD (2) (2) (3) (4) The clocks may be stopped. External Mute Mute ON Notes: (1) Slave mode (typ): 4134/fs @ Normal Speed, 8262/fs @ Double Speed, 16518/fs @ Quad Speed Master mode (typ): 4131/fs @ Normal Speed, 8259/fs @ Double Speed, 16515/fs @ Quad Speed (2) Click noise occurs at the “↑↓” of PDN signal. Mute the analog output externally if the click noise influences system performance. (3) LOUT/ROUT pins become Hi-Z at power-down. (4) In master mode, LRCK and BICK output “L” at power-down. Figure 9. Power-up/down Sequence MS0559-E-00 2006/11 - 17 - ASAHI KASEI [AK4556] System Reset The AK4556 should be reset once by bringing the PDN pin “L” after power-up. In slave mode, reset and power down states are released by MCLK and the internal timing starts clocking on the rising edge of LRCK in Mode LJ and Mode LJ/RJ. In Mode I2S, it starts clocking on the falling edge of BCLK after the first rising edge of BCLK after the falling edge of LRCK. The AK4556 is in power down state until LRCK is input. In master mode, reset and power down states are released by MCLK. The internal timing also starts by MCLK. MS0559-E-00 2006/11 - 18 - ASAHI KASEI [AK4556] SYSTEM DESIGN Figure 10 shows the system connection diagram. An evaluation board [AKD4556] is available which demonstrates application circuit, optimum layout, power supply arrangements and measurement results. 10u 10u 10u 0.1u Analog Supply (3.0V) + + 5.1 ohm Mode Control 1 RIN ROUT 20 2 LIN LOUT 19 3 VSS VCOM 18 4 VA 5 VD AK4556 + 2.2u 0.1u Reset PDN 17 BCLK 16 10u 0.1u 6 DEM0 MCLK 15 7 DEM1 LRCK 14 8 SDTO SDTI 13 9 CKS0 CKS3 12 10 CKS1 CKS2 11 Audio Controller Figure 10. System Connection Diagram Example (Mode 0: AK4552 Compatible Mode) Notes: - VSS of the AK4556 should be distributed separately from the ground external digital devices. - Do not allow digital input pins to float. - When LOUT/ROUT drives some capacitive load, a 220Ω resistor should be added in series between LOUT/ROUT and capacitive load. In this case, LOUT/ROUT pins can drive capacitor of 400pF. MS0559-E-00 2006/11 - 19 - ASAHI KASEI [AK4556] 1. Grounding and Power Supply Decoupling The AK4556 requires careful attention to power supply and grounding arrangements. VA pin is usually supplied from analog supply in system and VD pin is supplied from VA pin via 5.1Ω. Alternatively if VA and VD pins are supplied separately, the power up sequence is not critical. VSS pin of the AK4556 should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4556 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference The input to VA voltage sets the analog input/output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor are connected to VA and VSS pins, normally. VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from the VA, VD and VCOM pins in order to avoid unwanted coupling into the AK4556. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 8kΩ (typ, @fs=48kHz, 96kHz, 192kHz) resistance. The input signal range scales with the supply voltage and nominally 0.7xVA Vpp (typ). The ADC output data format is 2’s complement. The internal HPF removes the DC offset. The AK4556 samples the analog inputs at 128fs (@ fs=48kHz), 64fs (@fs=96kHz) or 32fs(@192kHz). The digital filter rejects noise above the stop band except for multiples of the sampling frequency of analog inputs. The AK4556 includes an anti-aliasing filter (RC filter) to attenuate a noise around the sampling frequency of analog inputs. 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.7 x VA Vpp (typ). The DAC input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). If the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. MS0559-E-00 2006/11 - 20 - ASAHI KASEI [AK4556] PACKAGE 6.5 ± 0.1 11 1 10 0.105 ~ 0.175 0.10 0.65 6.4 ± 0.2 4.4 ± 0.1 0.60 ± 0.10 20 M 0o ~ 8o 0.195 ~ 0.275 0.10 S 1.20MAX 0.10 ± 0.05 1.00 ± 0.05 S Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0559-E-00 2006/11 - 21 - AKM CONFIDENTIAL ASAHI KASEI [AK4556] MARKING AKM 4556VT XXXXXX 1) Pin #1 indication 2) Date Code: XXXXXX (6 digits) 3) Marketing Code: 4556VT Revision History Date (YY/MM/DD) 06/11/06 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Rev.0.4 2005/12 - 22 -