CY62146E MoBL® 4-Mbit (256K x 16) Static RAM Features device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: • Deselected (CE HIGH) • Outputs are disabled (OE HIGH) • Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) • When the write operation is active (CE LOW and WE LOW) • Very high speed: 45 ns • Wide voltage range: 4.5V–5.5V • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 7 µA • Ultra low active power • • • • — Typical active current: 2 mA @ f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 44-pin TSOP II package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). Functional Description[1] To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes. The CY62146E is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 256K x 16 RAM Array IO0–IO7 IO8–IO15 BHE WE CE OE BLE A17 A16 A15 A13 A14 A11 A12 COLUMN DECODER Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 001-07970 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 4, 2007 [+] Feedback CY62146E MoBL® Pin Configurations The figure that follows shows the 44-Pin TSOP II pinout.[2] Top View A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12 Product Portfolio Power Dissipation Product Range Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62146ELL Ind’l/Auto-A Min Typ[3] Max 4.5 5.0 5.5 45 ns f = fmax Standby ISB2 (µA) Typ[3] Max Typ[3] Max Typ[3] Max 2 2.5 15 20 1 7 Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°. Document #: 001-07970 Rev. *C Page 2 of 11 [+] Feedback CY62146E MoBL® DC Input Voltage[4, 5] ............... –0.5V to 6V (VCC max + 0.5V) Maximum Ratings Exceeding maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Ambient Temperature with Power Applied ........................................... –55°C to + 125°C Supply Voltage to Ground Potential ............................... –0.5V to + 6V (VCCmax + 0.5V) DC Voltage Applied to Outputs in High-Z State[4, 5] ....................–0.5V to 6V (VCCmax + 0.5V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Operating Range Device Range CY62146ELL Ind’l/Auto-A Ambient Temperature VCC[6] –40°C to +85°C 4.5V to 5.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –1.0 mA VOL Output LOW Voltage IOL = 2.1 mA VIH Input HIGH Voltage VCC = 4.5V to 5.5V VIL Input LOW Voltage VCC = 4.5V to 5.5V IIX Input Leakage Current IOZ Output Leakage Current ICC VCC Operating Supply Current f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels Automatic CE Power Down Current – CMOS Inputs ISB2[7] 45 ns (Ind’l/Auto-A) Min Typ [3] Unit Max 2.4 V 0.4 V 2.2 VCC + 0.3 V –0.5 0.8 V GND < VI < VCC –1 +1 µA GND < VO < VCC, Output Disabled –1 +1 µA 15 20 mA 2 2.5 1 7 CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max) µA Capacitance For all packages. Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF TSOP II Package Unit 77 °C/W 13 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (junction to ambient) ΘJC Thermal Resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit board Notes 4. VIL(min) = –2.0V for pulse durations less than 20 ns for I < 30 mA. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full device AC operations are based on a minimum of 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-07970 Rev. *C Page 3 of 11 [+] Feedback CY62146E MoBL® AC Test Loads and Waveforms Figure 1. AC Test Load and Waveforms R1 VCC OUTPUT 3V 30 pF INCLUDING JIG AND SCOPE 10% GND RISE TIME= 1 V/ns R2 ALL INPUT PULSES 90% 90% 10% FALL TIME= 1 V/ns EQUIVALENT TO: THEVENIN EQUIVALENT RTH OUTPUT V Parameters 5.0V Unit R1 1800 Ω R2 990 Ω RTH 639 Ω VTH 1.77 V Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR [7] Data Retention Current tCDR [8] Chip Deselect to Data Retention Time tR [9] Operation Recovery Time Conditions Typ [3] Min Max 2 VCC = 2V, CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Unit V Ind’l/Auto-A 1 7 µA 0 ns tRC ns Data Retention Waveform[10] Figure 2. Data Retention Waveform DATA RETENTION MODE VCC CE or VCC(min) tCDR VDR > 2.0V VCC(min) tR BHE.BLE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 10. BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE. Document #: 001-07970 Rev. *C Page 4 of 11 [+] Feedback CY62146E MoBL® Switching Characteristics Over the Operating Range [11, 12] Parameter Description 45 ns (Ind’l/Auto-A) Min Max Unit Read Cycle tRC Read Cycle Time 45 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns 45 10 ns ns OE LOW to Low-Z[13] OE HIGH to High-Z[13, 14] CE LOW to Low-Z[13] tHZCE CE HIGH to High-Z[13, 14] tPU CE LOW to Power Up tPD CE HIGH to Power Down 45 ns tDBE BLE/BHE LOW to Data Valid 22 ns tLZOE tHZOE tLZCE tLZBE tHZBE Write BLE/BHE LOW to Low[13] BLE/BHE HIGH to High-Z[13, 14] 5 ns 18 10 ns ns 18 0 ns ns 5 ns 18 ns Cycle[15] tWC Write Cycle Time 45 ns tSCE CE LOW to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tBW BLE/BHE LOW to Write End 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High-Z[13, 14] [13] WE HIGH to Low-Z 18 10 ns ns Notes 11. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 3 ns (1V/ns) or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedence state. 15. The internal memory write time is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 001-07970 Rev. *C Page 5 of 11 [+] Feedback CY62146E MoBL® Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[16, 17] Figure 3. Read Cycle No. 1 tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[17, 18] Figure 4. Read Cycle No. 2 ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 16. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE and BHE, BLE transition LOW. Document #: 001-07970 Rev. *C Page 6 of 11 [+] Feedback CY62146E MoBL® Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[15, 19, 20] Figure 5. Write Cycle No. 1 tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA IO tSD NOTE 21 tHD DATAIN tHZOE Write Cycle No. 2 (CE Controlled)[15, 19, 20] Figure 6. Write Cycle No. 2 tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD DATAIN NOTE 21 tHZOE Notes 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 21. During this period, the IOs are in output state. Do not apply input signals. Document #: 001-07970 Rev. *C Page 7 of 11 [+] Feedback CY62146E MoBL® Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[20] Figure 7. Write Cycle No. 3 tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA IO NOTE 21 tHD DATAIN tLZWE tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20] Figure 8. Write Cycle No. 4 tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA IO NOTE 21 tSD tHD DATAIN tLZWE Document #: 001-07970 Rev. *C Page 8 of 11 [+] Feedback CY62146E MoBL® Truth Table Inputs Outputs Mode Power CE WE OE BHE BLE H X X X X High-Z Deselect/Power Down Standby (ISB) L X X H H High-Z Output Disabled Active (ICC) L H L L L Data Out (IO0–IO15) Read Active (ICC) L H L H L Data Out (IO0–IO7); IO8–IO15 in High-Z Read Active (ICC) L H L L H Data Out (IO8–IO15); IO0–IO7 in High-Z Read Active (ICC) L H H L L High-Z Output Disabled Active (ICC) L H H H L High-Z Output Disabled Active (ICC) L H H L H High-Z Output Disabled Active (ICC) L L X L L Data In (IO0–IO15) Write Active (ICC) L L X H L Data In (IO0–IO7); IO8–IO15 in High-Z Write Active (ICC) L L X L H Data In (IO8–IO15); IO0–IO7 in High-Z Write Active (ICC) Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 45 CY62146ELL-45ZSXI 51-85087 44-pin Thin Small Outline Package II (Pb-free) Industrial 45 CY62146ELL-45ZSXA 51-85087 44-pin Thin Small Outline Package II (Pb-free) Automotive-A Contact your local Cypress sales representative for availability of these parts. Document #: 001-07970 Rev. *C Page 9 of 11 [+] Feedback CY62146E MoBL® Package Diagram Figure 9. 44-Pin TSOP II, 51-85087 DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 1 23 10.262 (0.404) 10.058 (0.396) 11.938 (0.470) 11.735 (0.462) 22 EJECTOR PIN 44 TOP VIEW 0.800 BSC (0.0315) OR E K X A SG BOTTOM VIEW 0.400(0.016) 0.300 (0.012) 10.262 (0.404) 10.058 (0.396) BASE PLANE 0.210 (0.0083) 0.120 (0.0047) 0°-5° 0.10 (.004) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.729) 18.313 (0.721) SEATING PLANE 0.597 (0.0235) 0.406 (0.0160) 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-07970 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62146E MoBL® Document History Page Document Title: CY62146E MoBL®, 4-Mbit (256K x 16) Static RAM Document Number: 001-07970 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 463213 See ECN NXR New Data Sheet *A 684343 See ECN VKN Added Preliminary Automotive-A Information Updated Ordering Information Table *B 925501 See ECN VKN Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters *C 1045260 See ECN VKN Converted Automotive-A specs from preliminary to final Document #: 001-07970 Rev. *C Page 11 of 11 [+] Feedback