CLC420 High-Speed, Voltage Feedback Op Amp General Description Applications The CLC420 is an operational amplifier designed for applications requiring matched inputs, integration or transimpedance amplification. Utilizing voltage feedback architecture, the CLC420 offers a 300MHz bandwidth, a 1100V/µs slew rate and a 4mA supply current (power consumption of 40mW, ± 5V supplies). Applications such as differential amplifiers will benefit from 70dB common mode rejection ratio and an input offset current of 0.2µA. With its unity-gain stability, 2pA/ current noise and 3µA of input bias current, the CLC420 is designed to meet the needs of filter applications and log amplifiers. The low input offset current and current noise, combined with a settling time of 18ns to 0.01% make the CLC420 ideal for D/A converters, pin diode receivers and photo multipliers amplifiers. All applications will find 70dB power supply rejection ratio attractive. n n n n n n Active filters/integrators Differential amplifiers Pin diode receivers Log amplifiers D/A converters Photo multiplier amplifiers Non-Inverting Frequency Response Features n n n n n n n 300MHz small signal bandwidth 1100V/µs slew rate Unity-gain stability Low distortion, -60dBc at 20MHz 0.01% settling in 18ns 0.2µA input offset current 2pA current noise DS012752-19 Connection Diagram DS012752-18 Pinout DIP & SOIC DS012752-20 2nd and 3rd Harmonic Distortion © 1999 National Semiconductor Corporation DS012752 www.national.com CLC420 High-Speed, Voltage Feedback Op Amp September 1999 CLC420 Ordering Information Package Temperature Range Industrial Packaging Marking 8-pin plastic DIP −40˚C to +85˚C CLC420AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC420AJE CLC420AJE-TR13 M08A www.national.com 2 NSC Drawing Supply Voltage (VCC) IOUT (is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed 70mA, except A8D, B8D which should not exceed 35mA over the military temperature range).. ± VCC Common Mode Input Voltage Differential Input Voltage Junction Temperature Operating Temperature Range AJ: Storage Temperature Range Lead Solder Duration (+300˚C) ± 7V 10V +150˚C −40˚C to +85˚C −65˚C to +150˚C 10 sec Electrical Characteristics AV = +1, VCC = ± 5V, RL = 100Ω, Rf = 0Ω; unless specified Symbol Parameter Ambient Temperature Conditions Typ CLC420AJ +25˚C −40˚C Max/Min (Note 2) +25˚C +85˚ Units > 200 > 25 > 65 > 35 > 130 > 20 > 45 > 30 MHz Frequency Domain Response VOUT < 0..4VPP 300 VOUT < 5VPP 40 Av = −1, Rf = 500Ω Av = −1, Rf = 500Ω VOUT < 0.4VPP 100 VOUT < 5VPP 60 > 200 > 20 > 65 > 30 gain flatness VOUT < 0.4VPP GFPL peaking 0.1MHz to 100MHz 0 <1 < 0.6 < 0.6 dB SSBW -3dB bandwidth LSBW SSBWI LSBWI MHz MHz MHz GFPH peaking > 100MHz 0 rolloff 0.1MHz to 100MHz 0.2 <5 <1 <3 <1 <3 <2 dB GFR GFRI rolloff, Av = −1, Rf = 500Ω 0.1MHz to 30MHz 0.2 < 1.4 < 1.4 < 1.6 dB LPD linear phase deviation 0.1MHz to 100MHz 0.9 < 1.8 < 1.8 < 2.5 ˚ <2 < 25 < 5.5 <2 < 20 < 5.5 <3 < 20 < 7.8 ns < 10 < 18 < 25 < 35 > 600 > 430 < 9.5 < 18 < 25 < 25 > 750 > 500 < 10 < 18 < 25 < 25 > 600 > 430 < −40 < −45 < −40 < −40 < −40 < −40 dBc −51 < −40 < −45 < −40 dB Time Domain Response TRS rise and fall time TRL TRSI rise and fall time,Av = −1, Rf = 500Ω TRLI 0.4V step 1.2 5V step 1.4 0.4V step 3.5 5V step 6 TSS settling time to ± 0.1% 2V step 12 TSP ± 0.01% 2V step 18 OS overshoot 0.4V step 8 SR slew rate, Av = +2 slew rate, Av = −1, Rf = 500Ω 5V step 1100 5V step 750 SRI ns ns ns ns ns % V/µs V/µs Distortion And Noise Response HD2 2nd harmonic distortion 2VPP, 20MHz −50 HD3 3rd harmonic distortion −53 HD2 2nd harmonic distortion HD3 3rd harmonic distortion 2VPP, 20MHz Av = −1 2VPP, 20MHz, Rf = 500 Av = −1, Rf = 500Ω2VPP, 20MHz, Rf = 500 −51 < −40 < −40 < −35 dBc 1MHz to 200MHz 4.2 < 5.3 < 5.3 <6 nV/ dBc dBc input referred noise VN voltage 3 www.national.com CLC420 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. CLC420 Electrical Characteristics (Continued) AV = +1, VCC = ± 5V, RL = 100Ω, Rf = 0Ω; unless specified Symbol Parameter Conditions Typ Max/Min (Note 2) Units Distortion And Noise Response ICN current 1MHz to 200MHz 2 < 2.9 < 2.6 < 2.3 < 3.2 < 15 < 20 < 120 < 2.6 < 20 > 52 > 55 > 60 <5 <2 > 56 > 60 > 65 <5 < 3.5 < 15 < 10 < 60 <2 < 10 > 56 > 60 > 65 <5 >1 <2 >1 <2 MΩ > 0.5 <2 < 0.2 > 0.5 <2 < 0.2 MΩ pA/ Static DC Performance VIO input offset voltage (Note 3) 1 DVIO average temperature coefficient 8 IB input bias current (Note 3) 3 DIB average temperature coefficient 45 IIO input offset current (Note 3) 0.2 DIIO average temperature coefficient 2 AOL open loop gain (Note 3) 65 PSRR power supply rejection ratio 70 CMRR common mode rejection ratio 80 ICC supply current (Note 3) - < 10 - <1 - mV µV/˚C µA A/˚C µA nA/˚C µA dB dB no load,quiescent 4 resistance 2 capacitance 1 common mode input resistance 1 RO output impedence at DC 0.02 > 0.5 <2 > 0.25 <2 < 0.3 VO output voltage range V common mode input range ± 2.5 ± 2.8 ± 2.5 ± 2.8 V CMIR ± 2.8 ± 2.5 ± 2.5 ±3 output voltage range ± 3.6 ± 2.9 ± 3.2 ±3 VOL no load RL = 100Ω IO output current ± 60 ± 30 ± 50 ± 50 mA mA Miscellaneous Performance RIND differential mode input CIND RINC CINC capacitance for rated performance 1 pF pF Ω V Package Thermal Resistance junction to case CLC420AJP 65˚ - - - - C/W junction to ambient CLC420AJP 120˚ - - - - C/W junction to case CLC420AJE 60˚ - - - - C/W junction to ambient CLC420AJE 140˚ - - - - C/W Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. www.national.com 4 Non-Inverting Frequency Response Inverting Frequency Response Frequency Response for Various RLS DS012752-2 DS012752-1 DS012752-3 Open Loop Gain and Phase Bandwidth vs. Gain, Transimpedance Configuration DS012752-4 2nd and 3rd Harmonic Distortion DS012752-6 DS012752-5 2-Tone, 3rd Order Intermodulation Intercept Equivalent Input Noise PSRR, CMRR, and Closed Loop RO DS012752-8 DS012752-9 DS012752-7 5 www.national.com CLC420 Typical Performance Characteristics CLC420 Typical Performance Characteristics Pulse Response (Continued) Settling Time Long-Term Settling Time DS012752-10 DS012752-11 DS012752-12 Settling Time vs. Capacitive Load Settling Time vs. Gain IB and IOS vs. Common-Mode Voltage DS012752-13 DS012752-15 DS012752-14 www.national.com 6 CLC420 Application Division DS012752-16 FIGURE 1. Recommended Non-Inverting Gain Circuit DS012752-17 FIGURE 2. Recommended Inverting Gain Circuit Another point to remember is that the closed-loop bandwidth is determined by the noise gain, not the signal gain of the circuit. Noise gain is the reciprocal of the attenuation in the feedback network enclosing the op amp. For example, a CLC420 setup as a non-inverting amplifier with a closed-loop gain of +1 (a noise gain of 1) has a 300MHz bandwidth. When used as an inverting amplifier with a gain of −1 (a noise gain of 2), the bandwidth is less, typically only 100MHz. Full-power bandwidth, and slew-rate The CLC420 combines exceptional full-power bandwidths (40MHz, V0 = 5Vpp, Av = +1) and slew rates (1100V/µs, Av = +1) with low (40mW) power consumption. These attractive results are achieved by using slew-boosting circuitry to keep the slew rates high while consuming very little power. In non-slew boosted amplifiers, full-power bandwidth can be easily determined from slew-rate measurements, but in slew-boosting amplifiers, such as the CLC420, you can’t. For this reason we provide data for both. Slew rate is also different for inverting and non-inverting configurations. This occurs because common-mode signal voltages are present in non-inverting circuits but absent in inverting circuits. Once again data is provided for both. Description The CLC420 is a high-speed, slew-boosted, voltage feedback amplifier with unity-gain stability. These features along with matched inputs, low input bias and noise currents, and excellent CMRR render the CLC420 very attractive for active filters, differential amplifiers, log amplifiers, and transimpedance amplifiers. DC accuracy Unlike current-feedback amplifiers, voltage-feedback amplifiers have matched inputs. This means that the non-inverting and inverting input bias current are well matched and track over temperature, etc. As a result, by matching the resistance looking out of the two inputs, these errors can be reduced to a small offset current term. Gain bandwidth product Since the CLC420 is a voltage-feedback op-amp, closed-loop bandwidth is approximately equal to the gain-bandwidth product (typically 100MHz) divided by the noise gain of the circuit (for noise gains greater than 5). At lower noise gains, higher-order amplifier poles contribute to higher closed-loop bandwidth. At low gains use the frequency response performance plots given in the data sheet. 7 www.national.com CLC420 Application Division From the “Transimpedance BW vs. Rf and Ci” plot, using Ci = 5pF it is determined from the two curves labeled Ci = 5pF, that Cf = 1.5pF provides optimal compensation (no more than 0.5dB frequency response peaking) and a −3dB bandwidth of approximately 27MHz. Printed circuit layout As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and good power supply bypassing close to the package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the output and inverting input: Node connections should be small with minimal coupling to the ground plane. (Continued) Transimpedance amplifier circuits Low inverting, input current noise (2pA/ ) makes the CLC420 ideal for high-sensitivity transimpedance amplifier circuits for applications such as pin-diode optical receivers, and detectors in receiver IFs. However, feedback resistors 4kΩ or greater are required if feedback resistor noise current is going to be less than the input current noise contribution of the op-amp. With feedback resistors this large, shunt capacitance on the inverting input of the op-amp (from the pin-diode, etc.) will unacceptably degrade phase margin causing frequency response peaking or oscillations a small valued capacitor shunting the feedback resistor solves this problem (Note: This approach does not work for a current-feedback op-amp configured for transimpedance applications). To determine the value of this capacitor, refer to the “Transimpedance BW vs. Rf and Ci” plot. For example, let’s assume an optical transimpedance receiver is being developed. Total capacitance from the inverting input to ground, including the photodiode and strays is 5pF. A 5kΩ feedback resistor value has been determined to provide best dynamic range based on the response of the photodiode and the range of incident optical powers, etc. www.national.com Parasitic or load capacitance directly on the output (pin 6) will introduce additional phase shift in the loop degrading the loop phase margin and leading to frequency response peaking. A small series resistor before this capacitance, if present, effectively decouples this effect. The graphs on the preceding page, “ Settling Time vs. CL”, illustrates the required resistor value and resulting performance vs. capacitance. Evaluation PC boards (part no. 730013 for through-hole and CLC730027 for SOIC) are available for the CLC420. 8 CLC420 Physical Dimensions inches (millimeters) unless otherwise noted N08E - CLC420AJP M08A - CLC420AJE or CLC420AJE-TR13 9 www.national.com CLC420 High-Speed, Voltage Feedback Op Amp Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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