DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 DS32EL0421 , DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface Check for Samples: DS32EL0421, DS32ELX0421 FEATURES DESCRIPTION • • • • • • The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface. 1 2 • • • • • • • • • • • 5-bit DDR LVDS Parallel Data Interface Programmable Transmit De-emphasis Configurable Output Levels (VOD) Selectable DC-balanced Encoder Selectable Data Scrambler Remote Sense for Automatic Detection and Negotiation of Link Status On Chip LC VCOs Redundant Serial Output (ELX device only) Data Valid Signaling to Assist with Synchronization of Multiple Receivers Supports AC- and DC-coupled Signaling Integrated CML and LVDS Terminations Configurable PLL Loop Bandwidth Programmable Output Termination (50Ω or 75Ω). Built-in Test Pattern Generator Loss of Lock and Error Reporting Configurable via SMBus 48-pin WQFN Package with Exposed DAP The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DCbalance encoding is enabled, the maximum data payload achievable is 2.5 Gbps. The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path. The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins. TARGET APPLICATIONS • • • • • • Imaging: Industrial, Medical Security, Printers Displays: LED Walls, Commercial Video Transport Communication Systems Test and Measurement Industrial Bus KEY SPECIFICATIONS • • • • • 1.25 to 3.125 Gbps Serial Data Rate 125 to 312.5 MHz DDR Parallel Clock -40° to +85°C Temperature Range >8 kV ESD (HBM) Protection Low Intrinsic Jitter — 35ps at 3.125 Gbps 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Application DS32ELX0421 5 LVDS R0 D1 R1 Redundant Driver Redundant Link Retimed Output LVDS Interface D0 Serial to Parallel Parallel to Serial Encoder LVDS Interface LVDS Interface LVDS Interface LVDS Interface 3.125 Gbps Data Payload RT0 LVDS System Logic 5 LVDS System Logic FPGA DS32ELX0124 LVDS Interface FPGA LVDS PLL Clock Control PLL Control Clock Control Control SMBus SMBus VDD33 1 N/C 2 TXIN4- TXIN4+ TXIN3- TXIN3+ TXIN2- TXIN2+ TXIN1- TXIN1+ TXIN0- TXIN0+ TXCLKIN- TXCLKIN+ 48 47 46 45 44 43 42 41 40 39 38 37 Connection Diagram 36 VDD33 35 VDD25 49 DAP = GND GPIO0 3 34 SMB_CS GPIO1 4 33 SCK DC_B 5 32 SDA RS 6 31 LOCK 30 RESET DS32EL0421 23 24 N/C VDD25 N/C 25 22 12 N/C N/C 21 LF_REF N/C 26 20 11 N/C GPIO2 19 LF_CP N/C 27 18 10 VDD25 DE_EMPH1 17 VDDPLL TXOUT0- 28 16 9 TXOUT0+ DE_EMPH0 15 RSVD VDD25 29 14 8 VOD_CTRL N/C 13 7 N/C VDD25 See Package Number RHS0048A TOP VIEW 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 VDD33 1 N/C 2 TXIN4- TXIN4+ TXIN3- TXIN3+ TXIN2- TXIN2+ TXIN1- TXIN1+ TXIN0- TXIN0+ TXCLKIN- TXCLKIN+ 47 46 45 44 43 42 41 40 39 38 37 SNLS282F – MAY 2008 – REVISED APRIL 2013 48 www.ti.com 36 VDD33 35 VDD25 49 DAP = GND GPIO0 3 34 SMB_CS GPIO1 4 33 SCK DC_B 5 32 SDA RS 6 31 LOCK 30 RESET DS32ELX0421 23 24 N/C VDD25 N/C 25 22 12 N/C TXOUT1_EN 21 LF_REF N/C 26 20 11 TXOUT1- GPIO2 19 LF_CP TXOUT1+ 27 18 10 VDD25 DE_EMPH1 17 VDDPLL TXOUT0- 28 16 9 TXOUT0+ DE_EMPH0 15 RSVD VDD25 29 14 8 VOD_CTRL N/C 13 7 N/C VDD25 See Package Number RHS0048A TOP VIEW PIN DESCRIPTIONS Pin Name Pin Number I/O, Type Description Power, Ground and Analog Reference VDD33 VDD25 I, VDD 3.3V supply 7, 15, 18, 25, I, VDD 35 1, 36 2.5V supply VDDPLL 28 I, VDD 3.3V supply VOD_CTRL 14 Analog VOD control. The serializer output amplitude can be adjusted by connecting this pin to a pulldown resistor. The value of the resistor determines the VOD. See CML LAUNCH AMPLITUDE for more details. LF_CP 27 Analog Loop filter connection for PLL LF_REF 26 Analog Loop filter ground reference Exposed Pad 49 GND Exposed Pad must be connected to GND by 9 vias TxOUT0+ TxOUT0- 16 17 O, CML Inverting and non-inverting high speed CML differential outputs of the serializer. These outputs are internally terminated. TxOUT1+ TxOUT1- 19 20 O, CML DS32ELX0421 ONLY. Redundancy output. Inverting and non-inverting high speed CML differential outputs of the serializer. These outputs are internally terminated CML I/O Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 3 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin Number I/O, Type Description 37 38 I, LVDS Serializer input clock. TxCLKIN+/- are the inverting and non-inverting LVDS transmit clock input pins. 39, 40, 41, 42, 43, 44, 45, 46, 47, 48 I, LVDS Serializer input data. TxIN[4:0]+/- are the inverting and non-inverting LVDS serializer input data pins. LVDS Parallel Data Bus TxCLKIN+ TxCLKINTxIN[4:0]+/- LVCMOS Control Pins DC_B RS 5 6 I, LVCMOS DC-balance and Remote Sense pins. See Device Configuration section DEVICE CONFIGURATION for device behavior. DE_EMPH0 DE_EMPH1 9 10 I, LVCMOS DE_EMPH0, DE_EMPH1 select the output de-emphasis level. These pins are internally pulldown. 00: Off 01: Low 10: Medium 11: Maximum TXOUT1_EN 12 I, LVCMOS DS32ELX0421 ONLY. When held high, redundant output TxOUT1+/- is enabled. This pin must be tied high when using TxOUT1+/-. RESET 30 I, LVCMOS When held low, reset the device. 0 = Device Reset 1 = Normal operation LOCK 31 O, LVCMOS Lock indication output. The input data on TxIN[0:4]+/- pins is ignored when LOCK pin is high. SCK 33 I/O, SMBus SMBus compatible clock. SDA 32 I/O, SMBus SMBus compatible data line. SMB_CS 34 I, SMBus SMBus chip select. When held high, SMBus management control is enabled. GPIO0 3 I/O, LVCMOS Software configurable I/O pin. GPIO1 4 I/O, LVCMOS Software configurable I/O pin. GPIO2 11 I/O, LVCMOS Software configurable I/O pin. 2, 8, 12, 13, 19, 20, 21, 22, 23, 24, 29 Misc. No Connect, for DS32EL0421 2, 8, 13, 21, 22, 23, 24, 29 Misc. No Connect, for DS32ELX0421 SMBus Interface Other NC These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (3.3V VDD33) −0.3V to +3V Supply Voltage (2.5V VDD25) LVCMOS Input Voltage −0.3V to (VDD + 0.3V) LVCMOS Output Voltage −0.3V to (VDD + 0.3V) LVDS Input Voltage (IN+, IN-) −0.3V to +3.6V CML Output Voltage −0.3V to +3.6V Junction Temperature +125°C Storage Temperature Range -65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C Thermal Resistance, θJA 25°C/W ESD Susceptibility HBM (1) (2) (3) (3) >8 kV “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114C Recommended Operating Conditions Min Typ Max Units Supply Voltage (VDD33 – GND) 3.135 3.3 3.465 V Supply Voltage (VDD25 – GND) 2.375 2.5 2.625 V 100 mVP-P -40 +25 +85 °C Supply Noise Amplitude from 10 Hz to 50 MHz Ambient Temperature (TA) Power Supply Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol IDD25 Parameter Condition 2.5V supply current 1 Output Enabled 2.5V supply current 2 Outputs Enabled IDD33 3.3V supply current 1 Output Enabled 3.3V supply current 2 Outputs Enabled (1) (2) (1) (2) Min Typ Max 1.25 Gbps 87 94 2.5 Gbps 95 105 3.125 Gbps 101 112 1.25 Gbps 126 135 2.5 Gbps 136 145 3.125 Gbps 142 152 1.25 Gbps 74 85 2.5 Gbps 74 85 3.125 Gbps 74 85 1.25 Gbps 80 92 2.5 Gbps 80 92 3.125 Gbps 80 92 Unit mA mA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 5 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Power Supply Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol PD Parameter Condition Power Consumption 1 Output Enabled Power Consumption 2 Output Enabled Min Typ Max 1.25 Gbps 460 540 2.5 Gbps 485 560 3.125 Gbps 500 575 1.25 Gbps 580 670 2.5 Gbps 605 695 3.125 Gbps 620 710 Unit mW LVCMOS Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Applies to GPIO0, GPIO1, GPIO2, RESET, LOCK, RS, and DC_BAL. (1) (2) (3) Symbol Parameter Conditions Min Typ Max Units VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage IOH = -2mA VOL Low Level Output Voltage IOL = 2mA VCL Input Clamp Voltage ICL = -18mA IIN Input Current VIN = 0.4V, 2.5V, or VDD IOS Output Short Circuit Current VOUT = 0V (1) (2) (3) (4) 2.7 3.3 V 0.3 -0.79 -35 V 35 μA 42 (4) V -1.5 mA The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. SMBus Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter VSIL Data, Clock Input Low Voltage VSIH Data, Clock Input High Voltage VSDD Nominal Bus Voltage iSLEAKB Input Leakage Per Bus Segment CSI Capacitance for SDA and SCLK (1) (2) (3) (4) (5) 6 Conditions See (4) (5) , (1) (2) (3) Min Typ Max Units 0.8 V 2 VSDD V 2.375 3.6 V ±200 μA 10 pF The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Recommended value, parameter is not tested. Recommended maximum capacitance load per bus segment is 400 pF. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 SMBus Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter (1) (2) Conditions Min Typ Max Units 100 kHz tSMB Bus Operating Frequency 10 tBUF Bus Free Time between Stop and Start Condition 4.7 μs tHD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. 4.0 μs tSU:STA Repeated Start Condition Setup Time 4.7 μs tSU:STO Stop Condition Setup Time 4.0 μs tHD:DAT Data Hold Time 300 ns tSU:DAT Data Setup Time 250 ns tLOW Clock Low Time 4.7 tHIGH Clock High Time 4.0 tF Clock/Data Fall Time tR Clock/Data Rise Time tSU:CS SMB_CS Setup Time tPOR Time in which the device must be operation after power on (1) (2) (3) μs 20% to 80% 50 μs 300 ns 1000 ns 500 ms 30 See (3) ns The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Parameter is ensured by characterization and is not tested at production. LVDS Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions VTH Differential Input High Threshold VTL Differential Input Low Threshold VLVCM LVDS Input Common Mode Voltage VLVOS LVDS Input Loss of Signal LVDS input loss of signal level. See (4) RLVIN Input Impedance Internal LVDS input termination between differential pairs. (1) (2) (3) (4) (1) (2) (3) Min 0.05V < VLVCM < VDD25 – 0.05V Typ Max Units +100 mV -100 mV 0.05 VDD25 – 0.05 20 85 100 V mVP-P 115 Ω The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. If input LVDS signal is below 20mVP-P, loss of signal (LOS) is detected. The device will flag a valid input signal if the signal level is above 100mVP-P LVDS Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions f Input DDR Clock (TxCLKIN) Frequency Range tCIP TxCLKIN Period (1) (2) (1) (2) Min Typ 125 See Figure 3 3.2 2T Max Units 312.5 MHz 8 ns The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 7 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com LVDS Timing Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter tCIT TxCLKIN Transition Time tXIT TxIN Transition Time tCIH TxCLKIN High Time tCIL Conditions See Figure 2 See (3) Min Typ Max Units 0.5 1.0 3.0 ns 3 ns 0.15 0.7T T 1.3T ns TxCLKIN Low Time 0.7T T 1.3T ns tSTC TxIN Setup to TxCLKIN -550 tHTC TxIN Hold to TxCLKIN 900 tLVDLS LVDS Input Clock Delay Step Size (3) See Figure 3 Programmable through the SMBus, register 30'h Default setting = 011'b [7:5] ps ps 100 ps Parameter is ensured by characterization and is not tested at production. CML Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter ROT Output Terminations ΔROT Mismatch in Output Termination Resistors VOD Output Differential Voltage Swing (1) (2) (3) (1) (2) (3) Conditions Min Typ Max Units On chip termination from TxOUT0/1 + and TxOUT0/1 - to VDD25 50Ω mode 40 50 60 Ω 75Ω mode 60 75 90 Ω 5 % 1450 mVP-P Based on VOD_CTRL = 9.1 kΩ 1175 1350 The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and ΔVOD. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. CML Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter (1) (2) Conditions LR Line Rate Tested with alternating 1-0 pattern. tOS Output Overshoot See tR Differential Low to High Transition Time tF Differential High to Low Transition Time tRFMM Mismatch in Rise/Fall Time tDE De-emphasis width tBIT Serializer Bit Width tSD Serializer Propagation Delay – Latency (1) (2) (3) 8 See See Min Typ Max Units 3.125 Gbps 10 % 60 90 ps 60 90 ps 15 ps 1.25 (3) (3) (3) Measured from zero-crossing at rising edge to 80% of VOD from zerocrossing at falling edge. TDE is measured at the High setting during test. Depends on mode — see Table 3 1 UI 0.2 x tCIP ns (10 – 14) T+ 5.5 ns The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. Parameter is ensured by characterization and is not tested at production. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 CML Timing Specifications (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol tJIND tJINR tJINT Parameter Conditions Serializer Output Deterministic Jitter Serializer Output Random Jitter Peak-to-peak Serializer Output Jitter λTXBW Jitter Transfer Function -3 dB Bandwidth δTX Jitter Transfer Function Peaking (4) (4) Min Typ Max Units Serializer output intrinsic deterministic jitter. Measure with PRBS-7 test pattern De-emphasis disabled. See (3) 1.25 Gbps 10 ps 2.5 Gbps 24 ps 3.125 Gbps 21 ps Serializer output intrinsic random jitter. Bit error rate ≥10-15. Alternating–10 pattern. De-emphasis disabled. See (3) 1.25 Gbps 1.3 psRMS 2.5 Gbps 1.15 psRMS 3.125 Gbps 1.14 psRMS Serializer output peak-to-peak jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input. Measure with PRBS-7 test pattern. Bit error rate ≥10-15. Deemphasis disabled. See (3) 1.25 Gbps 28 ps 2.5 Gbps 38 ps 3.125 Gbps 35 ps 1.25 Gbps 3.125 Gbps 100 300 kHz kHz 0.5 dB (4) Parameter is ensured by characterization and is not tested at production. Timing Diagrams SMB_CS tSU:CS tLOW tHIGH tR SCK tHD:STA tBUF tF tHD:DAT tSU:STA tSU:DAT tSU:STO SDA SP ST SP ST Figure 1. SMBus timing parameters 80% 80% TXCLK 20% 20% tCIT tCIT Figure 2. Serializer Input Clock Transition Time Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 9 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com tCIP/2 +100 mV TXCLK 0V -100 mV tCIL, tCIH tSTC tHTC Hold Setup TXn 0V Figure 3. Serializer (LVDS Interface) Setup/Hold and High/Low Times tCIP/2 TxCLKIN Clock Delay (Programmable) Programmable Delay Clock (Internal) tHTC tSTC TxIN Valid Data Window Figure 4. LVDS Input Clock Delay TXN Symbol N Symbol N+1 Symbol N+2 Symbol N+3 Symbol N+4 tSD TXCLK Symbol N-4 Symbol N-3 Symbol N-1 Symbol N-2 Symbol N TXOUT Figure 5. Propagation Delay Timing Diagram 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Previous Cycle Current Cycle Next Cycle Input Transmit Clock LVDS Data-0 A0 A1 A2 A3 LVDS Data-1 B0 B1 B2 B3 LVDS Data-2 C0 C1 C2 C3 LVDS Data-3 D0 D1 D2 D3 LVDS Data-4 E0 E1 E2 E3 Last Bit Out First Bit Out E3 D3 B3 C3 A3 E2 D2 B2 C2 A2 E1 D1 B1 C1 A1 E0 D0 B0 C0 A0 Serialized CML Output Figure 6. 5-Bit Parallel LVDS Inputs Mapped to CML Output FUNCTIONAL DESCRIPTION POWER SUPPLIES The DS32EL0421 and DS32ELX0421 have several power supply pins, at 2.5V as well as 3.3V. It is important that these pins all be connected and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF capacitors as a minimum, with a 0.1μF capacitor on each power pin. A 22 μF capacitor is required on the VDDPLL pin which is connected to the 3.3V rail. These devices have a large contact in the center on the bottom of the package. This contact must be connected to the system GND as it is the major ground connection for the device. POWER UP It is recommended, although not necessary, to bring up the 3.3V power supply before the 2.5V supply. If the 2.5V supply is powered up first, an initial current draw of approximately 600mA from the 2.5V rail may occur before settling to its final value. Regardless of the sequence, both power rails should monotonically ramp up to their final values. POWER MANAGEMENT These devices have two methods to reduce power consumption. To enter the first power save mode, the on board host FPGA or controlling device can cease to output the DDR transmit clock. To further reduce power consumption, write 40'h to register 26'h and 10'h to register 01'h. This will put the device in its lowest power consumption mode. RESET There are three ways to reset these devices. A reset occurs automatically during power-up. The device can also be reset by pulling the RESET pin low, with normal operation resuming when the pin is driven high again. The device can also be reset by writing to the reset register. This reset will put all of the register values back to their default values, except it will not affect the address register value if the SMBus default address has been changed. Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 11 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com LVDS INPUTS The DS32EL0421 and DS32ELX0421 have standard 2.5V LVDS inputs which are compliant with ANSI/TIA/EIA644. These inputs have internal 100Ω termination resistors. It is recommended that the PCB trace between the FPGA and the serializer be less than 40-inches. Longer PCB traces may degrade the quality of the input signal. The connection between the host and the DS32EL0421 or DS32ELX0421 should be over a controlled impedance transmission line with impedance that matches the termination resistor – usually 100Ω. Setup and hold times are specified in the LVDS Timing Specifications, however the clock delay can be adjusted by writing to register 30’h. LOOP FILTER The DS32EL0421 and DS32ELX0421 have an internal PLL which is used to generate the serialization clock from the parallel clock input. The loop filter for this PLL is external; and for optimum results, a 100nF capacitor and a 1.5 kΩ resistor in series should be connected between pins 26 and 27. See typical interface circuit (Figure 11). CML LAUNCH AMPLITUDE The launch amplitude of the CML output(s) is controlled by placing a single resistor from the VOD_CTRL pin to ground. Use the following equation to obtain the desired VOD by selecting the corresponding resistor value. R = (1400 mV / VOD) x 9.1 kΩ (1) The CML output launch amplitude can also be adjusted by writing to SMBus register 69'h, bits 2:0. This register is meant to assist system designers during the initial prototype design phase. For final production, it is recommended that the appropriate resistor value be selected for the desired VOD and that register 69'h be left to its default value. REMOTE SENSE The remote sense feature can be used when a DS32EL0421 or DS32ELX0421 serializer is directly connected to a DS32EL0124 or DS32ELX0124 deserializer. Active components in the signal path between the serializer and the deserializer may interfere with the back channel signaling of the devices. When remote sense is enabled, the serializer will cycle through four states to successfully establish a link and align the data. The state diagram for the serializer is shown in Figure 7. The serializer will remain in the low power IDLE state until it receives an input clock. Once the PLL of the serializer has locked to the input clock, the device will enter the LINK DETECT state. While in this state, the serializer will monitor the line to see if the deserializer is present. If a deserializer is detected, the serializer will enter the LINK ACQUISITION state. The serializer will transmit the entire training pattern and then enter the NORMAL state. If the deserializer is unable to successfully lock or maintain lock it will break the link, sending the serializer back to the IDLE or LINK DETECT states. With the Remote Sense feature active, the serializer can be forced out of lock due to events on the high speed serial line in two ways, a serial channel reset signal is sent upstream from the deserializer or the near end termination detect circuit signals and open termination was detected. The upstream signal sent from the deserializer that resets the serializer is called the link detect signal. Since the serializer and deserializer may power up at different times, the deserializer will transmit this link detect signal periodically, once it detects that a serializer is active on the other side of the high speed line. When a serializer receives the link detect signal, it will return to the LINK DETECT state. The near end open termination detection circuit will trigger only for near end open termination events, such as unplugging the cable on the serializer end of the line. DC-BALANCE ENCODER The DS32EL0421 and DS32ELX0421 have a built-in DC-balance encoder to support AC-coupled applications. When enabled, the input signal on TXIN4+/- is treated as a data valid bit. If TXIN4+/- is low, then the four bit nibbles from TXIN0-TXIN3 are taken to form a 16 bit word. This 16 bit word is processed as two 8 bit words and converted to two 10 bit words by using the standard 8b/10b data coding scheme. The two 10 bit words are then combined to create a 20 bit code. This 20 bit word is serialized and driven on the output. The nibble taken in on the rising edge of the clock is the most significant nibble and the nibble taken in on the falling edge is the least significant nibble. If TXIN4+/TXIN4- is high, then the inputs TXIN0 -TXIN3 are ignored and a programmable DCbalanced SYNC character is inserted in the output stream. The default character is a K28.5 code. In order to send other K codes, they must first be programmed into the serializer via the SMBus. The SMBus registers allows for only a single programmable character. 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Power-On/Reset TxCLKIN does not exist IDLE RS: 1, DC_B: 0 RS: 1, DC_B: 1 TxCLKIN exist LINK DETECT Link Detect fail LINK ACQUISITION NORMAL Figure 7. Serializer State Diagram SCRAMBLER and NRZI Encoder The CDR of the DS32EL0124 and the DS32ELX0124 expect a transition density of 20% for a period of 200 μs. If the scrambler and NRZI encoder are enabled, the raw or DC-balanced serialized data is scrambled to improve transition density. The scrambler accepts 20 bits of data and encodes it using the polynomial X9 + X4 + 1. The data can then be sent to the NRZ-to-NRZI converter before being output. Enabling the scrambler can help to lower EMI emissions by spreading the spectrum of the data. Scrambling also creates transitions for the deserializer’s CDR to properly lock onto. The scrambler and NRZI encoder are enabled or disabled by default depending on how the DC_B and RS pins are configured. To override the default scrambler setting two register writes must be performed. First, write to register 22’h and set bit 3 to unlock the scrambler register. Next write to register 21’h and change bit 4 to the desired value. The NRZI encoder can be enabled or disabled independently of the scrambler by controlling bit 7 of register 21'h and bit 4 of register 22'h. CML OUTPUT DATA INTERFACING The serial outputs provide low-skew differential signals. Internal resistors connected from TxOUTn+ and TxOUTn- to VDD25 terminate the outputs. The output level can be programmed by adjusting the pull-down resistor to the VOD_CTRL pin. The output terminations can also be programmed to be either 50 Ω or 75 Ω. The output buffer consists of a current mode logic (CML) driver with user configurable de-emphasis control, which can be used to optimize performance over a wide range of transmission line lengths and attenuation distortions resulting from low cost CAT(-5, -6, -7) cable or FR–4 backplane. Output de-emphasis is user programmable through either device pins DE_EMPH0 and DE_EMPH1 or SMBus interface. Users can control the strength of the de-emphasis to optimize for a specific system environment. Please see Table 1 for details. Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 13 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Table 1. De-Emphasis Control Table DE_EMPH[1:0] Output De-Emphasis Level 00'b Off 01'b Low 10'b Medium 11'b High The DS32ELX0421 provides a secondary serial output, supporting redundancy applications. The redundant output driver can be enabled by setting TXOUT1_EN pin to HIGH or by activating it through the SMBus reigsters. DEVICE CONFIGURATION There are four ways to configure the DS32EL0421 and DS32ELX0421 serializers, these combinations are shown in Table 2. Refer to Figure 7 to see how the combinations of the RS and DC_B pins change the link startup behavior of the serializers. When connecting to a deserializer other than the DS32EL0124 or DS32ELX0124, Remote Sense should be disabled. The scrambler and NRZI encoder shown in Table 2 can be enabled or disabled through register programming. When Remote Sense is enabled, with RS pin tied low, the serializer must be connected directly to a DS32EL0124 or DS32ELX0124 deserializer without any active components between them. The Remote Sense module features an upstream communication method for the serializer and deserializer to communicate. This feature is used to pass link status information between the 2 devices. When Remote Sense is enabled the serializer will send a training pattern to the deserializer to establish lock and lane alignment. If DC-Balance is enabled, a maximum of 4 parallel LVDS lanes can be used to receive data. The fifth lane (TXIN4±) is used for Data Valid signaling. Each time a serializer establishes a link to a deserializer with DCBalance enabled and Remote Sense disabled, the Data Valid input to the serializer must be held high for 110 LVDS clock periods. If the Data Valid input to the serializer is logic HIGH, then SYNC characters are transmitted. If the deserializer receives a SYNC character, then the LVDS data outputs will all be logic low and the Data Valid output will be logic high. If the deserializer detects a DC-Balance code error, the output data pins will be set to logic high with the Data Valid output also set to logic high. In the case where DC-Balance is enabled and Remote Sense is disabled, with RS set to high and DC_B set to low, it is recommended that the host device periodically toggle the Data Valid input to the serializer, to transmit SYNC symbols on the line, to ensure that the deserializer is and remains locked. In this configuration the deserializer or receiving device does not have a way to directly notify the serializer if it has lost lock. Periodically sending SYNC symbols will allow the receiving system to reacquire lock if a problem has occurred. With these pin settings the DS32EL0421/DS32ELX0421 and DS32EL0124/DS32ELX0124 devices can interface with other active component in the high speed signal path, such as fiber modules. When both Remote Sense and DC-Balance are disabled, RS and DC_B pins set to high, the LVDS lane alignment is not maintained. In this configuration, data formatting is handled by an FPGA or external source. This pin setting combination also allows for the DS32EL0421/DS32ELX0421 devices to interface with active components other than the DS32EL0124/DS32ELX0124 in the high speed signal path. In this configuration the host device is responsible for DC balancing the data in an AC coupled application. 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Table 2. Device Configuration Table Remote Sense Pin (RS) DC-Balance Pin (DC_B) Configuration 0 0 Remote Sense enabled DC-Balance enabled Data Alignment Scrambler and NRZI encoder disabled by default 0 1 Remote Sense enabled DC-Balance disabled Data Alignment Scrambler and NRZI encoder enabled by default 1 0 Remote Sense disabled DC-Balance enabled Data Alignment Scrambler and NRZI encoder enabled by default 1 1 Remote Sense disabled DC-Balance disabled No Data Alignment Scrambler and NRZI encoder disabled by default SMBus INTERFACE The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the Chip Select signal is required. Holding the SMB_CS pin HIGH enables the SMBus port, allowing access to the configuration registers. Holding the SMB_CS pin LOW disables the device's SMBus, allowing communication from the host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active. When communication to other devices on the SMBus is active, the SMB_CS signal for the serializer must be driven LOW. The address byte for all DS32EL0421 and DS32ELX0421 devices is AE'h. Based on the SMBus 2.0 specification, these devices have a 7-bit slave address of 1010111'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1110 'b or AE'h. The SCK and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not 5V tolerant. Transfer of Data via the SMBus During normal operation the data on SDA must be stable during the time when SCK is HIGH. There are three unique states for the SMBus: START A HIGH to LOW transition on SDA while SCK is HIGH indicates a message START condition STOP A LOW to HIGH transition on SDA while SCK is HIGH indicates a message STOP condition. IDLE If SCK and SDA are both high for a time exceeding tBUF from the last detected STOP condition or if they are HIGH for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus Transactions The devices support WRITE and READ transactions. See Register Description Table for register address, type (Read/ Write, Read Only), default value and function information. Writing to a Register To 1. 2. 3. 4. 5. write a register, the following protocol is used (see SMBus 2.0 specification). The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. The Device (Slave) drives the ACK bit (“0”). The Host drives the 8-bit Register Address. The Device drives an ACK bit (“0”). Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 15 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 6. 7. 8. 9. The The The The www.ti.com Host drive the 8-bit data byte. Device drives an ACK bit (“0”). Host drives a STOP condition. Host de-selects the device by driving its SMBus CS signal Low. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. Reading a Register To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host (Master) selects the device by driving its SMBus Chip Select (SMB_CS) signal HIGH. 2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 3. The Device (Slave) drives the ACK bit (“0”). 4. The Host drives the 8-bit Register Address. 5. The Device drives an ACK bit (“0”). 6. The Host drives a START condition. 7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 8. The Device drives an ACK bit “0”. 9. The Device drives the 8-bit data value (register contents). 10. The Host drives a NACK bit “1”indicating end of the READ transfer. 11. The Host drives a STOP condition. 12. The Host de-selects the device by driving its SMBus CS signal Low. The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. SMBus Configurations Many different configurations of the SMBus are possible and depend upon the specific requirements of the applications. Several possible applications are described. Configuration 1 The deserializer SMB_CS may be tied High (always enabled) since it is the only device on the SMBus. See Figure 8. Configuration 2 Since the multiple SER devices have the same address, the use of the individual SMB_CS signals is required. To communicate with a specific device, its SMB_CS is driven High to select the device. After the transaction is complete, its SMB_CS is driven Low to disable its SMB interface. Other devices on the bus may now be selected with their respective chip select signals and communicated with. See Figure 9. Configuration 3 The addressing field is limited to 7-bits by the SMBus protocol. Thus it is possible that multiple devices may share the same 7-bit address. An optional feature in the SMBus 2.0 specification supports an Address Resolution Protocol (ARP). This optional feature is not supported by the DS32EL0421/DS32ELX0421 devices. Solutions for this include: the use of the independent SMB_CS signals, independent SMBus segments, or other means. 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 SMBus Device FPGA Host 3V3 SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 8. SMBus Configuration 1 SMBus Device FPGA Host SMBus Device SMBus Device SMB_CS SDA SCK SMB_CS SDA SCK SMB_CS SDA LVCMOS GPIO SMBus Interface SCK 3V3 Figure 9. SMBus Configuration 2 SMBus Device SMBus Device 3V3 SMB_CS SDA SCK SMB_CS 3V3 SDA SMB_CS SDA SCK LVCMOS GPIO SMBus Interface SMBus Device 3V3 3V3 SCK FPGA Host Figure 10. SMBus Daisy Chained CS Configuration Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 17 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com PROPAGATION DELAY Once the serializer is locked, the amount of time it takes for a bit to travel into the device through the DDR LVDS inputs and out through the CML serial output is defined to be the propagation delay. The propagation delay through the DS32EL0421/DS32ELX0421 due to the analog circuitry is considered negligible compared to the time delay caused by the digital components. The information presented in this section allows system designers to predict the propagation delay through the device in terms of clock cycles which are proportional to the high speed serial line rate. Each clock cycle shown in Table 3 is defined to be 1/2 tCIP. Note at 3.125Gbps, tCIP is 312.5MHz, T is 1/2 tCIP or 156.25MHz which is 6.40ns per clock.. Table 3. Serializer Propagation Delay Config. Pins (DC_B, RS) LVDS Interface DC Balance Encoder Scrambler NRZ Encoder CML interface Analog Delay Total Propagation Delay Data Flow (left to right) 0, 0 3 clocks 1 clock – – 5 – 6 clocks 2 clocks + ~5.5ns 11 – 12 clocks + ~5.5ns 0, 1 3 clocks 1 clock 1 clock 1 clock 5 – 6 clocks 2 clocks + ~5.5ns 13 – 14 clocks + ~5.5ns 1, 0 3 clocks – 1 clock 1 clock 5 – 6 clocks 2 clocks + ~5.5ns 12 – 13 clocks + ~5.5ns 1, 1 3 clocks – – – 5 – 6 clocks 2 clocks + ~5.5ns 10 – 11 clocks + ~5.5ns Application Information GPIO PINS The GPIO pins can be useful tools when debugging or evaluating the system. For specific GPIO configurations and functions refer to registers 2, 3, 4, 5 and 6 in the device register map. GPIO pins are commonly used when there are multiple serializers on the same SMBus. In order to program individual settings into each serializer, they will each need to have a unique SMBus address. To reprogram multiple serializers on a single SMBus, configure the first serializer such that the SMBus lines are connected to the FPGA or host controller. The CS pin of the second serializer should be tied to GPIO0 of the first serializer, with the CS pin of the next serializer tied to GPIO0 of its preceding serializer. By holding all of the GPIO0 pins low, the first serializer’s address may now be reprogrammed by writing to register 0. The first serializer’s GPIO pin can now be asserted and the second serializer’s address may now be reprogrammed. HIGH SPEED COMMUNICATION MEDIA Using the serializer’s integrated de-emphasis blocks in combination with the DS32EL0124 or DS32ELX0124’s integrated equalization blocks allows data to be transmitted across a variety of media at high speeds. Factors that can limit device performance include excessive input clock jitter, noisy power rails, EMI from nearby noisy components and poor layout techniques. Although many cables contain wires of similar gauge and shielding, performance can vary greatly depending on the quality of the connector. REDUNDANCY APPLICATIONS The DS32ELX0421 has two high speed CML serial outputs. SMBus register control allows the device to use a single output exclusively, or both outputs simultaneously. This allows a single serializer to transmit data to two independant receiving systems, a primary and secondary endpoint. Some applications require a redundancy measure in case the primary signal path is compromised. The secondary output can be activated “on-the-go”, if a problem is detected on the primary link. See the Redundancy / Fail Over Configuration section located under Register Recipes. 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 LINK AGGREGATION Multiple DS32EL0421/DS32ELX0421 serializers and D32EL0124/DS32ELX0124 deserializers can be aggregated together if an application requires a data throughput of more than 3.125 Gbps. By utilizing the data valid signal of each device, the system can be properly deskewed to allow for a single cable, such as CAT-6, DVI-D, or HDMI, to carry data payloads beyond 3.125 Gbps. Link aggregation configurations can also be implemented in applications which require longer cable lengths. In these type of applications the data rate of each serializer and deserializer chipset can be reduced, such that the applications' net data throughput is still the same. Since each high speed channel is now operating at a fraction of the original data rate, the loss over the cable is reduced, allowing for greater lengths of cable to be used in the system. For more information regarding link aggregation please see SNLA109, Expanding the Payload with TI's FPGALink DS32ELX0421 and DS32ELX0124 Serializer and Deserializer. LAYOUT GUIDELINES It is important to follow good layout practices for high speed devices. The length of LVDS input traces should not exceed 40 inches. In noisy environment the LVDS traces may need to be shorter to prevent data corruption due to EMI. Noisy components should not be placed next to the LVDS or CML traces. The LVDS and CML traces must have a controlled differential impedance of 100 Ω. Do not place termination resistor at the LVDS inputs or CML outputs, the DS32EL0421 and DS32ELX0421 have internal termination resistors. It is recommended to avoid using vias. Vias create an impedance mismatch in the transmission line and result in reflections, which can greatly lower the maximum distance of the high speed data link. If vias are required, they should be placed symmetrically on each side of the differential pair. For more tips and detailed suggestions regarding high speed board layout principles, please consult the LVDS Owner’s Manual. 2.5V 3.3V 0.1 PF 0.1 PF 7, 15, 18, 25, 35 43 46 44 41 FPGA Host 42 39 40 37 38 1, 36 VCC33 48 45 + TXIN4 - VCC25 47 GND 49 TXOUT0 + TXIN3 - + - TXOUT1 + - 16 17 19 20 + TXIN2 - 3.3V + TXIN1 - VDDPLL 1: 28 22 PF + TXIN0 - DS32ELX0421 + TXCLKIN - VOD_CTRL 14 27 9.1 k: 1.5 k: LF_CP 30 31 LF_REF RESET 26 100 nF LOCK 32 GPIO0 3.3V 5 3 4 GPIO1 11 GPIO2 RS DC_B SDA 33 SCK 34 SMB_CS 6 3.3V Figure 11. Typical Interface Circuit Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 19 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics The eye diagrams shown below illustrate the typical performace of the DS32ELX0421/DS32EL0421 configured with RS = 0,DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost FPGA, which used an LMK03000C to generate the various clock frequencies. 20 Figure 12. CML Serial Differential Output 1.25 Gbps Figure 13. CML Serial Differential Output 3.125 Gbps Figure 14. CML Serial Singled Ended Output (+) 1.25 Gbps Figure 15. CML Serial Single Ended Output (+) 3.125 Gbps Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Register Map The register information for the serializer is shown in the table below. Some registers have been omitted or marked as reserved; these are for internal testing and should not be written to. Some register bits require an override bit to be set before they can be written to. Addr (Hex) Name 00 Device ID 01 Reset 02 03 04 GPIO0 Config GPIO1 Config GPIO2 Config Bits Field R/W Default Description R/W 57'h Some systems will use all 8 bits as the device ID. This will shift the value from 57’h to AE’h 7:1 SMBus Address 0 Reserved 0 7:5 Reserved 0 4 Analog Disable 3:1 Reserved 0 0 Software Reset 0 1: Reset the device. Does not affect device ID. 7:4 GPIO0 Mode R/W 0 0000: GP out register 0001: Link loss indicator 0011: TxCLKIN loss of signal 0100: TxCLKIN detect All others: Reserved 3:2 GPIO0 R Enable R/W 01'b 1 Input Enable R/W 0 0 Output Enable R/W 1'b 7:4 GPIO1 Mode R/W 0 0000: Power on reset 0001: GP out register 0010: PLL lock indicator 0011: TxIN0 loss of signal 0100: TxIN1 loss of signal 0101: TxIN2 loss of signal 0110: TxIN3 loss of signal 0111: TxIN4 loss of signal All others: Reserverd 3:2 GPIO1 R Enable R/W 01'b 00: Pullup/down disabled 01: Pulldown enabled 10: Pullup enabled 11: Reserved 1 Input Enable R/W 0 0 Output Enable R/W 1'b 7:4 GPIO2 Mode R/W 0 3:2 GPIO2 R Enable R/W 01'b 1 Input Enable R/W 0 0 Output Enable R/W 1'b R/W 0 1: Disables analog blocks. Power save feature 00: Pullup/down disabled 01: Pulldown enabled 10: Pullup enabled 11: Reserved 0: Input buffer disabled 1: Input buffer enabled 0: OutputTtri-State™ 1: Output enabled 0: Input buffer disabled 1: Input buffer enabled 0: Output Tri-State™ 1: Output enabled 0000: GP out register 0001: Always on clock out 0010: Parallel-to-serial clock out 0100: Digital clock out All others: Reserverd 00: Pullup/down disabled 01: Pulldown enabled 10: Pullup enabled 11: Reserved 0: Input buffer disabled 1: Input buffer enabled 0: Output Tri-State™ 1: Output enabled Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 21 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 Addr (Hex) Name 05 GP In 06 GP Out Bits www.ti.com Field R/W Default Description 7:3 Reserved 0 2 GP In 2 R 0 Input value on GPIO2 1 GP In 1 R 0 Input value on GPIO1 0 GP In 0 R 0 Input value on GPIO0 7:3 Reserved 2 GP Out 2 R/W 0 Output value on GPIO2 1 GP Out 1 R/W 0 Output value on GPIO1 0 GP Out 0 R/W 0 Output value on GPIO0 7:3 Reserved 2 Pin Override R/W 0 0: Pin values determine setting 1: Register overrides pin values 1:0 De-emphasis level R/W 0 00: 01: 10: 11: 7 NRZI enable R/W 0 1: Enable NRZI, if override bit is set 6 DV disable R/W 0 1: Disable Data Valid 5 Reserved R/W 0 4 Scrambler Enable R/W 0 1: Scrambler enable, requires override bit to change setting 3 DC Bal encoder bypass R/W 0 1: Bypass encoder, requires override bit to change setting 2 Training Sequence Enable R/W 0 1: Enable training sequence, requires override bit to change setting 1:0 Device Configuration R/W 0 MSB: Remote Sense enable, active low LSB: DC balance encoder enable, active low Requires override bit to change settings through registers. Normally controlled by pins. See Table 2 for more information. 7:5 Reserved 4 NRZ bypass override R/W 0 1: Unlock reg 21’h bit 7 3 Scrambler bypass override R/W 0 1: Unlock reg 21’h bit 4 2 DC Bal encoder bypass override R/W 0 1: Unlock reg 21’h bit 3 1 Training sequence enable override R/W 0 1: Unlock reg 21’h bit 2 0 Config pin override R/W 0 1: Unlock reg 21’h bits 1 and 0 TxCLKIN Delay Bypass R/W 0 0: TxCLKIN delay enable 1: Bypass TxCLKIN delay 0 07–1F Reserved 20 21 22 De-Emphasis Device Config Device Config Override 0 No de-emphasis Low Medium High 0 23 Reserved 24 LVDS Clock Delay 7 Enable 6:0 Reserved 0 25 Reserved 22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com Addr (Hex) 26 27 28 29 2A SNLS282F – MAY 2008 – REVISED APRIL 2013 Name Power Down Event Disable LVDS Operation Loss of Signal Status Event Status Bits Field R/W Default Description 7 Channel Reset R/W 0 1: Reset high speed channel. Self-clearing bit. 6 Clock Powerdown R/W 0 1: Power down parallel, parallel-to-serial, and always on clock 5 LVDS Clock enable R/W 1'b 0: Disable TxCLKIN 1: Enable TxCLKIN 4 TxIN4 Enable R/W 1'b 0: Disable TxIN4 1: Enable TxIN4 3 TxIN3 Enable R/W 1'b 0: Disable TxIN3 1: Enable TxIN3 2 TxIN2 Enable R/W 1'b 0: Disable TxIN2 1: Enable TxIN2 1 TxIN1 Enable R/W 1'b 0: Disable TxIN1 1: Enable TxIN1 0 TxIN0 Enable R/W 1'b 0: Disable TxIN0 1: Enable TxIN0 7:5 Reserved R/W 0 4 PLL Lock Disable R/W 0 0: Count clock errors 1: Clock error count disabled 3 FIFO Error Disable R/W 0 0: Count FIFO erros 1: FIFO error count disabled 2 Parallel Clock Detect Disable R/W 0 0: Count clock detect errors 1: Clock detect count disabled 1 Clock Loss of Signal Disable R/W 0 0: Count clock los of signal errors 1: Clock loss of signal count disabled 0 Data Loss of Signal Disable R/W 0 0: Count data los of signal errors 1: Clock data of signal count disabled 7:2 Reserved 1 LVDS Loss of Signal Preset R/W 0 1: Preset signal for LVDS loss of signal register 0 LVDS Loss of Signal Reset R/W 0 1: Clear signal for LVDS loss of signal register 7:6 Reserved 5 Clock Loss of Signal R 0 0: Clock present 1: No clock present on TxCLKIN 4:0 Data Loss of Signal R 0 0: Data present 1: No data present on TxIN4:0 7:4 Reserved 3 TxCLKIN Detect 2 Reserved 1:0 Link Detect 1:0 0 0 0 R/W 0 0: TxCLKIN not detected 1: TxCLKIN detected 0 R/W 0 0: Link not detected 1: Link detected Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 23 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 Addr (Hex) Name 2B Event Config Bits www.ti.com Field R/W Default Description 7 Reserved 6 PLL Lock Event R/W 0 0: Count PLL lock events 1: Do not count PLL lock events 5 Link Event R/W 0 0: Count link events 1: Do not count link events 4 Loss of Signal Event R/W 0 0: Count loss of signal events 1: Do not count loss of signal events 3 Event Count Select R/W 0 0: Select PLL event count for reading 1: Select link event count for reading 2 Clear PLL Error Count R/W 0 1: Reset PLL error count. Self clearing bit. 1 Clear Link Error Count R/W 0 1: Reset link error count. Self clearing bit. 0 Enable Count R/W 0 0: Disable event counters 1: Enable event counters Event Count 7:0 Event Counter R 0 Analog Driver 7 Reserved 6 Reverse Data Order R/W 0 5:2 Reserved R/W 0 1 Link Detect 1 R/W 0 Link detect value for channel 1 0 Link Detect 0 R/W 0 Link detect value for channel 0 7:6 Reserved 5 Output Termination R/W 1'b 0: 75 Ω terminations 1: 50 Ω terminations 4 Link Start R/W 1'b 0: Start when TxOUT0 or TxOUT1 link 1: Start when TxOUT0 and TxOUT1 linke 3 Link Stop R/W 1'b 0: Stop when TxOUT0 and TxOUT1 both links invalid 1: Stop when TxOUT0 or TxOUT1 break link, either link is invalid 2 TxOUT Override R/W 0 0: TxOUT0 enabled by default, TxOUT1_en pin controls channel1 1: Override enable of TxOUT0 and TxOUT1 1 TxOUT1 Enable R/W 0 0: TxOUT1 disabled 1: TxOUT1 enabled For proper operation of TxOUT1, the TxOUT1_EN pin must be held high. 0 TxOOUT0 Enable R/W 0 0: TxOUT0 disabled 1: TxOUT0 enabled 7:5 TxCLKIN Delay R/W 011’b 4:0 Reserved 7:3 Reserved 2:0 Amplitude Adjust 2C 0 2D Reserved 2E 2F 30 Tx Config Clock Delay 0 0: Normal 1: Reverse output data order 0 000: Min clock delay, 350 ps 011: 725 ps 111: Max clock delay, 1225 ps 00010’b 31–68 Reserved 69 24 Output Amplitude Adjust Submit Documentation Feedback 0 R/W 011’b 000: 001: 010: 011: 100: 101: 110: 111: Level Level Level Level Level Level Level Level 7 8 (Highest output) 5 6 (Normal output) 4 3 2 1 (Lowest output) Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 DS32EL0421, DS32ELX0421 www.ti.com SNLS282F – MAY 2008 – REVISED APRIL 2013 Register Recipes Many features of the serializer contained within the SMBus registers require multiple writes to configure and enable. This methodology was implemented to prevent accidental register writes from causing undesired device behavior. Several recipes for common features are listed below. When experimenting with other SMBus register features, be sure to read through the register map for override and enable bits. SCRAMBLER OVERRIDE CONTROL The scrambler’s default settings are described in the DEVICE CONFIGURATION section. However, the scrambler’s setting can be overridden if desired. Reg 22’h, write 08’h Reg 21’h, write to bit 3 to enable/disable 75Ω MODE The serializer can be programmed to interface with 75Ω media by using the recipe shown below. The inverting serial output should be terminated when interfacing with single ended media. Reg 2F’h, write 0 to bit 5 OUTPUT CHANNEL MUX CONTROL DS32ELX0421 only. TxOUT0 is the output channel enabled by default. By using the external pin TxOUT1_EN, TxOUT1 will be activated along with TxOUT0. If an application requires that only one channel be active at a time, the following recipe allows for each channel to be enabled or disabled independent of the other. Reg 2F’h, write 1’b to bit 2 Reg 2F’h, write to bits 1 or 0 to control the output channels OUTPUT THE SERIAL CLOCK ON GPIO2 It is very helpful to be able to monitor high speed communication systems and observe their signal integrity. Generally, this is done with a high speed real time oscilloscope or a sampling oscilloscope. Sampling oscilloscopes require a reference clock to trigger on. The following recipe can be used to bring out the serial clock on GPIO2 to provide a trigger for sampling oscilloscopes. Reg 04’h, write 21’h Power Save Mode When a system does not need to transmit high speed data from the DS32EL0421 or DS32ELX0421, the power consumption of the device can be managed as described in the POWER MANAGEMENT section on the Functional Description page. The following recipe powers down many of the analog and digital blocks in the serializer, but leaves the SMBus module operational. Please note that in order to resume normal operation the recipe below will have to be unwritten. Reg 01'h, write 10'h Reg 26'h, write 40'h Redundancy / Fail Over Configuration DS32ELX0421 only. Implementing a redundancy system with the DS32ELX0421 can be done in several ways. One method would be to program the redundancy or fail over logic into the host device or FPGA. The recipe below will describe a different method, for which a DS32ELX0421 will communicate to two different DS32EL0124 deserializers. The recipe below will configure the DS32ELX0421 serializer to automatically switch to the alternate output when the current high speed link fails. Configure all device with Remote Sense enabled either by pin or register control. Pull TxOUT1_EN pin high reg 2F'h, write 2D'h Reg 2F'h, write 28'h Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 Submit Documentation Feedback 25 DS32EL0421, DS32ELX0421 SNLS282F – MAY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 26 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 25 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS32EL0421 DS32ELX0421 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS32EL0421SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32EL0421 DS32EL0421SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32EL0421 DS32EL0421SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32EL0421 DS32ELX0421SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 32ELX0421 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing DS32EL0421SQ/NOPB WQFN RHS 48 DS32EL0421SQE/NOPB WQFN RHS DS32EL0421SQX/NOPB WQFN RHS DS32ELX0421SQE/NOPB WQFN RHS SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS32EL0421SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS32EL0421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS32EL0421SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 DS32ELX0421SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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