Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DESCRIPTION The MH32S72AQJA is 33554432 - word x 72-bit Sy nchronous DRAM module. This consist of eighteen industry standard 32M x 4 Sy nchronous DRAMs in TSOP. The TSOP on a card edge dual in-line package prov ides any application where high densities and large of quantities memory are required. This is a socket-ty pe memory m odule ,suitable f or easy interchange or addition of m odule. 85pin 1pin 94pin 10pin 95pin 11pin 124pin 40pin 125pin 41pin 168pin 84pin FEATURES Max. Frequency CLK Access Time [component level] -7 100MHz 6ns (CL = 2) -8 100MHz 6ns (CL = 3) Utilizes industry standard 32M X 4 Synchronous DRAMs in TSOP package , industry standard Resistered buffer in TSSOP package and industry standard PLL in TSSOP package Single 3.3V +/- 0.3V supply LVTTL Interface Burst length 1/2/4/8/Full Page(programmable) Burst W rite / Single W rite(programmable) Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycles every 64ms Discrete IC and module design conform to PC/100 specification. (module Spec. Rev. 1.2 and SPD 1.2A) APPLICATION Main memory unit for computers, Microcomputer memory. MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 1 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. 1 VSS 43 VSS 85 2 DQ0 44 NC PIN NAME PIN NO. PIN NAME VSS 127 VSS 86 DQ32 128 CKE0 3 DQ1 45 /S2 87 DQ33 129 NC 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VDD 48 NC 90 VDD 132 NC 7 DQ4 49 VDD 91 DQ36 133 VDD 8 DQ5 50 NC 92 DQ37 134 NC 9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref,NC 104 DQ47 146 Vref,NC 21 CB0 63 CKE1 105 CB4 147 REGE 22 CB1 64 VSS 106 CB5 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 VDD 68 VSS 110 VDD 152 VSS 27 /WE 69 DQ24 111 /CAS 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 /S0 72 DQ27 114 NC 156 DQ59 /RAS 157 VDD VSS 158 DQ60 31 NC 73 VDD 115 32 VSS 74 DQ28 116 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CK2 121 A9 163 CK3 38 A10 80 NC 122 BA0 164 NC 39 BA1 81 WP 123 A11 165 SA0 40 VDD 82 SDA 124 VDD 166 SA1 41 42 VDD CK0 83 84 SCL VDD 125 126 CK1 167 168 SA2 VDD NC NC = No Connection MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 2 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Add CKE0 /S0,2 DQM0-7 /W /RAS /CAS RCKE0 R/S0,2 RDQM0-7 DQ0 DQ1 10K VDD REGE DQ32 DQ33 DQ2 DQ3 DQ4 DQ5 D0 DQ34 DQ35 DQ36 DQ37 D9 DQ6 DQ7 D1 DQ38 DQ39 D10 DQ8 DQ9 DQ10 DQ40 DQ41 DQ42 D2 DQ11 DQ12 DQ13 DQ14 DQ15 DQ43 DQ44 DQ45 DQ46 DQ47 D3 CB5 CB6 D4 CB3 CB7 DQ16 DQ48 DQ17 DQ18 DQ19 DQ20 DQ21 D6 DQ54 DQ55 DQ24 DQ25 DQ56 DQ57 D7 DQ26 DQ27 DQ58 DQ59 DQ28 DQ29 DQ60 DQ61 D8 RCKE0 R/S0 R/S2 Terminated D0-17 D0-4,9-13 D5-8,14-17 MIT-DS-0371-0.2 D15 D16 D17 DQ62 DQ63 SERIAL PD PLL CK1 - CK3 D14 DQ52 DQ53 From PLL CK0 D13 DQ49 DQ50 DQ51 D5 DQ22 DQ23 DQ30 DQ31 D12 CB4 CB0 CB1 CB2 D11 RDQM RDQM RDQM RDQM RDQM RDQM RDQM RDQM 0 1 2 3 4 5 6 7 D0-1 D2-4 D5-6 D7-8 D9-10 D11-13 D14-15 D16-17 MITSUBISHI ELECTRIC SCL WP 47K A0 A1 SDA A2 SA0 SA1 SA2 VDD D0 to D17 VSS D0 to D17 17/Mar./2000 3 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM PIN FUNCTION Input Master Clock:All other inputs are referenced to the rising edge of CK CKE0 Input Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low. /S0,2 Input Chip Select: When /S is high,any command means No Operation. /RAS,/CAS,/W Input Combination of /RAS,/CAS,/W defines basic commands. Input A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-10.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged. Input Bank Address:BA0,1 is not simply BA.BA0,1 specifies the bank to which a command is applied.BA must be set with ACT,PRE,READ,WRITE commands CK0 A0-11 BA0-1 DQ0-63 CB0-7 DQM0-7 Vdd,Vss REGE MIT-DS-0371-0.2 Input/Output Data In and Data out are referenced to the rising edge of CK Input Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle. Power Supply Power Supply for the memory mounted module. Output Register enable:When REGE is low,All control signals and address are buffered. (Buffer mode) When REGE is high,All control and address are latched. (Latch mode) MITSUBISHI ELECTRIC 17/Mar./2000 4 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM BASIC FUNCTIONS The MH32S72AQJA provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table. CK /S Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Ref resh Option @ref resh command A10 Precharge Option @precharge or read/write command def ine basic commands Activate(ACT) [/RAS =L, /CAS = /WE =H] ACT command activates a row in an idle bank indicated by BA. Read(READ) [/RAS =H,/CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA). Write(WRITE) [/RAS =H, /CAS = /WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA). Precharge(PRE) [/RAS =L, /CAS =H,/WE =L] PRE command deactivates the active bank indicated by BA. This command also term inates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H] PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 5 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM COMMAND TRUTH TABLE CKE CKE n-1 n /RAS /CAS /WE BA0,1 A11 COMMAND MNEMONIC Deselect No Operation DESEL NOP H H X X H L X H X H X H X X X X X X X X ACT H X L L H H V V V V Single Bank Precharge Precharge All Bank PRE PREA H H X X L L L L H H L L V X X X L H X X Column Address Entry & Write WRITE H X L H L L V V L V Column Address Entry & Write with AutoPrecharge WRITEA H X L H L L V V H V Column Address Entry & Read READ H X L H L H V V L V Column Address Entry & Read with Auto Precharge READA H X L H L H V V H V Auto-Refresh Self-Refresh Entry Self-Refresh Exit REFA REFS REFSX Burst Terminate Mode Register Set TERM MRS H H L L H H H L H H X X L L H L L L L L X H H L L L X H H L H H X H L L X X X X X L X X X X X L X X X X X L X X X X X V*1 Row Adress Entry & Bank Activate /S A10 A0-9 H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number NOTE: 1.A7-9 = 0, A0-6 = Mode Address MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 6 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE /S IDLE H L X H X H X H X X L H H L BA L H L X BA,CA,A10 L L H H BA,RA ACT L L H L L L L H BA,A10 X PRE/PREA REFA L L L L H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X L L L L H X X X X DESEL NOP(Continue Burst to END) L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst ROW ACTIVE READ /RAS /CAS /WE Address Command Current State Op-Code, Mode-Add Op-Code, Mode-Add DESEL NOP TBST Action NOP NOP ILLEGAL*2 READ/WRITE ILLEGAL*2 MRS READ/READA Bank Active,Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 Begin Read,Latch CA, Determine Auto-Precharge WRITE/ Begin Write,Latch CA, WRITEA Determine Auto-Precharge REFA ILLEGAL MRS ILLEGAL Terminate Burst,Latch CA, L H L H BA,CA,A10 READ/READA Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, L H L L BA,CA,A10 WRITE/WRITEA Begin Write,Determine AutoPrecharge*3 MIT-DS-0371-0.2 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L Op-Code, Mode-Add MITSUBISHI ELECTRIC Bank Active/ILLEGAL*2 Terminate Burst,Precharge REFA ILLEGAL MRS ILLEGAL 17/Mar./2000 7 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE(continued) Current State WRITE READ with AUT O PRECHARGE WRITE with AUT O PRECHARGE /S H L L /RAS /CAS X X H H H H /WE Address X X H X L BA Command Action DESEL NOP(Continue Burst to END) NOP NOP(Continue Burst to END) TBST Terminate Burst Terminate Burst,Latch CA, READ/READA Begin Read,Determine AutoPrecharge*3 L H L H BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA ACT L L L L H L L H BA,A10 X PRE/PREA REFA L L L L Op-Code, Mode-Add H L L L X H H H X H H L X H L H X X BA BA,CA,A10 L H L L BA,CA,A10 L L H H BA,RA DESEL NOP TBST READ/READA WRITE/ WRITEA ACT L L H L BA,A10 PRE/PREA L L L H X Op-Code, Mode-Add X X WRITE/ WRITEA MRS NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 MRS ILLEGAL L L H L L L X H H H X H H L X H L H L H L L BA,CA,A10 L L H H BA,RA ACT L L L L H L L H BA,A10 X PRE/PREA REFA L L L L Op-Code, Mode-Add DESEL NOP TBST READ/READA WRITE/ WRITEA MITSUBISHI ELECTRIC ILLEGAL ILLEGAL L MIT-DS-0371-0.2 Terminate Burst,Precharge ILLEGAL REFA L BA BA,CA,A10 Terminate Burst,Latch CA, Begin Write,Determine AutoPrecharge*3 Bank Active/ILLEGAL*2 MRS NOP(Continue Burst to END) NOP(Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active/ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL 17/Mar./2000 8 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE(continued) /S PRE - H X X X X DESEL NOP(Idle after tRP) CHARGING L H H H X NOP NOP(Idle after tRP) L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT L L H L BA,A10 PRE/PREA L L L H X L L L L ROW H X X X X DESEL NOP(Row Active after tRCD ACT IVATING L H H H X NOP NOP(Row Active after tRCD L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L WRITE RE- H X X X X DESEL NOP COVERING L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X L L L L MIT-DS-0371-0.2 /RAS /CAS /WE Command Current State Address Action READ/WRITE ILLEGAL*2 Op-Code, Mode-Add ILLEGAL*2 NOP*4(Idle after tRP) REFA ILLEGAL MRS ILLEGAL READ/WRITE ILLEGAL*2 Op-Code, Mode-Add REFA ILLEGAL MRS ILLEGAL READ/WRITE ILLEGAL*2 Op-Code, Mode-Add MITSUBISHI ELECTRIC REFA ILLEGAL MRS ILLEGAL 17/Mar./2000 9 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE(continued) Current State /S /RAS /CAS /WE Address RE- H X X X X DESEL NOP(Idle after tRC) FRESHING L H H H X NOP NOP(Idle after tRC) L H H L BA TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL MODE H X X X X DESEL NOP(Idle after tRSC) REGISTER L H H H X NOP NOP(Idle after tRSC) SETTING L H H L BA TBST ILLEGAL L H L X BA,CA,A10 L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL L L L L MRS ILLEGAL Op-Code, Mode-Add Op-Code, Mode-Add Command Action READ/WRITE ILLEGAL READ/WRITE ILLEGAL ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Mus t satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state.May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed. MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 10 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM FUNCTION TRUTH TABLE FOR CKE Current State CKE n-1 CKE n /S SELF - H X X X REFRESH*1 L H H L H L /RAS /CAS Action /WE Add X X X INVALID X X X X Exit Self-Refresh(Idle after tRC) L H H H X Exit Self-Refresh(Idle after tRC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh) POWER H X X X X X X INVALID DOWN L H X X X X X Exit Power Down to Idle L L X X X X X NOP(Maintain Self-Refresh) ALL BANKS H H X X X X X Refer to Function Truth Table IDLE*2 H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down ANY STATE H H X X X X X Refer to Function Truth Table other than H L X X X X X Begin CK0 Suspend at Next Cycle*3 listed above L H X X X X X Exit CK0 Suspend at Next Cycle*3 L L X X X X X Maintain CK0 Suspend ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care NOTES: 1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All banks idle State. 3. Mus t be legal command. MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 11 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM POWER ON SEQUENCE Before s tarting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs. 2. Maintain s table power, stable clock, and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. CK /S BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RAS /CAS 0 0 0 0 WM 0 0 LTMODE BT BL /WE BA0,1 A11-0 CL 000 001 010 LATENCY MODE WRITE MODE 0 1 1 1 1 1 0 0 1 1 0 1 MIT-DS-0371-0.2 1 0 1 0 1 /CAS LATENCY BURST LENGTH R R 2 3 R R R R BURST TYPE 0 0 0 0 1 1 1 1 V BL BT= 0 BT= 1 0 0 1 1 0 0 1 1 1 2 4 8 R R R FP 1 2 4 8 R R R R 0 1 0 1 0 1 0 1 0 1 SEQUENTIAL INTERLEAVED R:Reserved for Future Use FP: Full Page BURST SINGLE BIT MITSUBISHI ELECTRIC 17/Mar./2000 12 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM CK Command Read Write Y Y Address Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 D0 Q3 D1 D2 D3 Burst Length Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 Interleaved Sequential 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 13 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Condition Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V VI Input Voltage with respect to Vss -0.5 ~ 4.6 V VO Output Voltage with respect to Vss -0.5 ~ 4.6 V IO Output Current 50 mA Pd Power Dissipation 20.7 W Topr Operating Temperature 0 ~ 70 °C Tstg Storage Temperature -45 ~ 100 °C Ta=25°C RECOM M ENDED OPERATING CONDITION (Ta=0 ~ 70°C, unless otherwise noted) Limits Parameter Symbol Unit Typ. Max. 3.3 3.6 V 0 V Vdd Supply Voltage Min. 3.0 Vss Supply Voltage 0 VIH High-Level Input Voltage all inputs 2.0 0 Vdd+0.3 VIL Low-Level Input Voltage all inputs -0.3 0.8 V V Note) 1:VIH(max)=5.5V f or pulse width less than 10ns. 2.VIL(min)=-1.0 f or pulse width less than 10ns. CAPACITANCE (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Parameter Test Condition Symbol CI(A) Input Capacitance, address pin @1MHz CI(C) Input Capacitance, control pin 1.4V bias CI(K) Input Capacitance, CK0 pin 200mV swing Input Capacitance, I/O pin CI/O MIT-DS-0371-0.2 MITSUBISHI ELECTRIC Limits(max.) Unit 25 25 pF pF 35 16.5 pF pF 17/Mar./2000 14 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Symbol Parameter Test Condition Limits (max) Unit -7,-8 operating current one bank activ e (discrete) tRC=min.tCLK=min, BL=1,CL=3 1910 mA CKE=L,tCLK=15ns, /CS>Vcc-0.2V Icc2PS CKE=CLK=L, /CS>Vcc-0.2V Icc2N CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V Icc2NS CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed) 236 218 650 470 mA 740 560 mA burst current auto-refresh current Icc3N CKE=H,tCLK=15ns Icc3NS CKE=H,CLK=L tCLK=min, BL=4, CL=3,all banks activ e(discerte) Icc4 tRC=min, tCLK=min Icc5 self-refresh current Icc6 Icc1 precharge stanby current in power-down mode precharge stanby current in non power-down mode active stanby current in non power-down mode one bank activ e (discrete) Icc2P 2180 3080 236 CKE <0.2V mA mA mA mA mA mA mA Note) 1:Icc(max) is specif ied at the output open condition. AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted) Limits Unit Min. Max. VOH(DC) High-Level Output Voltage(DC) IOH=-2mA V 2.4 VOL(DC) Low-Level Output Voltage(DC) IOL=2mA 0.4 V Off-stare Output Current Q floating VO=0 ~ Vdd -10 10 uA IOZ Input Current Ii VIH=0 ~ Vdd+0.3V -10 10 uA Symbol MIT-DS-0371-0.2 Parameter Test Condition MITSUBISHI ELECTRIC 17/Mar./2000 15 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM AC TIMING REQUIREMENTS (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V LATCH MODE Limits Symbol Parameter -7 Min. CL=3 CL=4 tCLK CK cycle time tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tSRX tPDE tREF CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley tim e Mode Register Set Cycle time Self Refresh Exit time Power Down Exit tim e Refresh Interval time Min. 10 13 10 3 3 1 2 1 70 20 50 20 20 20 20 10 10 3 3 1 2 1 70 20 50 20 20 20 20 10 10 10 100000 10 64 CK 1.4V Signal 1.4V MIT-DS-0371-0.2 MITSUBISHI ELECTRIC Unit -8 Max. Max. 10 100000 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Any AC timing is referenced to the input signal crossing through 1.4V. 17/Mar./2000 16 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM BUFFER MODE Limits Symbol Parameter tCLK CK cycle time tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tSRX tPDE tREF CK High pulse width CK Low pilse width Transition time of CK Input Setup time(all inputs) Input Hold time(all inputs) Row cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Deley tim e Mode Register Set Cycle time Self Refresh Exit time Power Down Exit tim e Refresh Interval time Min. Max. Min. CL=2 CL=3 Unit -8 -7 10 13 10 3 3 1 7 0 70 20 50 20 20 20 20 10 10 3 3 1 7 0 70 20 50 20 20 20 20 10 10 10 100000 10 Max. 10 100000 64 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms SWITCHING CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) LATCH MODE Limits -7 Symbol Parameter Min. tAC tOH tOLZ tOHZ Access time from CK Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK CL=3 CL=4 -8 Max. Min. Unit Max. 6 7 6 6 ns 3 3 ns 0 0 ns 3 6 3 6 ns Note) 1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter. MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 17 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM BUFFER MODE Limits Symbol Parameter tAC tOH tOLZ tOHZ -8 -7 Min. Access time from CK Max. Min. Unit Max. CL=2 6 7 CL=3 6 6 Output Hold time from CK Delay time, output low impedance from CK Delay time, output high impedance from CK ns 3 3 ns 0 0 ns 3 3 6 6 ns Note) 1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter. Output Load Condition CK 1.4V V OUT 50pF DQ 1.4V Output Timing Measurement Ref erence Point 1.4V CK DQ 1.4V tAC MIT-DS-0371-0.2 tOH tOHZ MITSUBISHI ELECTRIC 17/Mar./2000 18 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (single bank) 1 0 2 3 5 4 7 6 BL=4,Buffer mode(REGE="L") 9 8 11 10 12 13 14 15 17 16 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQM A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE D0 DQ ACT#0 D0 WRITE#0 D0 D0 D0 PRE#0 ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 19 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (dual bank) 1 0 3 2 5 4 7 6 BL=4,Buffer mode(REGE="L") 9 8 11 10 13 12 15 14 17 16 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 D1 D1 0 1 2 Y 0 REGE D0 DQ ACT#0 D0 WRITE#0 ACT#1 D0 D0 D1 PRE#0 WRITE#1 D1 D0 ACT#0 D0 D0 D0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 20 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (single bank) 1 0 2 3 5 4 7 6 BL=4,Lacth mode(REGE="H") 9 8 11 10 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQM A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE D0 DQ ACT#0 WRITE#0 D0 D0 D0 PRE#0 D0 ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 21 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM WRITE CYCLE (dual bank) 1 0 3 2 5 4 7 6 BL=4,Latch mode(REGE="H") 9 8 11 10 13 12 15 14 17 16 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQM A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 0 D0 D1 1 2 Y 0 REGE D0 DQ ACT#0 WRITE#0 ACT#1 D0 D0 D1 PRE#0 WRITE#1 D1 D1 ACT#0 D0 D0 D0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 22 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (single bank) 1 0 2 3 5 4 7 6 BL=4,CL=3,Buffer mode(REGE="L") 9 8 11 10 12 13 14 15 17 16 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE CL=3 Q0 DQ ACT#0 READ#0 Q0 Q0 Q0 PRE#0 Q0 ACT#0 Q0 READ#0 READ to PRE ≥ BL allows full data out Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 23 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (dual bank) 1 0 3 2 4 5 BL=4,CL=3,Buffer mode(REGE="L") 7 6 9 8 11 10 13 12 15 14 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =2 A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 0 1 2 Q1 Q1 Q1 Y 0 REGE CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 PRE#0 READ#1 Q1 Q0 READ#0 ACT#0 PRE#1 ACT#2 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 24 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (single bank) 1 0 2 3 5 4 7 6 BL=4, CL=3,Latch mode(REGE="H") 9 8 11 10 12 13 14 15 17 16 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =3 A0-9 X A10 X X A11 X X BA0,1 0 Y X 0 0 0 Y 0 REGE CL=3 Q0 DQ ACT#0 READ#0 Q0 Q0 Q0 PRE#0 Q0 ACT#0 Q0 READ#0 READ to PRE ≥ BL allows full data out Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 25 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM READ CYCLE (dual bank) 1 0 3 2 4 5 BL=4,CL=3,Latch mode(REGE="H") 7 6 9 8 11 10 13 12 15 14 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency =3 A0-9 X X A10 X A11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 0 0 1 2 Q1 Q1 Q1 Y 0 REGE CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 PRE#0 READ#1 Q1 Q0 READ#0 ACT#0 PRE#1 ACT#2 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 26 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst WRITE (multi bank) with AUTO-PRECHARGE 0 1 2 4 3 6 5 8 7 BL=4,Buffer mode(REGE="L") 10 9 11 12 14 13 16 15 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD /CAS tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP /WE CKE DQM A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 Y Y 0 X 1 Y X 0 0 1 D1 D0 D0 Y 1 REGE D0 DQ ACT#0 ACT#1 D0 D0 D0 WRITE#0 with AutoPrecharge D1 D1 D1 ACT#0 WRITE#1 with AutoPrecharge D0 WRITE#0 ACT#1 D0 D1 WRITE#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 27 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst WRITE (multi bank) with AUTO-PRECHARGE 0 1 2 4 3 6 5 8 7 BL=4,Latch mode(REGE="H") 10 9 12 11 14 13 16 15 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD /CAS tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP /WE CKE DQM A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 Y Y 0 X 1 Y 0 0 X Y 1 1 REGE D0 DQ ACT#0 ACT#1 D0 D0 WRITE#0 with AutoPrecharge D0 D1 D1 D1 D1 ACT#0 WRITE#1 with AutoPrecharge D0 D0 WRITE#0 ACT#1 D0 D0 WRITE#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 28 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst READ (multi bank) with AUTO-PRECHARGE 0 1 2 4 3 5 6 8 7 BL=4,Buffer mode(REGE="L") 10 9 12 11 14 13 16 15 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL+tRP BL+tRP /WE CKE DQM DQM read latency =2 Y Y Y A0-9 X X A10 X X X X A11 X X X X BA0,1 0 1 0 X 1 0 0 X Y 1 1 REGE CL=3 CL=3 Q0 DQ ACT#0 ACT#1 READ#0 with Auto-Precharge Q0 Q0 CL=3 Q0 Q1 Q1 ACT#0 READ#1 with Auto-Precharge Q1 Q1 Q0 Q0 READ#0 ACT#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 29 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Burst READ (multi bank) with AUTO-PRECHARGE 0 1 2 4 3 5 6 8 7 BL=4,Latch mode(REGE="H") 10 9 12 11 14 13 16 15 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL+tRP BL+tRP /WE CKE DQM DQM read latency =3 A0-9 X X Y Y A10 X X X X A11 X X X X BA0,1 0 1 0 X 1 Y 0 0 X Y 1 1 REGE CL=3 CL=3 Q0 DQ ACT#0 ACT#1 READ#0 with Auto-Precharge Q0 Q0 CL=3 Q0 Q1 Q1 ACT#0 READ#1 with Auto-Precharge Q1 Q1 Q0 Q0 READ#0 ACT#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 30 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Write (multi bank) 1 0 3 2 5 4 7 6 9 8 BL=4,Buffer mode(REGE="L") 11 10 12 13 14 15 17 16 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE D0 DQ ACT#0 D0 WRITE#0 ACT#1 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D0 D0 D0 WRITE#0 WRITE#0 WRITE#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 31 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Write (multi bank) 1 0 3 2 5 4 7 6 9 8 BL=4,Latch mode(REGE="H") 11 10 12 13 15 14 17 16 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE D0 DQ ACT#0 WRITE#0 ACT#1 D0 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D0 D0 WRITE#0 WRITE#0 WRITE#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 32 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Read (multi bank) 1 0 3 2 4 5 7 6 9 8 BL=4,Buffer mode(REGE="L") 11 10 13 12 14 15 17 16 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE CL=3 Q0 DQ ACT#0 READ#0 ACT#1 CL=3 CL=3 Q0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 READ#0 READ#0 READ#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 33 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Page Mode Burst Read (multi bank) 1 0 3 2 4 5 7 6 9 8 BL=4,Latch mode(REGE="H") 11 10 13 12 14 15 17 16 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=3 A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 REGE CL=3 Q0 DQ ACT#0 READ#0 ACT#1 CL=3 CL=3 Q0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 READ#0 READ#0 READ#1 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 34 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Write / Read 0 1 2 4 3 6 5 8 7 BL=4,Buffer mode(REGE="L") 10 9 12 11 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y Y 0 0 0 1 0 REGE CL=3 D0 DQ D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 ACT#0 READ#0 WRITE#0 WRITE#0 WRITE#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 35 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Write / Read 0 1 2 4 3 6 5 8 7 BL=4,Latch mode(REGE="H") 10 9 12 11 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQM A0-9 X X A10 X X A11 X X BA0,1 0 1 Y Y Y Y Y 0 0 0 1 0 REGE CL=3 D0 DQ D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 ACT#0 READ#0 WRITE#0 WRITE#0 WRITE#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 36 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Read / Write 1 0 3 2 4 5 7 6 BL=4,Buffer mode(REGE="L") 9 8 11 10 12 13 14 15 17 16 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=2 A0-9 X X A10 X X A11 X X BA0,1 0 1 DQ Y Y Y Y Y Y 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 D0 REGE ACT#0 READ#0 WRITE#0 READ#0 READ#0 READ#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 37 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Read / Write 1 0 3 2 4 5 7 6 BL=4,Latch mode(REGE="H") 9 8 11 10 12 13 14 15 17 16 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM DQM read latency=3 A0-9 X X A10 X X A11 X X BA0,1 0 1 DQ Y Y Y Y Y Y 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 REGE ACT#0 READ#0 WRITE#0 READ#0 READ#0 READ#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 38 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Precharge 0 1 2 4 3 6 5 8 7 BL=4,Buffer mode(REGE="L") 10 9 11 12 13 14 16 15 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X Y A10 X X X A11 X X X BA0,1 0 1 0 D0 DQ Y D0 D0 D0 X 1 0 D1 D1 1 1 Y 1 D1 D1 D1 REGE ACT#0 WRITE#0 ACT#1 PRE#0 WRITE#1 PRE#1 Burst Write is not interrupted by Precharge of the other bank. ACT#1 WRITE#1 Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 39 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Write Interrupted by Precharge 0 1 2 4 3 6 5 8 7 BL=4,Latch mode(REGE="H") 10 9 11 12 13 14 16 15 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0-9 X X Y Y A10 X X X A11 X X X BA0,1 0 1 0 D0 DQ D0 D0 X 1 0 1 D0 D1 D1 1 Y 1 D1 D1 D1 REGE ACT#0 WRITE#0 ACT#1 PRE#0 WRITE#1 PRE#1 Burst Write is not interrupted by Precharge of the other bank. ACT#1 WRITE#1 Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 40 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Precharge 0 2 1 4 3 5 6 8 7 BL=4,Buffer mode(REGE="L") 10 9 11 12 13 14 16 15 17 CLK /CS tRRD tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency=2 A0-9 X X Y Y A10 X X X A11 X X X BA0,1 0 1 0 Q0 DQ X 1 0 1 Q0 Q0 Q0 1 Q1 Y 1 Q1 REGE ACT#0 READ#0 ACT#1 PRE#0 READ#1 PRE#1 Burst Read is not interrupted by Precharge of the other bank. ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 41 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Read Interrupted by Precharge 0 2 1 4 3 5 6 8 7 BL=4,Latch mode(REGE="H") 10 9 11 12 13 14 16 15 17 CLK /CS tRRD tRP /RAS tRCD tRCD /CAS /WE CKE DQM DQM read latency=3 A0-9 X X Y Y A10 X X X A11 X X X BA0,1 0 1 0 Q0 DQ X 1 0 1 Q0 Q0 Q0 1 Q1 Y 1 Q1 REGE ACT#0 READ#0 ACT#1 PRE#0 READ#1 PRE#1 Burst Read is not interrupted by Precharge of the other bank. ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 42 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Mode Register Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 17 16 CLK /CS tRSC tRC /RAS tRCD /CAS /WE CKE DQM M A0-9 X A10 X A11 X 0 BA0,1 0 Y 0 D0 DQ D0 D0 D0 REGE Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 43 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Auto-Refresh @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 13 12 14 15 16 17 CLK /CS tRC /RAS tRCD /CAS /WE CKE DQM A0-9 X A10 X A11 X BA0,1 0 Y 0 D0 DQ D0 D0 D0 REGE Auto-Refresh ACT#0 Before Auto-Refresh, all banks must be idle state. After tRC from Auto-Refresh, all banks are idle state. WRITE#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 44 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Self-Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CLK can be stopped tRC /CS /RAS /CAS /WE tSRX CKE CKE must be low to maintain Self-Refresh DQM A0-9 X A10 X A11 X BA0,1 0 DQ REGE Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. Self-Refresh Exit ACT#0 After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 45 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Write Mask @BL=4 0 2 1 4 3 BL=4,Buffer mode(REGE="L") 6 5 8 7 9 10 12 11 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked D0 DQ D0 D0 D0 masked D0 D0 D0 REGE ACT#0 WRITE#0 WRITE#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 46 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Write Mask @BL=4 0 2 1 4 3 6 5 BL=4,Latch mode(REGE="H") 8 7 10 9 12 11 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked D0 DQ D0 D0 D0 masked D0 D0 D0 REGE ACT#0 WRITE#0 WRITE#0 WRITE#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 47 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Read Mask @BL=4 CL=3 0 2 1 4 3 5 6 BL=4,Buffer mode(REGE="L") 8 7 10 9 12 11 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=2 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked Q0 DQ Q0 Q0 Q0 masked Q0 Q0 Q0 REGE ACT#0 READ#0 READ#0 READ#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 48 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM DQM Read Mask @BL=4 CL=3 0 2 1 4 3 5 6 BL=4,Latch mode(REGE="H") 8 7 10 9 12 11 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=3 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y Y 0 0 0 masked Q0 DQ Q0 Q0 Q0 masked Q0 Q0 Q0 REGE ACT#0 READ#0 READ#0 READ#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 49 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Power Down 0 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 CLK /CS /RAS /CAS /WE Standby Power Down Active Power Down CKE CKE latency=1 DQM A0-9 X A10 X A11 X BA0,1 0 DQ REGE Precharge All ACT#0 Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 50 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM CLK Suspend @BL=4 CL=3 1 0 2 3 5 4 BL=4,Buffer mode(REGE="L") 7 6 9 8 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 CKE latency=1 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y 0 0 D0 DQ D0 D0 D0 Q0 Q0 Q0 Q0 REGE ACT#0 READ#0 WRITE#0 CLK suspended CLK suspended Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 51 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM CLK Suspend @BL=4 CL=3 1 0 2 3 5 4 6 BL=4,Latch mode(REGE="H") 7 9 8 10 11 12 13 15 14 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=2 CKE latency=2 DQM A0-9 X A10 X A11 X BA0,1 0 Y Y 0 0 D0 DQ D0 D0 D0 Q0 Q0 Q0 Q0 REGE ACT#0 READ#0 WRITE#0 CLK suspended CLK suspended Italic parameter indicates minimum case MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 52 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Serial Presence Detect Table I Byte Function described SPD enrty data SPD DATA(hex) 0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 0B 4 # Column Addresses on this assembly A0-A10 5 # Module Banks on this assembly 1BANK 01 6 Data Width of this assembly... x72 48 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 10ns A0 6ns 60 ECC 02 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). Cycle time for CL=3 10 SDRAM Access from Clock tAC for CL=3 11 DIMM Configuration type (Non-parity,Parity,ECC) 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x4 04 14 Error Checking SDRAM data width x4 04 Minimum Clock Delay,Back to Back Random Column Addresses 1 01 16 Burst Lengths Supported 1/2/4/8/Full page 8F 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency 2/3 06 19 20 CS# Latency Write Latency 0 0 01 01 21 SDRAM Module Attributes buffered,registered 1F SDRAM Device Attributes:General Precharge All,Auto precharge Write1/Read Burst 0E -7 10ns A0 -8 13ns D0 -7 6ns 60 15 22 23 SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2 24 SDRAM Access form Clock(2nd highest CAS latency) tAC for CL=2 -8 7ns 70 25 SDRAM Cycle time(3rd highest CAS latency) N/A 00 26 SDRAM Access form Clock(3rd highest CAS latency) N/A 00 27 Precharge to Active Minimum 20ns 14 28 Row Active to Row Active Min. 20ns 14 29 RAS to CAS Delay Min 20ns 14 30 Active to Precharge Min 50ns 32 MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 53 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Serial Presence Detect Table II 31 Density of each bank on module 256MByte 40 Command and Address signal input setup time 2ns 20 33 Command and Address signal input hold time 1ns 10 34 Data signal input setup time 2ns 20 35 Data signal input hold time 1ns 10 32 36-61 Superset Information (may be used in future) option 00 62 SPD Revision rev 1.2A 12 63 Checksum for bytes 0-62 Check sum for -7 60 Check sum for -8 A0 64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF 72 Manufacturing location Miyoshi,Japan 01 Tajima,Japan 02 NC,USA 03 Germany 04 MH32S72AQJA-7 4D48333253373241514A412D372020202020 MH32S72AQJA-8 4D48313653373241514A412D382020202020 Revision Code PCB revision rrrr Manufacturing date 73-90 Manufactures Part Number 91-92 93-94 year/week code yyww 95-98 Assembly Serial Number serial number ssssssss 99-125 Manufacture Specific Data option 00 126 Intetl specification frequency 100MHz 64 127 Intel specification CAS# Latency support 128+ Unused storage locations MIT-DS-0371-0.2 -7 CL=2/3,AP,CK0 8F -8 CL=3,AP,CK0 8D 00 open MITSUBISHI ELECTRIC 17/Mar./2000 54 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM 133.35 3 8.89 6.35 11.43 1.27 6.35 36.83 24.495 54.61 42.18 127.35 3 43.18 3.9Max 1.27 MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000 55 Preliminary Spec. MITSUBISHI LSIs Some contents are subject to change without notice. MH32S72AQJA-7, -8 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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MIT-DS-0371-0.2 MITSUBISHI ELECTRIC 17/Mar./2000