4A CY2254A Pentium® Processor Compatible Clock Synthesizer/Driver Features • Multiple clock outputs to meet requirements of most Pentium® motherboards — Four pin-selectable CPU clocks @ 66.66 MHz, 60.0 MHz, and 50.0 MHz for support of Intel Triton™ PCIset based PC — 55.0 MHz pin-selectable CPU clock also available (−2 option only) — Six PCI clocks at 1/2 CPU Clock frequency — One I/O clock @ 24 MHz — One Keyboard Controller clock @ 12 MHz (−1 option) or one Universal Serial Bus clock @ 48 MHz (−2 option) — Two Ref. clocks @ 14.318 MHz • • • • • Freq. stability = 0.01% (max.) Output duty cycle 45% min. to 55% max. Test mode support (−1 option only) 3.3V or 5.0V operation Internal pull-up resistors on S0, S1, and OE inputs Functional Description The CY2254A is a Clock Synthesizer/Driver that provides the multiple clocks required for a Pentium-based PC. The CY2254A has low-skew outputs (< 250 ps between the CPU Clocks, < 250 ps between the PCI Clocks). In addition, the CY2254A CPU clock outputs have less than 200 ps cycle-to-cycle jitter. Finally, both the PCI and CPU clock outputs meet the 1 V/ns slew rate requirement of a Pentium processor-based system. The CY2254A accepts a 14.318 MHz reference signal as its input. The CY2254A has 2 PLLs, one of which generates the CPU and PCI clocks, and the other generates the I/O and Keyboard Controller or USB clocks. The CY2254A runs off either a 3.3V or 5V supply. — Ref. 14.318 MHz Xtal oscillator input • CPU clock jitter < 200 ps cycle-to-cycle • Low skew outputs — < 250 ps between CPU clocks — < 250 ps between PCI clocks — < 500 ps between CPU and PCI clocks (−2 option) — CPU clock leads PCI clock by +1 ns min. to +4 ns max. (−1 option) The CY2254A is available in two options. The −1 option supports the Intel Triton PCIset and provides a 12 MHz keyboard clock on pin 25. The −2 option provides a 48 MHz USB clock on pin 25 and supports the Cyrix® M1 processor. Pin Configuration Logic Block Diagram REF0 (14.318 MHz) Top View SOIC REF1 (14.318 MHz) ÷2 SYS PLL XTALIN XTALOUT ÷2 14.318 MHz OSC. KBDCLK (12 MHz) VDD XTALIN XTALOUT 1 2 3 28 27 26 REF0 REF1 VDD VSS OE CPUCLK0 CPUCLK1 VDD CPUCLK2 CPUCLK3 VSS S1 4 5 6 7 8 9 10 11 12 25 24 23 22 21 20 19 18 17 SEEBELOW IOCLK VSS PCICLK2 PCICLK3 VDD PCICLK4 PCICLK5 VSS 13 14 16 15 PCICLK1 PCICLK0 IOCLK (24 MHz) USBCLK (48 MHz) CPU PLL CPUCLK0 CPUCLK1 ROM CPUCLK2 CPUCLK3 S0 ÷2 S1 −1 option only S0 VDD DELAY PCICLK0 PCICLK1 OPTION PCICLK2 −1 PCICLK3 PIN 25 KBDCLK 12 MHz −2 PCICLK4 USBCLK 48 MHz PCICLK5 OE Intel and Pentium are registered trademarks of Intel Corporation. Triton is a trademark of Intel Corporation. Cyrix is a registered trademark of Cyrix Corporation. Cypress Semiconductor Corporation Document #: 38-07203 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY2254A Pin Summary −1 Name −2 Description VDD 1 1 Voltage supply XTALIN[1] 2 2 Reference crystal input XTALOUT[1] 3 3 Reference crystal feedback VSS 4 4 Ground OE 5 5 Output Enable, Active HIGH (internal pull-up resistor to VDD) CPUCLK0 6 6 CPU clock output CPUCLK1 7 7 CPU clock output VDD 8 8 Voltage supply CPUCLK2 9 9 CPU clock output CPUCLK3 10 10 CPU clock output VSS 11 11 Ground S1 12 12 CPU clock select input, bit 1 (internal pull-up resistor to VDD) S0 13 13 CPU clock select input, bit 0 (internal pull-up resistor to VDD) VDD 14 14 Voltage supply PCICLK0 15 15 PCI clock output PCICLK1 16 16 PCI clock output VSS 17 17 Ground PCICLK5 18 18 PCI clock output PCICLK4 19 19 PCI clock output VDD 20 20 Voltage supply PCICLK3 21 21 PCI clock output PCICLK2 22 22 PCI clock output VSS 23 23 Ground IOCLK 24 24 I/O clock output (24 MHz) KBDCLK 25 USBCLK Keyboard controller clock output (12 MHz) 25 Universal Serial Bus clock output (48 MHz) VDD 26 26 Voltage supply REF1 27 27 Reference clock output (14.318 MHz) REF0 28 28 Reference clock output (14.318 MHz) Function Table Option XTALIN CPUCLK PCICLK Ref. Clock Output OE S0 S1 −1,−2 0 X X 14.318 MHz High-Z High-Z High-Z −1,−2 1 0 0 14.318 MHz 50.0 MHz 25.0 MHz −1,−2 1 0 1 14.318 MHz 60.0 MHz −1,−2 1 1 0 IOCLK USBCLK −2 only High-Z High-Z 14.318 MHz 24 MHz 12 MHz 48 MHz 30.0 MHz 14.318 MHz 24 MHz 12 MHz 48 MHz 14.318 MHz 66.66 MHz 33.33 MHz 14.318 MHz 24 MHz 12 MHz 48 MHz TCLK/4 TCLK TCLK/8 27.5 MHz 14.318 MHz 24 MHz −1 1 1 1 TCLK[2] −2 1 1 1 14.318 MHz 55.0 MHz TCLK/2 High-Z KBDCLK −1 only TCLK/4 48 MHz Notes: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 17 pF. 2. TCLK is a test clock on XTALIN (pin 2) during test mode. Document #: 38-07203 Rev. *A Page 2 of 8 CY2254A PCI Clock Driver Strength Requirements Maximum Ratings • Matched impedances on both rising and falling edges on the output drivers • Output impedance: 25Ω (typical) measured at 1.5V • Maximum output impedance: 40Ω measured at 1.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage........................................................−0.5 to +7.0V Input Voltage ................................................. −0.5V to VDD + 0.5 Storage Temperature (Non-Condensing) .... −65°C to +150°C CPU Clock Driver Strength Requirements Junction Temperature............................................... +150°C • Matched impedances on both rising and falling edges on the output drivers • Output impedance: 25Ω (typical) measured at 1.5V • Maximum output impedance: 40Ω measured at 1.5V Package Power Dissipation.............................................. 1W Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015) Operating Conditions[3] Parameter Description VDD Supply Voltage 3.3V Supply Voltage 5.0V TA Operating Ambient Temperature CL Max. Capacitive Load on CPUCLK PCICLK IOCLK KBDCLK / USBCLK REF0 REF1 f(REF) Reference Frequency, Oscillator Nominal Value tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. Max. Unit 3.135 4.5 3.6 5.5 V V 0 70 °C pF 20 30 20 20 30 15 14.318 14.318 MHz 0.05 50 ms Electrical Characteristics VDD = 3.135V − 3.6V, or 5.0V ±10%, TA = 0°C to +70°C Parameter Description Test Conditions VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs VOH[4] High-level Output Voltage VDD = VDD Min. VOL[4] IIH IIL Low-level Output Voltage Input High Current Input Low Current VDD = VDD Min. Max. 2.0 CPUCLK IOH = 12 mA PCICLK, REF0 IOH = 4 mA KBDCLK, USBCLK IOH = 8 mA REF1 IOL = 6 mA CPUCLK IOL = 12 mA PCICLK, REF0 IOL = 4 mA KBDCLK, USBCLK IOL = 8 mA REF1 Unit V 0.8 IOH = 6 mA 2.4 V V 0.4 V VIH = VDD, VDD = 3.3V 5 µA VIH = VDD, VDD = 5.0V 10 µA VIL = 0 V, VDD = 3.3V 100 µA VIL = 0 V, VDD = 5.0V 250 µA IOZ Output Leakage Current Three-state IDD Power Supply Current VDD = 3.6V, VIN = 0 or VDD VDD = 5.5V, VIN = 0 or VDD Document #: 38-07203 Rev. *A Min. −10 +10 µA 90 150 mA mA Page 3 of 8 CY2254A Electrical Characteristics VDD = 3.135V − 3.6V, or 5.0V ±10%, TA = 0°C to +70°C (continued) Parameter Description Test Conditions Min. Max. Unit Min. Max. Unit 45% 55% Notes: 3. Electrical parameters are guaranteed with these operating conditions. 4. Guaranteed by design, not tested. Switching Characteristics[5] Parameter Output Name Description [6] t1 = t1A ÷ t1B t1 All Output Duty Cycle t2[4] CPUCLK, PCICLK Output Rising and Falling Edge Rate Measured between 0.4 and 2.4V t3[4] REF, KBDCLK, USBCLK Rise Time Measured between 0.4 and 2.4V 4 ns t4[4] t5[4] t6[4] t7[4] REF, KBDCLK, USBCLK Fall Time Measured between 2.4 and 0.4V 4 ns CPUCLK CPU-CPU Clock Skew Measured at 1.5V 250 ps PCICLK PCI-PCI Clock Skew Measured at 1.5V 250 ps CPUCLK, PCICLK CPU-PCI Skew Measured at 1.5V (−1 option) 4 ns 500 ps 200 ps Measured at 1.5V (−2 option) t8[4] CPUCLK Cycle-Cycle Clock Jitter CPU Clock Jitter 1 1 V/ns Switching Waveforms Duty Cycle Timing t1B t1A 1.5V 1.5V 1.5V All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V t2 t3 Document #: 38-07203 Rev. *A 2.4V 0.4V 3.3V 0V t2 t4 Page 4 of 8 CY2254A Switching Waveforms (continued) Clock Skew 1.5V CPUCLK/ PCICLK 1.5V t5 t6 Notes: 5. All parameters specified with outputs fully loaded. 6. Duty cycle is measured at 1.5V. Document #: 38-07203 Rev. *A Page 5 of 8 CY2254A Switching Waveforms (continued) CPU-PCI Clock Skew CPUCLK 1.5V 1.5V PCICLK t7 Test Circuit VDD 1 26 0.1 µF 0.1 µF VDD 4 23 8 20 0.1 µF 0.1 µF 11 17 14 OUTPUTS 0.1 µF CLOAD Note: All capacitors should be placed as close to each pin as possible. Ordering Information Ordering Code Package Name Package Type Operating Range CY2254ASC−1 S21 28-Pin SOIC Commercial CY2254ASC−2 S21 28-Pin SOIC Commercial Document #: 38-07203 Rev. *A Page 6 of 8 CY2254A Package Diagram 28-Lead (300-Mil) Molded SOIC S21 51-85026-A Document #: 38-07203 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2254A Document Title: CY2254A Pentium® Processor Compatible Clock Synthesizer/Driver Document Number: 38-07203 ECN NO. Issue Date Orig. of Change ** 111723 12/15/01 DSG Change from Spec number: 38-00504 to 38-07203 *A 121838 12/14/02 RBI Power up requirements added to Operating Conditions Information REV. Document #: 38-07203 Rev. *A Description of Change Page 8 of 8