KIT ATION EVALU E L B AVAILA 19-2727; Rev 2; 6/04 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization Features The MAX3786 is an AC-coupled, serial-ATA (SATA)compatible, 1.5Gbps multiplexer/buffer (mux/buffer) IC that provides the capability to switch a single serial data signal between two redundant I/O channels. SATA out-of-band (OOB) signaling is supported using loss-of-signal (LOS) detect on all three inputs and shutdown on the corresponding outputs. The high-speed inputs and outputs are all internally terminated, compatible with 100Ω differential systems, and must be AC-coupled to the controller IC and SATA-compatible disk drive. ♦ < 50psP-P Total Residual Jitter (20in FR-4, EQ and PE On) ♦ Supports SATA OOB Signaling ♦ Loopback of Nonselected Channel ♦ Receive Equalization and Transmit Preemphasis on Controller-Side I/O Channels ♦ 0°C to +85°C Operation ♦ 32-Pin, 5mm ✕ 5mm Thin QFN Package Receive equalization (EQ) and transmit preemphasis (PE) are provided on the dual I/O channels to mitigate the effects of intersymbol interference in the signal path. Loopback can be enabled on the nonselected I/O channel. The MAX3786 operates from a single +3.3V supply and typically consumes 520mW with PE and EQ enabled. It is available in a 5mm x 5mm, 32-lead thin QFN exposed-pad package and operates over a 0°C to +85°C temperature range. ♦ +3.3V Power Supply Ordering Information PART Applications TEMP RANGE PIN-PACKAGE PKG CODE MAX3786UTJ 0°C to +85°C 32 Thin QFN-EP* (5mm × 5mm) T3255-2 MAX3786UTJ+ 0°C to +85°C 32 Thin QFN-EP* (5mm × 5mm) — +Denotes lead-free package. *EP = Exposed pad. 1.5Gbps Serial ATA Redundancy OUT1 IN1 RX MAX3786 TX CONNECTOR CONNECTOR OUT0 IN0 SATA CONNECTOR CONTROLLER 1 2in TO 24in FR-4 SATA CONNECTOR CONNECTOR CONNECTOR Typical Application Circuit DISK DRIVE 2in TO 24in FR-4 CONTROLLER 2 Pin Configuration and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3786 General Description MAX3786 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization ABSOLUTE MAXIMUM RATINGS Voltage at PE1EN, PE0EN, EQ1EN, EQ0EN, LB_EN, SEL, CM1, CM0 .........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 32-Pin Thin QFN (derate 21.3mW/°C above +85°C) .1384mW Operating Temperature Range ....................………0°C to +85°C Storage Temperature Range .......................…..-55°C to +150°C Lead Temperature (soldering, 10s) .............……………..+300°C Supply Voltage, VCC ...................................……...-0.5V to +5.0V Continuous Current at Outputs (TX±, OUT1±, OUT0±)............................………………±22mA Input Voltage (RX±, IN1±, IN0±) ..................................-0.5V to (VCC + 0.5V) Differential Input Voltage (RX±, IN1±, IN0±) ...................................………………..±2.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER Supply Current SYMBOL ICC TYP 125 MAX EQ and PE off CONDITIONS MIN EQ and PE on 158 220 Maximum Data Rate (Note 1) 1.5 Differential Input Voltage (RX, IN1, IN0) (Note 2) 250 Input Termination Differential 85 Input Return Loss |S11| UNITS mA Gbps 100 100MHz to 2.5GHz 14 Input Equalization At 750MHz 4.5 Differential Output Voltage (TX, OUT0, OUT1) (Note 2) PE off 400 150 500 Output disabled by OOB signaling 600 mVP-P 115 Ω dB dB 600 30 mVP-P Output Termination Single ended to VCC 42.5 50 57.5 Ω Output Transition Time 1.5Gbps data, 20% to 80% (Notes 1, 3) 135 200 270 ps Output Preemphasis At 750MHz (Note 4) 4.5 Output Jitter DJ + 14RJ, EQ and PE off (Notes 1, 5, 8) 30 40 psP-P Total Residual Jitter DJ + 14RJ, EQ and PE on (Notes 1, 6, 8) 40 50 psP-P Differential Output Skew (Note 1) LOS Detector Threshold 50 Output Startup/Shutdown Time LVCMOS Input High Voltage 2 (Note 7) VIH 1.5 _______________________________________________________________________________________ dB 20 ps 150 mVP-P 5 ns V 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization (VCC = +3.0V to +3.6V, TA = 0°C to +85°C. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS Input Low Voltage VIL 0.5 V LVCMOS Input High Current IOH VIH = +2.0V to (VCC + 0.3V) 150 µA LVCMOS Input Low Current IOL VIL = -0.3V to +0.8V 150 µA AC specifications are guaranteed by design and characterization. Differential voltage is defined as VP-P = (V+ - V-). Inputs and outputs must be AC-coupled for proper operation. Output transition time measured using a 0000011111 pattern, with transmit PE off. Transmit PE compensates for 20in of 6-mil-wide differential stripline in FR-4 or equivalent path loss. Jitter after paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a ±K28.5 pattern, and a path consisting of the MAX3786 alone. Note 6: Jitter after EQ for the paths from RX to OUT_ or IN_ to TX. Measured with no jitter on the input, using a ±K28.5 pattern, and a path consisting of the MAX3786 plus 20in of 6-mil-wide differential stripline in FR-4 on the output. Note 7: Total time for LOS to enable/disable the outputs. Note 8: Measured with a 100mV sinusoidal common-mode signal in the 2MHz ≤ f ≤ 200MHz range. Note 1: Note 2: Note 3: Note 4: Note 5: Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) -10 PE AND EQ ON -15 -20 -25 -30 PE AND EQ OFF -35 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 70 60 50 40 30 20 10 -40 0 80 TOTAL RESIDUAL JITTER (psP-P) 240 220 200 180 160 140 120 100 80 60 40 MAX3786 toc02 MAX3786 toc01 0 -5 |S11| (dB) CURRENT (mA) 280 260 TOTAL RESIDUAL JITTER vs. PATH LENGTH (FR-4 STRIPLINE AT OUT0, ±K28.5 PATTERN) DIFFERENTIAL INPUT RETURN LOSS MAX3786 toc03 SUPPLY CURRENT vs. TEMPERATURE 0 0 0.5 1.0 1.5 FREQUENCY (GHz) 2.0 2.5 0 5 10 15 20 25 30 FR-4 LENGTH (in) _______________________________________________________________________________________ 3 MAX3786 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) OUTPUT SWING vs. INPUT SWING (±K28.5 PATTERN) MAX3786 toc04 600 500 OUTPUT SWING (mVP-P) 400 300 200 100 0 0 100 200 300 400 500 600 INPUT SWING (mVP-P) OUTPUT EYE DIAGRAM, TRANSMIT PE ON (10in FR-4 STRIPLINE AT OUT0, ±K28.5 PATTERN) MAX3786 toc06 MAX3786 toc05 OUTPUT EYE DIAGRAM, RECEIVE EQ ON (10in FR-4 STRIPLINE AT IN0, ±K28.5 PATTERN) 70mV/div 70mV/div 100ps/div OUTPUT EYE DIAGRAM, RECEIVE EQ ON (20in FR-4 STRIPLINE AT IN0, ±K28.5 PATTERN) OUTPUT EYE DIAGRAM, TRANSMIT PE ON (20in FR-4 STRIPLINE AT OUT0, ±K28.5 PATTERN) MAX3786 toc08 100ps/div MAX3786 toc07 MAX3786 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization 70mV/div 70mV/div 100ps/div 4 100ps/div _______________________________________________________________________________________ 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization PIN NAME FUNCTION 1, 4, 8, 15, 17, 20, 21, 24, 26, 30 VCC 2 TX+ Positive TX Data Output, CML. Serial ATA compatible. 3 TX- Negative TX Data Output, CML. Serial ATA compatible. 5 SEL Multiplex Select Control Input, LVCMOS. Set high to connect RX/TX to OUT1/IN1. 6 RX- Negative RX Data Input, CML. Serial ATA compatible. 7 RX+ Positive RX Data Input, CML. Serial ATA compatible. +3.3V Supply Voltage 9 PE1EN 10 EQ1EN Channel 1 Equalization Enable Input, LVCMOS. Set low to enable IN1 EQ. 11 LB_EN Loopback Enable Input, LVCMOS. Set low to loopback data on nonselected channel. 12 CM1 Input 1 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0µF capacitor. See Figure 1. 13 IN1- Negative Channel 1 Data Input, CML. Serial ATA compatible. Positive Channel 1 Data Input, CML. Serial ATA compatible. Channel 1 Preemphasis Enable Input, LVCMOS. Set low to enable OUT1 PE. 14 IN1+ 16, 25 GND 18 OUT1- 19 OUT1+ Positive Channel 1 Data Output, CML. Serial ATA compatible. 22 OUT0- Negative Channel 0 Data Output, CML. Serial ATA compatible. 23 OUT0+ Positive Channel 0 Data Output, CML. Serial ATA compatible. 27 IN0- Negative Channel 0 Data Input, CML. Serial ATA compatible. 28 IN0+ Positive Channel 0 Data Input, CML. Serial ATA compatible. 29 CM0 Input 0 Common-Mode Point. Normally not connected; can be connected to VCC through 1.0µF capacitor. See Figure 1. 31 EQ0EN Supply Ground Negative Channel 1 Data Output, CML. Serial ATA compatible. 32 PE0EN EP Exposed pad Channel 0 Equalization Enable Input, LVCMOS. Set low to enable IN0 EQ. Channel 0 Preemphasis Enable Input, LVCMOS. Set low to enable OUT0 PE. Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. Detailed Description The MAX3786 consists of three multiplexers, I/O buffers, and LOS-detection circuitry (see the Functional Diagram). The buffers on the controller side provide EQ on the inputs and PE on the outputs. Mux/Buffer Logic By means of the LVCMOS input SEL, a SATA-compatible device at TX/RX can be connected to either IN0/OUT0 or IN1/OUT1. When SEL is low, TX/RX are connected to IN0/OUT0, and when SEL is high, TX/RX are connected to IN1/OUT1. Use of the SEL input provides the ability to operate a single SATA disk drive from redundant controllers. Loopback is provided on the IN_/OUT_ side and is controlled by the LVCMOS input LB_EN. When LB_EN is low, the nonselected IN_/OUT_ loops back (see Table 1). The SEL and LB_EN control lines are internally pulled high through 40kΩ resistors (see the Functional Diagram). Loss-of-Signal Logic At each high-speed input to the MAX3786, an LOS circuit is provided. In this circuit, a differential signal of 50mVP-P or less is detected as OFF, and a signal of greater than 150mVP-P is detected as ON. The LOS detectors, in combination with the select logic, control their associated high-speed output-disable circuits, so _______________________________________________________________________________________ 5 MAX3786 Pin Description MAX3786 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization VCC VCC IN_+ MAX3786 50Ω 50Ω OUT_+ 50Ω OUT_- 1.6kΩ VCC CM_ VCC 0.2mA 50Ω 2pF IN_- MAX3786 Figure 1. Input Structure (IN0, IN1) Figure 2. Output Structure (OUT0, OUT1) that OOB signaling is transmitted through the MAX3786 (see Table 1). The time for the LOS circuit to detect an inactive input and disable the associated output, or detect an active input and enable the output, is less than 5ns. Equalization and Preemphasis High-speed inputs IN0 and IN1 have integrated equalization, and high-speed outputs OUT0 and OUT1 have integrated PE to mitigate the effects of intersymbol interference in an FR-4 transmission line signal path. These circuits provide EQ or PE that matches the typical path loss of a 20in, 6-mil FR-4 differential stripline. Four active-low LVCMOS inputs, EQ0EN, EQ1EN, PE0EN, and PE1EN are provided to enable EQ and PE independently. All four control lines are internally pulled high through 40kΩ resistors (see the Functional Diagram). EQ and PE should be enabled when the total path loss exceeds approximately 2.5dB. Input Terminations All high-speed inputs accept current-mode logic (CML) and are SATA compatible. The inputs contain internal 100Ω differential termination, and must be AC-coupled to the controller IC and SATA-compatible disk drive for proper operation. Two pins (CM0 and CM1) provide access to the IN0 and IN1 common-mode points. CM0 and CM1 are normally left unconnected; however, a capacitor up to 1.0µF can be connected from each CM_ pin to VCC, providing a low-impedance AC common-mode path to VCC (see Figure 1). 6 Output Terminations The MAX3786 uses CML for its high-speed outputs. They are SATA compatible and provide 50Ω terminations to VCC (see Figure 2). The high-speed outputs must be AC-coupled to the controller IC and SATAcompatible disk drive for proper operation. Applications Information Hot Swap The MAX3786 is designed so that arbitrary sequencing of VCC and I/O signals during startup does not affect operation of the part. Exposed-Pad Package The MAX3786 is available in a 5mm ✕ 5mm, 32-pin thin QFN package with EP for signal integrity and placement flexibility. The exposed pad provides thermal and electrical connectivity to the IC, and must be soldered to a high-frequency ground plane. It is recommended to use at least nine vias to connect the ground pad underneath the 32-lead thin QFN package to the PC board ground plane. Layout Considerations Use controlled-impedance transmission lines to interface with the MAX3786 high-speed inputs and outputs. Power-supply decoupling capacitors should be placed as close as possible to the VCC pins. _______________________________________________________________________________________ 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786 Table 1. Operation Truth Table INPUT CONTROLS LOSS-OF-SIGNAL DETECT OUTPUT FUNCTION SEL LB_EN LOS_RX LOS_0 LOS_1 TX OUT0 Low Low False False False IN0 RX IN1 Low Low False False True IN0 RX OFF Low Low False True False Off RX IN1 Low Low False True True Off RX Off Low Low True False False IN0 Off IN1 Low Low True False True IN0 Off Off Low Low True True False Off Off IN1 Low Low True True True Off Off Off OUT1 Low High False False X IN0 RX Off Low High False True X Off RX Off Low High True False X IN0 Off Off Low High True True X Off Off Off High Low False False False IN1 IN0 RX High Low False False True Off IN0 RX High Low False True False IN1 Off RX High Low False True True Off Off RX High Low True False False IN1 IN0 Off High Low True False True Off IN0 Off High Low True True False IN1 Off Off High Low True True True Off Off Off High High False X False IN1 Off RX High High False X True Off Off RX High High True X False IN1 Off Off High High True X True Off Off Off SEL = Low connects TX/RX to IN0/OUT0, high connects TX/RX to IN1/OUT1. LOS = True indicates loss of signal. LB_EN = Low enables loopback of nonselected channel. X = Don’t care. _______________________________________________________________________________________ 7 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization MAX3786 Functional Diagram EQ0EN LOS_0 (AND) SEL (OR) LOS_1 (AND) SEL TX 2 2 EQ1EN CML 1 EQ LOS_1 RX IN0 EQ LOS_0 0 2 IN1 PE0EN 2 CML LOS_RX 0 VCC PE (LOS_RX (AND) SEL) (OR) (LB_EN (AND) SEL) (OR) (LOS_0 (AND) SEL (AND) LB_EN) 1 40kΩ SEL OUT0 2 PE1EN 0 VCC MAX3786 VCC 40kΩ PE0EN PE (LOS_RX (AND) SEL) (OR) (LB_EN (AND) SEL) (OR) (LOS_1 (AND) SEL (AND) LB_EN) 1 PE1EN VCC 40kΩ EQ0EN VCC 40kΩ EQ1EN VCC 40kΩ 40kΩ LB_EN PE0EN EQ0EN VCC CMO IN0+ IN0- VCC GND 32 31 30 29 28 27 26 25 Pin Configuration TOP VIEW 1 24 VCC TX+ 2 23 OUT0+ TX- 3 22 OUT0- VCC 4 21 VCC 14 15 16 IN1+ VCC GND VCC 13 OUT1- 17 12 18 8 IN1- 7 VCC CM1 RX+ 11 OUT1+ 10 VCC 19 LB_EN 20 6 EQ1EN 5 RX- 9 SEL PE1EN Chip Information TRANSISTOR COUNT: 2848 PROCESS: SiGe BiCMOS VCC MAX3786 OUT1 2 QFN* *THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. 8 _______________________________________________________________________________________ 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization QFN THIN.EPS D2 D b C L 0.10 M C A B D2/2 D/2 k L MARKING XXXXX E/2 E2/2 C L (NE-1) X e E DETAIL A PIN # 1 I.D. E2 PIN # 1 I.D. 0.35x45∞ e (ND-1) X e DETAIL B e L1 L C L C L L L e e 0.10 C A C 0.08 C A1 A3 PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm -DRAWING NOT TO SCALE- 21-0140 G 1 2 _______________________________________________________________________________________ 9 MAX3786 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3786 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) COMMON DIMENSIONS EXPOSED PAD VARIATIONS PKG. 20L 5x5 28L 5x5 32L 5x5 16L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 A3 b D E L1 0 0.02 0.05 0 0.20 REF. 0.20 REF. 0.02 0.05 0 0.20 REF. 0.02 0.05 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.65 BSC. 0.80 BSC. e k L 0.02 0.05 0.50 BSC. 0.50 BSC. - 0.25 - 0.25 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 - - - - - N ND NE 16 4 4 20 5 5 JEDEC WHHB WHHC - - - - - 28 7 7 WHHD-1 - - 32 8 8 WHHD-2 NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. D2 L E2 PKG. CODES MIN. NOM. MAX. MIN. NOM. MAX. ±0.15 T1655-1 T1655-2 T1655N-1 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 3.10 3.20 T2055-2 T2055-3 T2055-4 3.00 3.00 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.10 3.20 3.10 3.20 ** ** ** ** T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 ** ** 0.40 DOWN BONDS ALLOWED NO YES NO NO YES NO Y ** NO NO YES YES NO ** ** 0.40 ** ** ** ** ** NO YES Y N NO YES NO NO ** ** ** ** ** SEE COMMON DIMENSIONS TABLE 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. -DRAWING NOT TO SCALE- PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm 21-0140 G 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.